Open
Description
How to reproduce:
- Set QOI_FPGA_ENCODER_POST_CYCLES = 0 so verilator_shim does not compensate for this effect
- perhaps comment out all ops in the verilog except QOI_OP_RGB, so it's more visible
Note how everything's shifted over by 1 cycle, so the last pixel is missing. How come the upstream decoder is still ok with this? How does it manage to make up the last 0xffffff on testcard.qoi
?