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Upstream qoi decoder seems fine if stream ends early, investigate #1

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@amstan

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@amstan

How to reproduce:

  • Set QOI_FPGA_ENCODER_POST_CYCLES = 0 so verilator_shim does not compensate for this effect
  • perhaps comment out all ops in the verilog except QOI_OP_RGB, so it's more visible

Note how everything's shifted over by 1 cycle, so the last pixel is missing. How come the upstream decoder is still ok with this? How does it manage to make up the last 0xffffff on testcard.qoi?

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