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Copy pathCsComputeLibraryPayload.lgc
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CsComputeLibraryPayload.lgc
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; Define a compute library that can be called from a compute shader.
; Ensure that the first argument uses the same registers as the return value.
; The assembly should not have any movs of vector registers.
; RUN: lgc -mcpu=gfx1010 -o - - <%s | FileCheck --check-prefixes=CHECK %s
; ModuleID = 'lgcPipeline'
target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-ni:7"
target triple = "amdgcn--amdpal"
; Function Attrs: nounwind
define spir_func <10 x i32> @func(<10 x i32> %arg) local_unnamed_addr #0 !lgc.shaderstage !7 {
; CHECK-LABEL: func:
; CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_waitcnt_vscnt null, 0x0
; CHECK: s_getpc_b64 s[{{[0-9]+:[0-9]+}}]
; CHECK: s_mov_b32 s9, s{{[0-9]+}}
; CHECK-NEXT: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}}
; CHECK-NEXT: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[8:9], 0x0
; CHECK: v_mov_b32_e32 v12, s{{[0-9]+}}
; CHECK: s_waitcnt lgkmcnt(0)
; CHECK-NEXT: buffer_store_dwordx3 v[{{[0-9]+:[0-9]+}}], off, s[{{[0-9]+:[0-9]+}}], 0
; CHECK: s_waitcnt_vscnt null, 0x0
; CHECK-NEXT: s_setpc_b64 s[30:31]
.entry:
%id = call <3 x i32> @lgc.shader.input.LocalInvocationId(i32 0)
%buf = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 2, i32 0, i32 2)
%buf2 = bitcast i8 addrspace(7)* %buf to <3 x i32> addrspace(7)*
store <3 x i32> %id, <3 x i32> addrspace(7)* %buf2, align 4
ret <10 x i32> %arg
}
declare <3 x i32> @lgc.shader.input.LocalInvocationId(i32) #1
; Function Attrs: nounwind readonly
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #1
attributes #0 = { nounwind }
attributes #1 = { nounwind readonly }
!llpc.compute.mode = !{!0}
!lgc.options = !{!1}
!lgc.options.CS = !{!2}
!lgc.user.data.nodes = !{!3, !4, !5, !6}
!0 = !{i32 2, i32 3, i32 1}
!1 = !{i32 2113342239, i32 1385488414, i32 -1007072744, i32 -815526592, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 2}
!2 = !{i32 1792639877, i32 1348715323, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 64, i32 0, i32 0, i32 3}
!3 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
!4 = !{!"DescriptorBuffer", i32 4, i32 16, i32 0, i32 1, i32 4}
!5 = !{!"DescriptorTableVaPtr", i32 20, i32 1, i32 1}
!6 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 2, i32 4}
!7 = !{i32 7}