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CsBuiltIns.lgc
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; BEGIN_LGC_TEST
; ----------------------------------------------------------------------
; Extract 1: DeviceIndex test, DeviceIndex from pipeline state
; RUN: lgc -extract=1 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK1 %s
; CHECK1-LABEL: _amdgpu_cs_main:
; CHECK1: v_mov_b32_e32 [[REG:v[0-9]+]], 0xbc614e
; CHECK1: buffer_store_dword [[REG]],
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 4438, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!lgc.device.index = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; DeviceIndex
!3 = !{i32 12345678}
; ----------------------------------------------------------------------
; Extract 2: DeviceIndex test, reloc in unlinked shader
; RUN: lgc -extract=2 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK2 %s
; CHECK2-LABEL: _amdgpu_cs_main:
; CHECK2: v_mov_b32_e32 [[REG:v[0-9]+]], ($deviceIdx)@abs32@lo
; CHECK2: buffer_store_dword [[REG]],
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 4438, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.unlinked = !{!1}
; ShaderStageCompute
!0 = !{i32 7}
; DeviceIndex
!1 = !{i32 1}
; ----------------------------------------------------------------------
; Extract 3: WorkgroupSize test, from shader mode
; RUN: lgc -extract=3 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK3 %s
; CHECK3-LABEL: _amdgpu_cs_main:
; CHECK3: v_mov_b32_e32 v0, 5
; CHECK3: v_mov_b32_e32 v1, 6
; CHECK3: v_mov_b32_e32 v2, 7
; CHECK3: buffer_store_dwordx3 v[0:2],
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 25, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
ret void
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; Compute mode, containing workgroup size
!3 = !{i32 5, i32 6, i32 7}
; ----------------------------------------------------------------------
; Extract 4: NumWorkgroups test, from value pointed to by special user data entry
; RUN: lgc -extract=4 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK4 %s
; CHECK4-LABEL: _amdgpu_cs_main:
; CHECK4: s_load_dwordx4 s{{\[}}[[SREGNUM:[0-9]+]]:{{[0-9]+}}], s[2:3]
; CHECK4: v_mov_b32_e32 v0, s[[SREGNUM]]
; CHECK4: buffer_store_dwordx3 v[0:2],
; CHECK4: COMPUTE_USER_DATA_2): 0x10000006
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 24, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
ret void
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; ----------------------------------------------------------------------
; Extract 5: WorkgroupId test, from three SGPRs set up by hardware
; RUN: lgc -extract=5 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK5 %s
; CHECK5-LABEL: _amdgpu_cs_main:
; CHECK5-DAG: v_mov_b32_e32 v0, s{{[0-9]*}}
; CHECK5-DAG: v_mov_b32_e32 v1, s{{[0-9]*}}
; CHECK5-DAG: v_mov_b32_e32 v2, s{{[0-9]*}}
; CHECK5: buffer_store_dwordx3 v[0:2],
; rsrc2 bits 7,8,9 need to be set to enable the three WorkgroupId SGPRs
; CHECK5: COMPUTE_PGM_RSRC2): 0x{{[0-9a-f]*[7f][89a-f][0-9a-f]$}}
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 26, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
ret void
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; ----------------------------------------------------------------------
; Extract 6: LocalInvocationId test, from three VGPRs set up by hardware
; RUN: lgc -extract=6 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK6 %s
; CHECK6-LABEL: _amdgpu_cs_main:
; CHECK6-NOT: v0
; CHECK6-NOT: v1
; CHECK6-NOT: v2
; CHECK6: buffer_store_dwordx3 v[0:2],
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 27, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
ret void
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; Compute mode, containing workgroup size
!3 = !{i32 5, i32 6, i32 7}
; ----------------------------------------------------------------------
; Extract 7: SubgroupSize, constant 32 or 64
; RUN: lgc -extract=7 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK7,CHECK7_WAVE64 %s
; RUN: lgc -extract=7 -mcpu=gfx1010 %s -o - | FileCheck --check-prefixes=CHECK7,CHECK7_WAVE32 %s
; CHECK7-LABEL: _amdgpu_cs_main:
; CHECK7_WAVE64: v_mov_b32_e32 v0, 64
; CHECK7_WAVE32: v_mov_b32_e32 v0, 32
; CHECK7: buffer_store_dword v0,
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 36, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; ----------------------------------------------------------------------
; Extract 8: SubgroupLocalInvocationId, from v_mbcnt instruction(s)
; RUN: lgc -extract=8 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK8,CHECK8_WAVE64 %s
; RUN: lgc -extract=8 -mcpu=gfx1010 %s -o - | FileCheck --check-prefixes=CHECK8,CHECK8_WAVE32 %s
; CHECK8-LABEL: _amdgpu_cs_main:
; CHECK8: v_mbcnt_lo_u32_b32{{[^ ]*}} v0, -1, 0
; CHECK8_WAVE32-NOT: v_mbcnt_hi
; CHECK8_WAVE64: v_mbcnt_hi_u32_b32{{[^ ]*}} v0, -1, v0
; CHECK8: buffer_store_dword v0,
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 41, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; ----------------------------------------------------------------------
; Extract 9: NumSubgroups, constant calculated from WorkgroupSize and wave size
; RUN: lgc -extract=9 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK9,CHECK9_WAVE64 %s
; RUN: lgc -extract=9 -mcpu=gfx1010 %s -o - | FileCheck --check-prefixes=CHECK9,CHECK9_WAVE32 %s
; CHECK9-LABEL: _amdgpu_cs_main:
; CHECK9_WAVE64: v_mov_b32_e32 v0, 4
; CHECK9_WAVE32: v_mov_b32_e32 v0, 7
; CHECK9: buffer_store_dword v0,
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 38, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; Compute mode, containing workgroup size
!3 = !{i32 5, i32 6, i32 7}
; ----------------------------------------------------------------------
; Extract 10: GlobalInvocationId test, from WorkgroupId * WorkgroupSize + LocalInvocationId
; WorkgroupId is in three SGPRs set by hardware
; WorkgroupSize is constant from shader mode
; LocalInvocationId is in three VGPRs set by hardware
; RUN: lgc -extract=10 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK10 %s
; CHECK10-LABEL: _amdgpu_cs_main:
; CHECK10: s_mov_b32 [[INPUT0:s[0-9]+]], s3
; CHECK10: s_mul_i32 [[PRODUCT0:s[0-9]+]], [[INPUT0]], 5
; CHECK10: s_mul_i32 [[PRODUCT1:s[0-9]+]], s4, 6
; CHECK10: s_mul_i32 [[PRODUCT2:s[0-9]+]], s5, 7
; CHECK10: v_add_u32_e32 v0, vcc, [[PRODUCT0]], v0
; CHECK10: v_add_u32_e32 v1, vcc, [[PRODUCT1]], v1
; CHECK10: v_add_u32_e32 v2, vcc, [[PRODUCT2]], v2
; CHECK10: buffer_store_dwordx3 v[0:2],
; rsrc2 bits 7,8,9 need to be set to enable the three WorkgroupId SGPRs
; CHECK10: COMPUTE_PGM_RSRC2): 0x{{[0-9a-f]*[7f][89a-f][0-9a-f]$}}
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call <3 x i32> (...) @lgc.create.read.builtin.input.v3i32(i32 28, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to <3 x i32> addrspace(7)*
store <3 x i32> %1, <3 x i32> addrspace(7)* %2, align 4
ret void
}
declare <3 x i32> @lgc.create.read.builtin.input.v3i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; Compute mode, containing workgroup size
!3 = !{i32 5, i32 6, i32 7}
; ----------------------------------------------------------------------
; Extract 11: LocalInvocationIndex test, linearized from LocalInvocationId and WorkgroupSize
; LocalInvocationId from three VGPRs set up by hardware
; RUN: lgc -extract=11 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK11 %s
; CHECK11-LABEL: _amdgpu_cs_main:
; CHECK11: v_mul_lo_u32 [[VAL1:v[0-9]+]], v2, 6
; CHECK11: v_add_u32_e32 [[VAL2:v[0-9]+]], vcc, [[VAL1]], v1
; CHECK11: v_mul_lo_u32 [[VAL3:v[0-9]+]], [[VAL2]], 5
; CHECK11: v_add_u32_e32 [[VAL4:v[0-9]+]], vcc, [[VAL3]], v0
; CHECK11: buffer_store_dword [[VAL4]],
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 29, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; Compute mode, containing workgroup size
!3 = !{i32 5, i32 6, i32 7}
; ----------------------------------------------------------------------
; Extract 12: SubgroupId, calculated as LocalInvocationIndex divided by wave size
; LocalInvocationIndex linearized from LocalInvocationId and WorkgroupSize
; LocalInvocationId from three VGPRs set up by hardware
; RUN: lgc -extract=12 -mcpu=gfx802 %s -o - | FileCheck --check-prefixes=CHECK12,CHECK12_WAVE64,CHECK12_CO %s
; RUN: lgc -extract=12 -mcpu=gfx1010 %s -o - | FileCheck --check-prefixes=CHECK12,CHECK12_WAVE32,CHECK12_NC %s
; CHECK12-LABEL: _amdgpu_cs_main:
; CHECK12: v_mul_lo_u32 [[VAL1:v[0-9]+]], v2, 6
; CHECK12_CO: v_add_u32_e32 [[VAL2:v[0-9]+]], vcc, [[VAL1]], v1
; CHECK12_NC: v_add_nc_u32_e32 [[VAL2:v[0-9]+]], [[VAL1]], v1
; CHECK12: v_mul_lo_u32 [[VAL3:v[0-9]+]], [[VAL2]], 5
; CHECK12_CO: v_add_u32_e32 [[VAL4:v[0-9]+]], vcc, [[VAL3]], v0
; CHECK12_NC: v_add_nc_u32_e32 [[VAL4:v[0-9]+]], [[VAL3]], v0
; CHECK12_WAVE32: v_lshrrev_b32_e32 [[VAL5:v[0-9]+]], 5, [[VAL4]]
; CHECK12_WAVE64: v_lshrrev_b32_e32 [[VAL5:v[0-9]+]], 6, [[VAL4]]
; CHECK12: buffer_store_dword [[VAL5]],
define dllexport spir_func void @lgc.shader.CS.main() local_unnamed_addr #0 !lgc.shaderstage !0 {
.entry:
%0 = call i8 addrspace(7)* (...) @lgc.create.load.buffer.desc.p7i8(i32 0, i32 0, i32 0, i32 2)
%1 = call i32 (...) @lgc.create.read.builtin.input.i32(i32 40, i32 0, i32 undef, i32 undef)
%2 = bitcast i8 addrspace(7)* %0 to i32 addrspace(7)*
store i32 %1, i32 addrspace(7)* %2, align 4
ret void
}
declare i32 @lgc.create.read.builtin.input.i32(...) local_unnamed_addr #0
declare i8 addrspace(7)* @lgc.create.load.buffer.desc.p7i8(...) local_unnamed_addr #0
attributes #0 = { nounwind }
!lgc.user.data.nodes = !{!1, !2}
!llpc.compute.mode = !{!3}
; ShaderStageCompute
!0 = !{i32 7}
; type, offset, size, count
!1 = !{!"DescriptorTableVaPtr", i32 2, i32 1, i32 1}
; type, offset, size, set, binding, stride
!2 = !{!"DescriptorBuffer", i32 0, i32 4, i32 0, i32 0, i32 4}
; Compute mode, containing workgroup size
!3 = !{i32 5, i32 6, i32 7}
; END_LGC_TEST