GateMate Support With Amaranth

[TarikHamedovic]

I am currently working on a board with a GateMate FPGA chip, but there is no GateMate toolchain for Amaranth, nor the board in question. GateMate uses yosys, nextpnr and openFPGALoader.
Is it possible for me to write the toolchain support for Amaranth and the board definition, if so how would I do that?

[whitequark]

Yes. Take a look at one of the existing platforms, e.g. amaranth/vendor/_quicklogic.py. I would be happy to have GateMate support upstream, but for that I will need a GateMate board.

Where can I buy one?

[chili-chips]

... it seems that CologneChip proprietary PNR tool has problems with inout ports. @goran-mahovlic reported something along those lines while working on Verilog for PS2 keyboard. While we did not create a formal issue at that time, we should perhaps do it now.

[chili-chips-ba]

Check this for and earlier issue with CologneChip inout ports

[chili-chips-ba]

@pu-cc has now resolved this problem.

[TarikHamedovic]

We have now fixed the issue with the Pin_in, Pin_out, Pin_inout pin declarations with the new p_r GateMate tool update that lets us declare ports this way.
Net "led_0__io" Loc = "IO_SB_B6";

Now the .ccf file can be simply generated using this

"{{name}}.ccf": r"""
 # {{autogenerated}}
 {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
     Net "{{port_name}}" Loc = "{{pin_name}}";
 {% endfor %}
""",

I know that I need to add attributes, but this was just to test out the Blinky example I wrote for the Olimex board so I can close this discussion.

Next step for me is to make the gatemate_a1_evb.py in amaranth_boards file have more Resources and the check the gatemate.py file.

[whitequark]

Sounds good, thank you!