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c128.sv
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//============================================================================
// C128 Top level for MiSTer
// Copyright (C) 2022 Erik Scheffers
// Based on C64 for MiSTer Copyright (C) 2017-2021 Sorgelig
//
// Used DE2-35 Top level by Dar ([email protected])
//
// FPGA64 is Copyrighted 2005-2008 by Peter Wendrich ([email protected])
// http://www.syntiac.com/fpga64.html
//
//
// This program is free software; you can redistribute it and/or modify it
// under the terms of the GNU General Public License as published by the Free
// Software Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
// more details.
//
// You should have received a copy of the GNU General Public License along
// with this program; if not, write to the Free Software Foundation, Inc.,
// 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
//============================================================================
module emu
(
//Master input clock
input CLK_50M,
//Async reset from top-level module.
//Can be used as initial reset.
input RESET,
//Must be passed to hps_io module
inout [48:0] HPS_BUS,
//Base video clock. Usually equals to CLK_SYS.
output CLK_VIDEO,
//Multiple resolutions are supported using different CE_PIXEL rates.
//Must be based on CLK_VIDEO
output CE_PIXEL,
//Video aspect ratio for HDMI. Most retro systems have ratio 4:3.
//if VIDEO_ARX[12] or VIDEO_ARY[12] is set then [11:0] contains scaled size instead of aspect ratio.
output [12:0] VIDEO_ARX,
output [12:0] VIDEO_ARY,
output [7:0] VGA_R,
output [7:0] VGA_G,
output [7:0] VGA_B,
output VGA_HS,
output VGA_VS,
output VGA_DE, // = ~(VBlank | HBlank)
output VGA_F1,
output [1:0] VGA_SL,
output VGA_SCALER, // Force VGA scaler
output VGA_DISABLE, // analog out is off
input [11:0] HDMI_WIDTH,
input [11:0] HDMI_HEIGHT,
output HDMI_FREEZE,
`ifdef MISTER_FB
// Use framebuffer in DDRAM
// FB_FORMAT:
// [2:0] : 011=8bpp(palette) 100=16bpp 101=24bpp 110=32bpp
// [3] : 0=16bits 565 1=16bits 1555
// [4] : 0=RGB 1=BGR (for 16/24/32 modes)
//
// FB_STRIDE either 0 (rounded to 256 bytes) or multiple of pixel size (in bytes)
output FB_EN,
output [4:0] FB_FORMAT,
output [11:0] FB_WIDTH,
output [11:0] FB_HEIGHT,
output [31:0] FB_BASE,
output [13:0] FB_STRIDE,
input FB_VBL,
input FB_LL,
output FB_FORCE_BLANK,
`ifdef MISTER_FB_PALETTE
// Palette control for 8bit modes.
// Ignored for other video modes.
output FB_PAL_CLK,
output [7:0] FB_PAL_ADDR,
output [23:0] FB_PAL_DOUT,
input [23:0] FB_PAL_DIN,
output FB_PAL_WR,
`endif
`endif
output LED_USER, // 1 - ON, 0 - OFF.
// b[1]: 0 - LED status is system status OR'd with b[0]
// 1 - LED status is controled solely by b[0]
// hint: supply 2'b00 to let the system control the LED.
output [1:0] LED_POWER,
output [1:0] LED_DISK,
// I/O board button press simulation (active high)
// b[1]: user button
// b[0]: osd button
output [1:0] BUTTONS,
input CLK_AUDIO, // 24.576 MHz
output [15:0] AUDIO_L,
output [15:0] AUDIO_R,
output AUDIO_S, // 1 - signed audio samples, 0 - unsigned
output [1:0] AUDIO_MIX, // 0 - no mix, 1 - 25%, 2 - 50%, 3 - 100% (mono)
//ADC
inout [3:0] ADC_BUS,
//SD-SPI
output SD_SCK,
output SD_MOSI,
input SD_MISO,
output SD_CS,
input SD_CD,
//High latency DDR3 RAM interface
//Use for non-critical time purposes
output DDRAM_CLK,
input DDRAM_BUSY,
output [7:0] DDRAM_BURSTCNT,
output [28:0] DDRAM_ADDR,
input [63:0] DDRAM_DOUT,
input DDRAM_DOUT_READY,
output DDRAM_RD,
output [63:0] DDRAM_DIN,
output [7:0] DDRAM_BE,
output DDRAM_WE,
//SDRAM interface with lower latency
output SDRAM_CLK,
output SDRAM_CKE,
output [12:0] SDRAM_A,
output [1:0] SDRAM_BA,
inout [15:0] SDRAM_DQ,
output SDRAM_DQML,
output SDRAM_DQMH,
output SDRAM_nCS,
output SDRAM_nCAS,
output SDRAM_nRAS,
output SDRAM_nWE,
`ifdef MISTER_DUAL_SDRAM
//Secondary SDRAM
//Set all output SDRAM_* signals to Z ASAP if SDRAM2_EN is 0
input SDRAM2_EN,
output SDRAM2_CLK,
output [12:0] SDRAM2_A,
output [1:0] SDRAM2_BA,
inout [15:0] SDRAM2_DQ,
output SDRAM2_nCS,
output SDRAM2_nCAS,
output SDRAM2_nRAS,
output SDRAM2_nWE,
`endif
input UART_CTS,
output UART_RTS,
input UART_RXD,
output UART_TXD,
output UART_DTR,
input UART_DSR,
// Open-drain User port.
// 0 - D+/RX
// 1 - D-/TX
// 2..6 - USR2..USR6
// Set USER_OUT to 1 to read from USER_IN.
input [6:0] USER_IN,
output [6:0] USER_OUT,
input OSD_STATUS
);
assign {DDRAM_CLK, DDRAM_BURSTCNT, DDRAM_ADDR, DDRAM_DIN, DDRAM_BE, DDRAM_RD, DDRAM_WE} = 0;
assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
assign LED_DISK = 0;
assign LED_POWER = 0;
assign LED_USER = |drive_led | ioctl_download | tape_led;
assign BUTTONS = 0;
assign VGA_DISABLE = 0;
assign VGA_SCALER = 0;
// Status Bit Map:
// Upper Lower
// 0 1 2 3 4 5 6
// 01234567890123456789012345678901 23456789012345678901234567890123
// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
// XXXXXXXXXXXXXX XXXXXX XXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXX
// 1 1 1
// 6 7 8 9 0 1 2
// 45678901234567890123456789012345 67890123456789012345678901234567
// XXXXXXXXXXXXXXXX
// bits 0.. 63 keep in sync with C64 core
// bits 64.. 79 reserved in case C64 core starts using them
// bits 80..127 C128 core options
`include "build_id.v"
localparam CONF_STR = {
"C128;UART9600:2400;",
// XXXXXXXXXXXXXXXXXXXXXXXXXXXX
"-,/!\\ This in-development core;",
"-,needs a modified MiSTer main;",
"-, binary for the disk drives;",
"-,to function. See the MiSTer;",
"-, forum for details.;",
"-;",
"H7S0,D64G64D71G71D81T64,Mount #8 ;",
"H0S1,D64G64D71G71D81T64,Mount #9 ;",
"-;",
"F1,PRGCRTREUTAP;",
"h3-;",
"h3R7,Tape Play/Pause;",
"h3RN,Tape Unload;",
"h3OB,Tape Sound,Off,On;",
"-;",
"P1,Audio & Video;",
"P1O2,Video Standard,PAL,NTSC;",
"P1O45,Aspect Ratio,Original,Full Screen,[ARC1],[ARC2];",
"P1O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%,CRT 75%;",
"d1P1o0,Vertical Crop,No,Yes;",
"P1OUV,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
"P1O[95:94],VIC Jailbars,Off,Low,Medium,High;",
"P1-;",
"P1OD,Left SID,8580,6581;",
"d4P1o23,Left Filter,Default,Custom 1,Custom 2,Custom 3;",
"P1OG,Right SID,8580,6581;",
"d5P1o56,Right Filter,Default,Custom 1,Custom 2,Custom 3;",
"P1OKL,Right SID Port,Same,D420,DE00,DF00;",
"P1FC7,FLT,Load Custom Filters;",
"P1-;",
"P1OC,Sound Expander,Disabled,OPL2;",
"P1o89,DigiMax,Disabled,DE00,DF00;",
"P1OIJ,Stereo Mix,None,25%,50%,100%;",
"P1-;",
"P1O[81:80],VDC version,2 (8568 DCR),1 (8563 R9),0 (8563 R7a);",
"d6P1O[88],VDC memory,16k,64k;",
"P1O[92:91],VDC palette,Default,Analogue,Monochrome,Composite;",
"h2P1O[90:89],VDC colour,White,Green,Amber,Red;",
"P2,Hardware;",
"P2oPQ,Enable Drive #8,If Mounted,Always,Never;",
"P2oNO,Enable Drive #9,If Mounted,Always,Never;",
"D7P2O[84:83],Drive #8 5.25\" model,1571,1541,1570;",
"D0P2O[86:85],Drive #9 5.25\" model,1571,1541,1570;",
"P2oC,Parallel port,Enabled,Disabled;",
"P2OP,External IEC,Disabled,Enabled;",
"P2R6,Reset Disk Drives;",
"P2-;",
"P2O[87],Internal memory,128K,256K;",
"P2oK,GeoRAM,Disabled,4MB;",
"P2oLM,REU,Disabled,512KB,2MB (512KB wrap),16MB;",
"P2-;",
"P2oB,Expansion,Joysticks,RS232;",
"P2oJ,RS232 mode,UP9600,VIC-1011;",
"P2o1,RS232 connection,Internal,External;",
"P2o4,Real-Time Clock,Auto,Disabled;",
"P2oD,CIA Model,8521,6526;",
"P2-;",
"P2OQR,Pot 1/2,Joy 1 Fire 2/3,Mouse,Paddles 1/2;",
"P2OST,Pot 3/4,Joy 2 Fire 2/3,Mouse,Paddles 3/4;",
"P2-;",
"P2oRS,Key modifier,L+R Shift,L Shift,R Shift;",
"P2-;",
"P2O1,Release Keys on Reset,Yes,No;",
"P2OO,Clear RAM on Reset,Yes,No;",
"P2oI,Reset & Run PRG,Yes,No;",
"P2oA,Pause When OSD is Open,No,Yes;",
"P2o7,Tape Autoplay,Yes,No;",
"P2-;",
"P2FC8,ROM,Syst. ROM1+4 C64+Kernal+Char;",
"P2FC9,ROM,Syst. ROM2+3 Basic ;",
"P2FC6,ROM,Function ROM ;",
"P2FC4,R41R70R71R81,Drive ROM ;",
"P2-;",
"P2FC5,CRT,Boot Cartridge ;",
"P2-;",
"P2O[93],ROM set,128DCR,Standard;",
"P2O[82],Char switch,C64 mode,Caps Lk key;",
"-;",
"O3,Swap Joysticks,No,Yes;",
"-;",
"R0,Reset;",
"RH,Reset & Detach Cartridge;",
"J,Fire 1,Fire 2,Fire 3,Paddle Btn,Mod1,Mod2;",
"jn,A,B,Y,X|P,R,L;",
"jp,A,B,Y,X|P,R,L;",
"I,",
"SHIFT LOCK: Off,SHIFT LOCK: On,",
"CAPS LOCK: On,CAPS LOCK: Off,",
"CHARSET: DIN,CHARSET: ASCII,",
"40/80 DISPLAY: 80,40/80 DISPLAY: 40,",
"NO SCROLL LOCK: Off,NO SCROLL LOCK: On;",
"V,v",`BUILD_DATE
};
wire pll_locked;
wire clk_sys;
wire clk64;
wire clk48;
pll pll
(
.refclk(CLK_50M),
.outclk_0(clk48),
.outclk_1(clk64),
.outclk_2(clk_sys),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
.locked(pll_locked)
);
wire [63:0] reconfig_to_pll;
wire [63:0] reconfig_from_pll;
wire cfg_waitrequest;
reg cfg_write;
reg [5:0] cfg_address;
reg [31:0] cfg_data;
pll_cfg pll_cfg
(
.mgmt_clk(CLK_50M),
.mgmt_reset(0),
.mgmt_waitrequest(cfg_waitrequest),
.mgmt_read(0),
.mgmt_readdata(),
.mgmt_write(cfg_write),
.mgmt_address(cfg_address),
.mgmt_writedata(cfg_data),
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll)
);
always @(posedge CLK_50M) begin
reg ntscd = 0, ntscd2 = 0;
reg [2:0] state = 0;
reg ntsc_r;
ntscd <= ntsc;
ntscd2 <= ntscd;
cfg_write <= 0;
if(ntscd2 == ntscd && ntscd2 != ntsc_r) begin
state <= 1;
ntsc_r <= ntscd2;
end
if(!cfg_waitrequest) begin
if(state) state<=state+1'd1;
case(state)
1: begin
cfg_address <= 0;
cfg_data <= 0;
cfg_write <= 1;
end
/*
3: begin
cfg_address <= 4;
cfg_data <= ntsc_r ? 'h20504 : 'h404;
cfg_write <= 1;
end
*/
5: begin
cfg_address <= 7;
cfg_data <= ntsc_r ? 3357876127 : 1503512573;
cfg_write <= 1;
end
7: begin
cfg_address <= 2;
cfg_data <= 0;
cfg_write <= 1;
end
endcase
end
end
reg reset_n;
reg reset_wait = 0;
always @(posedge clk_sys) begin
integer reset_counter;
reg old_download;
reg do_erase = 1;
reset_n <= !reset_counter;
old_download <= ioctl_download;
if (RESET | status[0] | status[17] | buttons[1] | !pll_locked) begin
if(RESET) do_erase <= 1;
reset_counter <= 100000;
end
else if(~old_download & ioctl_download & load_prg & ~status[50]) begin
do_erase <= 1;
reset_wait <= 1;
reset_counter <= 255;
end
else if (ioctl_download & (load_crt | load_rom14 | load_rom23 | load_romF1)) begin
do_erase <= 1;
reset_counter <= 255;
end
else if ((ioctl_download || inj_meminit) & ~reset_wait);
else if (erasing) force_erase <= 0;
else if (!reset_counter) begin
do_erase <= 0;
if(reset_wait && c128_addr[15:0] == 'hFFCF) reset_wait <= 0;
end
else begin
reset_counter <= reset_counter - 1;
if (reset_counter == 100 && (~status[24] | do_erase)) force_erase <= 1;
end
end
wire [15:0] joyA,joyB,joyC,joyD;
wire [15:0] joy = joyA | joyB | joyC | joyD;
wire [127:0] status;
wire forced_scandoubler;
wire ioctl_wr;
wire [24:0] ioctl_addr;
wire [7:0] ioctl_data;
wire [9:0] ioctl_index;
wire ioctl_download;
wire [31:0] ioctl_file_ext;
wire [31:0] sd_lba[2];
wire [5:0] sd_blk_cnt[2];
wire [1:0] sd_rd;
wire [1:0] sd_wr;
wire [1:0] sd_ack;
wire [15:0] sd_buff_addr;
wire [7:0] sd_buff_dout;
wire [7:0] sd_buff_din[2];
wire sd_buff_wr;
wire [1:0] img_mounted;
wire [31:0] img_size;
wire img_readonly;
wire [24:0] ps2_mouse;
wire [10:0] ps2_key;
wire [2:0] ps2_kbd_led_status = {2'b00, ~cpslk_sense};
wire [2:0] ps2_kbd_led_use = 3'b001;
wire sftlk_sense;
wire cpslk_sense;
wire d4080_sense;
wire noscr_sense;
wire [1:0] buttons;
wire [21:0] gamma_bus;
wire [7:0] pd1,pd2,pd3,pd4;
wire [64:0] RTC;
hps_io #(.CONF_STR(CONF_STR), .VDNUM(2), .BLKSZ(1)) hps_io
(
.clk_sys(clk_sys),
.HPS_BUS(HPS_BUS),
.joystick_0(joyA),
.joystick_1(joyB),
.joystick_2(joyC),
.joystick_3(joyD),
.paddle_0(pd1),
.paddle_1(pd2),
.paddle_2(pd3),
.paddle_3(pd4),
.status(status),
.status_menumask({status[58], |status[81:80], status[16], status[13], tap_loaded, status[92], |vcrop, status[56]}),
.buttons(buttons),
.forced_scandoubler(forced_scandoubler),
.gamma_bus(gamma_bus),
.sd_lba(sd_lba),
.sd_blk_cnt(sd_blk_cnt),
.sd_rd(sd_rd),
.sd_wr(sd_wr),
.sd_ack(sd_ack),
.sd_buff_addr(sd_buff_addr),
.sd_buff_dout(sd_buff_dout),
.sd_buff_din(sd_buff_din),
.sd_buff_wr(sd_buff_wr),
.img_mounted(img_mounted),
.img_size(img_size),
.img_readonly(img_readonly),
.ps2_key(ps2_key),
.ps2_mouse(ps2_mouse),
.ps2_kbd_led_status(ps2_kbd_led_status),
.ps2_kbd_led_use(ps2_kbd_led_use),
.RTC(RTC),
.ioctl_download(ioctl_download),
.ioctl_index(ioctl_index),
.ioctl_file_ext(ioctl_file_ext),
.ioctl_wr(ioctl_wr),
.ioctl_addr(ioctl_addr),
.ioctl_dout(ioctl_data),
.ioctl_wait(ioctl_req_wr|reset_wait),
.info_req(info_req),
.info(info)
);
wire load_prg = ioctl_index == 'h01;
wire load_crt = ioctl_index == 'h41 || ioctl_index == 5;
wire load_reu = ioctl_index == 'h81;
wire load_tap = ioctl_index == 'hC1;
wire load_flt = ioctl_index == 7;
wire load_rom14 = ioctl_index == 8;
wire load_rom23 = ioctl_index == 9;
wire load_romF1 = ioctl_index == 10;
wire load_c15xx = ioctl_index == 11;
wire game;
wire game_mmu;
wire exrom;
wire exrom_mmu;
wire io_rom;
wire cart_ce;
wire cart_we;
wire nmi;
wire cart_oe;
wire IOF_rd;
wire [7:0] cart_data;
wire [24:0] cart_addr;
cartridge cartridge
(
.clk32(clk_sys),
.reset_n(reset_n),
.cart_loading(ioctl_download && load_crt),
.cart_id(cart_attached ? cart_id : status[52] ? 8'd99 : 8'd255),
.cart_c128(cart_c128),
.cart_exrom(cart_exrom),
.cart_game(cart_game),
.cart_bank_laddr(cart_bank_laddr),
.cart_bank_size(cart_bank_size),
.cart_bank_num(cart_bank_num),
.cart_bank_type(cart_bank_type),
.cart_bank_raddr(ioctl_load_addr),
.cart_bank_wr(cart_hdr_wr),
.exrom(exrom),
.exrom_in(exrom_mmu),
.game(game),
.game_in(game_mmu),
.c128_n(c128_n),
.romL(romL),
.romH(romH),
.UMAXromH(UMAXromH),
.IOE(IOE),
.IOF(IOF),
.mem_write(ram_we),
.mem_ce(ram_ce),
.mem_ce_out(cart_ce),
.mem_write_out(cart_we),
.IO_rom(io_rom),
.IO_rd(cart_oe),
.IO_data(cart_data),
.addr_in(c128_addr),
.data_in(c128_data_out),
.addr_out(cart_addr),
.freeze_key(freeze_key),
.mod_key(mod_key),
.nmi(nmi),
.nmi_ack(nmi_ack)
);
wire dma_req;
wire dma_cycle;
wire [15:0] dma_addr;
wire [7:0] dma_dout;
wire [7:0] dma_din;
wire dma_we;
wire ext_cycle;
wire [24:0] reu_ram_addr;
wire [7:0] reu_ram_dout;
wire reu_ram_we;
wire [7:0] reu_dout;
wire reu_irq;
wire reu_oe = IOF && reu_cfg;
wire [1:0] reu_cfg = status[54:53];
reu reu
(
.clk(clk_sys),
.reset(~reset_n),
.cfg(reu_cfg),
.dma_req(dma_req),
.dma_cycle(dma_cycle),
.dma_addr(dma_addr),
.dma_dout(dma_dout),
.dma_din(dma_din),
.dma_we(dma_we),
.ram_cycle(ext_cycle),
.ram_addr(reu_ram_addr),
.ram_dout(reu_ram_dout),
.ram_din(sdram_data),
.ram_we(reu_ram_we),
.cpu_addr(c128_addr[15:0]),
.cpu_dout(c128_data_out),
.cpu_din(reu_dout),
.cpu_we(ram_we),
.cpu_cs(IOF),
.irq(reu_irq)
);
reg ext_cycle_d;
always @(posedge clk_sys) ext_cycle_d <= ext_cycle;
wire reu_ram_ce = ~ext_cycle_d & ext_cycle & dma_req;
// rearrange joystick contacts for c64
wire [6:0] joyA_int = joy[8] ? 7'd0 : {joyA[6:4], joyA[0], joyA[1], joyA[2], joyA[3]};
wire [6:0] joyB_int = joy[8] ? 7'd0 : {joyB[6:4], joyB[0], joyB[1], joyB[2], joyB[3]};
wire [6:0] joyC_c64 = joy[8] ? 7'd0 : {joyC[6:4], joyC[0], joyC[1], joyC[2], joyC[3]};
wire [6:0] joyD_c64 = joy[8] ? 7'd0 : {joyD[6:4], joyD[0], joyD[1], joyD[2], joyD[3]};
// swap joysticks if requested
wire [6:0] joyA_c64 = status[3] ? joyB_int : joyA_int;
wire [6:0] joyB_c64 = status[3] ? joyA_int : joyB_int;
wire [7:0] paddle_1 = status[3] ? pd3 : pd1;
wire [7:0] paddle_2 = status[3] ? pd4 : pd2;
wire [7:0] paddle_3 = status[3] ? pd1 : pd3;
wire [7:0] paddle_4 = status[3] ? pd2 : pd4;
wire paddle_1_btn = ~joy[8] & (status[3] ? joyC[7] : joyA[7]);
wire paddle_2_btn = ~joy[8] & (status[3] ? joyD[7] : joyB[7]);
wire paddle_3_btn = ~joy[8] & (status[3] ? joyA[7] : joyC[7]);
wire paddle_4_btn = ~joy[8] & (status[3] ? joyB[7] : joyD[7]);
wire [1:0] pd12_mode = status[27:26];
wire [1:0] pd34_mode = status[29:28];
reg [24:0] ioctl_load_addr;
reg ioctl_req_wr;
reg [15:0] cart_id;
reg cart_c128;
reg [15:0] cart_bank_laddr;
reg [15:0] cart_bank_size;
reg [15:0] cart_bank_num;
reg [7:0] cart_bank_type;
reg [7:0] cart_exrom;
reg [7:0] cart_game;
reg cart_attached = 0;
reg [3:0] cart_hdr_cnt;
reg cart_hdr_wr;
reg [31:0] cart_blk_len;
reg force_erase;
reg erasing;
reg inj_meminit = 0;
wire io_cycle;
reg io_cycle_ce;
reg io_cycle_we;
reg [24:0] io_cycle_addr;
reg [7:0] io_cycle_data;
localparam TAP_ADDR = 25'h0200000;
localparam REU_ADDR = 25'h1000000;
always @(posedge clk_sys) begin
reg [4:0] erase_to;
reg old_download;
reg erase_cram;
reg io_cycleD;
reg old_st0 = 0;
reg old_meminit;
reg [15:0] inj_end;
reg [7:0] inj_meminit_data;
old_download <= ioctl_download;
io_cycleD <= io_cycle;
cart_hdr_wr <= 0;
if (~io_cycle & io_cycleD) begin
io_cycle_ce <= 1;
io_cycle_we <= 0;
io_cycle_addr <= tap_play_addr + TAP_ADDR;
if (ioctl_req_wr) begin
ioctl_req_wr <= 0;
io_cycle_we <= 1;
io_cycle_addr <= ioctl_load_addr;
ioctl_load_addr <= ioctl_load_addr + 1'b1;
if (erasing) io_cycle_data <= {8{ioctl_load_addr[6]}};
else if (inj_meminit) io_cycle_data <= inj_meminit_data;
else io_cycle_data <= ioctl_data;
end
end
if (io_cycle & io_cycleD) {io_cycle_ce, io_cycle_we} <= 0;
if (ioctl_wr) begin
if (load_prg) begin
// PRG header
// Load address low-byte
if (ioctl_addr == 0) begin ioctl_load_addr[7:0] <= ioctl_data; inj_end[7:0] <= ioctl_data; end
// Load address high-byte
else if (ioctl_addr == 1) begin ioctl_load_addr[15:8] <= ioctl_data; inj_end[15:8] <= ioctl_data; end
else begin ioctl_req_wr <= 1; inj_end <= inj_end + 1'b1; end
end
if (load_crt) begin
if (ioctl_addr == 0) begin
ioctl_load_addr <= 24'h100000;
cart_blk_len <= 0;
cart_hdr_cnt <= 0;
end
if (ioctl_addr == 8'h01) cart_c128 <= ioctl_data[0];
if (ioctl_addr == 8'h16) cart_id[15:8] <= ioctl_data;
if (ioctl_addr == 8'h17) cart_id[7:0] <= ioctl_data;
if (ioctl_addr == 8'h18) cart_exrom[7:0] <= ioctl_data;
if (ioctl_addr == 8'h19) cart_game[7:0] <= ioctl_data;
if (ioctl_addr >= 8'h40) begin
if (cart_blk_len == 0 & cart_hdr_cnt == 0) begin
cart_hdr_cnt <= 1;
if (ioctl_load_addr[12:0] != 0) begin
// align to 8KB boundary
ioctl_load_addr[12:0] <= 0;
ioctl_load_addr[24:13] <= ioctl_load_addr[24:13] + 1'b1;
end
end else if (cart_hdr_cnt != 0) begin
cart_hdr_cnt <= cart_hdr_cnt + 1'b1;
if (cart_hdr_cnt == 4) cart_blk_len[31:24] <= ioctl_data;
if (cart_hdr_cnt == 5) cart_blk_len[23:16] <= ioctl_data;
if (cart_hdr_cnt == 6) cart_blk_len[15:8] <= ioctl_data;
if (cart_hdr_cnt == 7) cart_blk_len[7:0] <= ioctl_data;
if (cart_hdr_cnt == 8) cart_blk_len <= cart_blk_len - 8'h10;
if (cart_hdr_cnt == 9) cart_bank_type <= ioctl_data;
if (cart_hdr_cnt == 10) cart_bank_num[15:8] <= ioctl_data;
if (cart_hdr_cnt == 11) cart_bank_num[7:0] <= ioctl_data;
if (cart_hdr_cnt == 12) cart_bank_laddr[15:8]<= ioctl_data;
if (cart_hdr_cnt == 13) cart_bank_laddr[7:0] <= ioctl_data;
if (cart_hdr_cnt == 14) cart_bank_size[15:8] <= ioctl_data;
if (cart_hdr_cnt == 15) cart_bank_size[7:0] <= ioctl_data;
if (cart_hdr_cnt == 15) cart_hdr_wr <= 1;
end
else begin
cart_blk_len <= cart_blk_len - 1'b1;
ioctl_req_wr <= 1;
end
end
end
if (load_tap) begin
if (ioctl_addr == 0) ioctl_load_addr <= TAP_ADDR;
if (ioctl_addr == 12) tap_version <= ioctl_data[1:0];
ioctl_req_wr <= 1;
end
if (load_reu) begin
if (ioctl_addr == 0) ioctl_load_addr <= REU_ADDR;
ioctl_req_wr <= 1;
end
end
if (old_download != ioctl_download && load_crt) begin
cart_attached <= old_download;
erase_cram <= 1;
end
// meminit for RAM injection
if (old_download != ioctl_download && load_prg && !inj_meminit) begin
inj_meminit <= 1;
ioctl_load_addr <= 0;
end
if (inj_meminit) begin
if (!ioctl_req_wr) begin
// check if done
if (ioctl_load_addr == 'h100) begin
inj_meminit <= 0;
end
else begin
ioctl_req_wr <= 1;
// Initialize BASIC pointers to simulate the BASIC LOAD command
case(ioctl_load_addr)
// TXT (2D-2E)
// Set these two bytes to $01, $08 just as they would be on reset (the BASIC LOAD command does not alter these)
'h2D: inj_meminit_data <= 'h01;
'h2E: inj_meminit_data <= 'h1C;
// SAVE_START (AC-AD)
// Set these two bytes to zero just as they would be on reset (the BASIC LOAD command does not alter these)
'hAC, 'hAD: inj_meminit_data <= 'h00;
// VAR (2D-2E), ARY (2F-30), STR (31-32), LOAD_END (AE-AF)
// Set these just as they would be with the BASIC LOAD command (essentially they are all set to the load end address)
'h2F, 'h31, 'h33, 'hAE: inj_meminit_data <= inj_end[7:0];
'h30, 'h32, 'h34, 'hAF: inj_meminit_data <= inj_end[15:8];
default: begin
ioctl_req_wr <= 0;
// advance the address
ioctl_load_addr <= ioctl_load_addr + 1'b1;
end
endcase
end
end
end
old_meminit <= inj_meminit;
start_strk <= old_meminit & ~inj_meminit;
old_st0 <= status[17];
if (~old_st0 & status[17]) cart_attached <= 0;
if (!erasing && force_erase) begin
erasing <= 1;
ioctl_load_addr <= 0;
end
if (erasing && !ioctl_req_wr) begin
erase_to <= erase_to + 1'b1;
if (&erase_to) begin
if (ioctl_load_addr < ({erase_cram, 16'hFFFF}))
ioctl_req_wr <= 1;
else begin
erasing <= 0;
erase_cram <= 0;
end
end
end
end
reg start_strk = 0;
reg reset_keys = 0;
reg [10:0] key = 0;
always @(posedge clk_sys) begin
reg [3:0] act = 0;
reg joy_finish = 0;
reg [17:0] joy_last = 0;
reg [17:0] joy_key;
int to;
reset_keys <= 0;
joy_key =(joy[9:8] == 3) ?
(joy[0] ? 18'h005 : joy[1] ? 18'h006 : joy[2] ? 18'h004 : joy[3] ? 18'h00C :
joy[4] ? 18'h003 : joy[5] ? 18'h00B : joy[6] ? 18'h083 : joy[7] ? 18'h00A : 18'h0):
(joy[9]) ?
(joy[0] ? 18'h016 : joy[1] ? 18'h01E : joy[2] ? 18'h026 : joy[3] ? 18'h025 :
joy[4] ? 18'h02E : joy[5] ? 18'h045 : joy[6] ? 18'h035 : joy[7] ? 18'h031 : 18'h0):
(joy[0] ? 18'h174 : joy[1] ? 18'h16B : joy[2] ? 18'h172 : joy[3] ? 18'h175 :
joy[4] ? 18'h05A : joy[5] ? 18'h029 : joy[6] ? 18'h076 : joy[7] ? 18'h2276 : 18'h0);
if(~reset_n) {joy_finish, act} <= 0;
if(joy[9:8]) begin
joy_finish <= 1;
if(!joy[7:0] && joy_last) begin
joy_last <= 0;
reset_keys <= 1;
end
else if(!joy_last[8:0] && joy_key) begin
to <= to + 1'd1;
if(joy_last[17:9] != joy_key[17:9]) begin
joy_last[17:9] <= joy_key[17:9];
key <= joy_key[17:9];
key[9] <= 1;
key[10] <= ~key[10];
end
else if(to > 640000 && joy_last[8:0] != joy_key[8:0]) begin
joy_last[8:0] <= joy_key[8:0];
key <= joy_key[8:0];
key[9] <= 1;
key[10] <= ~key[10];
end
end
else begin
to <= 0;
end
end
else if(joy_finish) begin
joy_last <= 0;
key <= 0;
key[10] <= ps2_key[10];
joy_finish <= 0;
reset_keys <= 1;
end
else if(act) begin
to <= to + 1;
if(to > 1280000) begin
to <= 0;
act <= act + 1'd1;
case(act)
// PS/2 scan codes
1: key <= 'h2d; // R
3: key <= 'h3c; // U
5: key <= 'h31; // N
7: key <= 'h5a; // <RETURN>
9: key <= 'h00;
10: act <= 0;
endcase
key[9] <= act[0];
key[10] <= (act >= 9) ? ps2_key[10] : ~key[10];
end
end
else begin
to <= 0;
key <= ps2_key;
end
if(start_strk & ~status[50]) begin
act <= 1;
key <= 0;
end
end
assign SDRAM_CKE = 1;
wire [7:0] sdram_data;
sdram sdram
(
.sd_addr(SDRAM_A),
.sd_data(SDRAM_DQ),
.sd_ba(SDRAM_BA),
.sd_cs(SDRAM_nCS),
.sd_we(SDRAM_nWE),
.sd_ras(SDRAM_nRAS),
.sd_cas(SDRAM_nCAS),
.sd_clk(SDRAM_CLK),
.sd_dqm({SDRAM_DQMH,SDRAM_DQML}),
.clk(clk64),
.init(~pll_locked),
.refresh(refresh),
.addr( io_cycle ? io_cycle_addr : ext_cycle ? reu_ram_addr : cart_addr ),
.ce ( io_cycle ? io_cycle_ce : ext_cycle ? reu_ram_ce : cart_ce ),
.we ( io_cycle ? io_cycle_we : ext_cycle ? reu_ram_we : cart_we ),
.din ( io_cycle ? io_cycle_data : ext_cycle ? reu_ram_dout : c128_data_out ),
.dout( sdram_data )
);
wire [7:0] c128_data_out;
wire [17:0] c128_addr;
wire c64_pause;
wire refresh;
wire ram_ce;
wire ram_we;
wire nmi_ack;
wire freeze_key;
wire mod_key;
wire IOE;
wire IOF;
wire romL;
wire romH;
wire UMAXromH;
wire [17:0] audio_l,audio_r;
wire ntsc = status[2];
wire vicHsync, vicVsync;
wire [7:0] vicR, vicG, vicB;
wire vdcHsync, vdcVsync;
wire vdcHblank, vdcVblank;
wire [7:0] vdcR, vdcG, vdcB;
wire c64_iec_atn;
wire c64_iec_clk_o;
wire c64_iec_data_o;
wire c64_iec_srq_n_o;
wire c64_iec_clk_i;