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I want to run the simulation tests for this design , however I am unable to run the test with the command "make WAVES=1". I get below error.
FST warning: ignoring signals in previously scanned scope test_fpga_core.core_inst.udp_payload_fifo.genblk9.
ERROR: results.xml was not written by the simulation!
make[1]: *** [/home/liza/anaconda3/lib/python3.9/site-packages/cocotb/share/makefiles/simulators/Makefile.icarus:96: results.xml] Error 1
make[1]: Leaving directory '/home/liza/verilog-ethernet/example/Alveo/fpga_25g/tb/fpga_core'
make: *** [/home/liza/anaconda3/lib/python3.9/site-packages/cocotb/share/makefiles/Makefile.inc:40: sim] Error 2
I suspect that the Icarus Verilog simulator is not installed, however I do not know how to get this simulator installed. The link in this page for Icarus Verilog does not exist anymore.
The text was updated successfully, but these errors were encountered:
I want to run the simulation tests for this design , however I am unable to run the test with the command "make WAVES=1". I get below error.
FST warning: ignoring signals in previously scanned scope test_fpga_core.core_inst.udp_payload_fifo.genblk9.
ERROR: results.xml was not written by the simulation!
make[1]: *** [/home/liza/anaconda3/lib/python3.9/site-packages/cocotb/share/makefiles/simulators/Makefile.icarus:96: results.xml] Error 1
make[1]: Leaving directory '/home/liza/verilog-ethernet/example/Alveo/fpga_25g/tb/fpga_core'
make: *** [/home/liza/anaconda3/lib/python3.9/site-packages/cocotb/share/makefiles/Makefile.inc:40: sim] Error 2
I suspect that the Icarus Verilog simulator is not installed, however I do not know how to get this simulator installed. The link in this page for Icarus Verilog does not exist anymore.
The text was updated successfully, but these errors were encountered: