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‎LICENSE

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Apache License
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‎README.md

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## Start
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This demo project files are copied from block-pio-sifive files at first.
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and modified for similar to the ddr4 on-boarding environment.
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They have 3 interfaces, 2 port AXI and 1 port APB as I knew.
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We don't have ddr4 ctl and phy verilog code, so we are using pwm and pio model
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instead of DDR4 verilog files as below figure.
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APB inf. AXI inf. AXI inf.
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^ ^ ^
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| | |
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+----- | ------------- | ---------- | --------+
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| | | | |
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| | V V |
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| | +----------+ +----------+ |
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| | | capctl | | pio | |
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| | | | | | |
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| | +--++++++--+ +----+-----+ |
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| | |||||| | |
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| V |||||| | |
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| +------------------++++++--+ +----+-----+ |
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| | cap | | loopback | |
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| | PWM | | | |
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| | | +----------+ |
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| | | |
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| | PTC0 PTC1 ... PTC5 | |
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| +--------------------------+ |
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| demo |
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+---------------------------------------------+
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(demo block : made simuiler to the structure of DDR ctl&phy)
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[verilog files]
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block-demo-sifive/rtl :
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./rtl/loopback/loopback.sv
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./rtl/pio/pio.sv
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./rtl/pwm/PWM.v : pwm verilog file
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./rtl/pwm/PTC.v : ptc verilog file
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./rtl/capctl/capctl.sv : for controlling cap signal
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## Question
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1. What about the procedure for on-boarding of demo block
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(including PWM, capctl, pio, loopback module)
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2. Can we on-board seperate module? or do we have to make top verilog module for onboarding?
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‎craft/loopback/src/loopback-base.scala

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// Generated Code
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// Please DO NOT EDIT
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package sifive.vip.loopback
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import chisel3._
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// import chisel3.{withClockAndReset, _}
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import chisel3.util._
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import chisel3.experimental._
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import freechips.rocketchip.config._
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import freechips.rocketchip.diplomacy._
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import freechips.rocketchip.amba.axi4._
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import freechips.rocketchip.amba.apb._
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import freechips.rocketchip.amba.ahb._
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import freechips.rocketchip.interrupts._
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import freechips.rocketchip.util.{ElaborationArtefacts}
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import freechips.rocketchip.tilelink._
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import freechips.rocketchip.subsystem._
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import freechips.rocketchip.regmapper._
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import sifive.skeleton._
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import sifive.blocks.util.{NonBlockingEnqueue, NonBlockingDequeue}
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class loopbackBlackBoxIO(
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val pioWidth: Int
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) extends Bundle {
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val odata = Input(UInt((pioWidth).W))
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val oenable = Input(UInt((pioWidth).W))
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val idata = Output(UInt((pioWidth).W))
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}
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class loopback(
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val pioWidth: Int
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) extends BlackBox(Map(
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"pioWidth" -> core.IntParam(pioWidth)
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)) with HasBlackBoxResource {
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val io = IO(new loopbackBlackBoxIO(
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pioWidth
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))
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// setResource("top.v")
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}
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case class loopbackParams(
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pioWidth: Int = 32,
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cacheBlockBytes: Int
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)
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class LloopbackBase(c: loopbackParams)(implicit p: Parameters) extends LazyModule {
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val device = new SimpleDevice("loopback", Seq("sifive,loopback-v0"))
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val pioWidth = c.pioWidth
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val ioBridgeSource = BundleBridgeSource(() => new loopbackBlackBoxIO(
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c.pioWidth
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))
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class LloopbackBaseImp extends LazyRawModuleImp(this) {
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val blackbox = Module(new loopback(
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c.pioWidth
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))
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// interface wiring 2
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// port wiring
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blackbox.io.odata := ioBridgeSource.bundle.odata
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blackbox.io.oenable := ioBridgeSource.bundle.oenable
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ioBridgeSource.bundle.idata := blackbox.io.idata
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// interface alias
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// interface wiring
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}
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lazy val module = new LloopbackBaseImp
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}
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case class NloopbackTopParams(
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blackbox: loopbackParams
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) {
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def setBurstBytes(x: Int): NloopbackTopParams = this.copy()
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}
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object NloopbackTopParams {
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def defaults(
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cacheBlockBytes: Int
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) = NloopbackTopParams(
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blackbox = loopbackParams(
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cacheBlockBytes = cacheBlockBytes
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)
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)
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}
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class NloopbackTopBase(c: NloopbackTopParams)(implicit p: Parameters) extends SimpleLazyModule {
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val imp = LazyModule(new Lloopback(c.blackbox))
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val pioWidth: Int = c.blackbox.pioWidth
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// no channel node
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}
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object NloopbackTopBase {
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def attach(c: NloopbackTopParams)(bap: BlockAttachParams): NloopbackTop = {
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implicit val p: Parameters = bap.p
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val loopback_top = LazyModule(new NloopbackTop(c))
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// no channel attachment
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loopback_top
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}
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}
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class WithloopbackTopBase (
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) extends Config((site, here, up) => {
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case BlockDescriptorKey =>
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BlockDescriptor(
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name = "loopback",
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place = NloopbackTop.attach(NloopbackTopParams.defaults(
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cacheBlockBytes = site(CacheBlockBytes)
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))
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) +: up(BlockDescriptorKey, site)
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})

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