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ipts.patch
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ipts.patch
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From 2034ee48e92c8cae6c8aa6590a5ac8b55a0b48bf Mon Sep 17 00:00:00 2001
From: Jake Day <[email protected]>
Date: Thu, 6 Jun 2019 13:41:03 -0400
Subject: [PATCH 05/12] ipts
---
drivers/gpu/drm/i915/Makefile | 3 +
drivers/gpu/drm/i915/i915_drv.c | 13 +
drivers/gpu/drm/i915/i915_drv.h | 3 +
drivers/gpu/drm/i915/i915_gem_context.c | 12 +
drivers/gpu/drm/i915/i915_irq.c | 7 +-
drivers/gpu/drm/i915/i915_params.c | 5 +-
drivers/gpu/drm/i915/i915_params.h | 5 +-
drivers/gpu/drm/i915/intel_dp.c | 4 +-
drivers/gpu/drm/i915/intel_guc.h | 1 +
drivers/gpu/drm/i915/intel_guc_submission.c | 90 +-
drivers/gpu/drm/i915/intel_guc_submission.h | 4 +
drivers/gpu/drm/i915/intel_ipts.c | 657 ++++++++++++
drivers/gpu/drm/i915/intel_ipts.h | 36 +
drivers/gpu/drm/i915/intel_lrc.c | 12 +-
drivers/gpu/drm/i915/intel_lrc.h | 9 +
drivers/gpu/drm/i915/intel_panel.c | 7 +
drivers/hid/hid-multitouch.c | 22 +-
drivers/misc/Kconfig | 1 +
drivers/misc/Makefile | 1 +
drivers/misc/ipts/Kconfig | 9 +
drivers/misc/ipts/Makefile | 13 +
drivers/misc/ipts/ipts-binary-spec.h | 118 +++
drivers/misc/ipts/ipts-dbgfs.c | 152 +++
drivers/misc/ipts/ipts-gfx.c | 184 ++++
drivers/misc/ipts/ipts-gfx.h | 24 +
drivers/misc/ipts/ipts-hid.c | 456 ++++++++
drivers/misc/ipts/ipts-hid.h | 34 +
drivers/misc/ipts/ipts-kernel.c | 1050 +++++++++++++++++++
drivers/misc/ipts/ipts-kernel.h | 23 +
drivers/misc/ipts/ipts-mei-msgs.h | 585 +++++++++++
drivers/misc/ipts/ipts-mei.c | 282 +++++
drivers/misc/ipts/ipts-msg-handler.c | 431 ++++++++
drivers/misc/ipts/ipts-msg-handler.h | 32 +
drivers/misc/ipts/ipts-resource.c | 277 +++++
drivers/misc/ipts/ipts-resource.h | 30 +
drivers/misc/ipts/ipts-sensor-regs.h | 700 +++++++++++++
drivers/misc/ipts/ipts-state.h | 29 +
drivers/misc/ipts/ipts.h | 200 ++++
drivers/misc/mei/hw-me-regs.h | 1 +
drivers/misc/mei/pci-me.c | 1 +
include/linux/intel_ipts_if.h | 75 ++
41 files changed, 5573 insertions(+), 25 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_ipts.c
create mode 100644 drivers/gpu/drm/i915/intel_ipts.h
create mode 100644 drivers/misc/ipts/Kconfig
create mode 100644 drivers/misc/ipts/Makefile
create mode 100644 drivers/misc/ipts/ipts-binary-spec.h
create mode 100644 drivers/misc/ipts/ipts-dbgfs.c
create mode 100644 drivers/misc/ipts/ipts-gfx.c
create mode 100644 drivers/misc/ipts/ipts-gfx.h
create mode 100644 drivers/misc/ipts/ipts-hid.c
create mode 100644 drivers/misc/ipts/ipts-hid.h
create mode 100644 drivers/misc/ipts/ipts-kernel.c
create mode 100644 drivers/misc/ipts/ipts-kernel.h
create mode 100644 drivers/misc/ipts/ipts-mei-msgs.h
create mode 100644 drivers/misc/ipts/ipts-mei.c
create mode 100644 drivers/misc/ipts/ipts-msg-handler.c
create mode 100644 drivers/misc/ipts/ipts-msg-handler.h
create mode 100644 drivers/misc/ipts/ipts-resource.c
create mode 100644 drivers/misc/ipts/ipts-resource.h
create mode 100644 drivers/misc/ipts/ipts-sensor-regs.h
create mode 100644 drivers/misc/ipts/ipts-state.h
create mode 100644 drivers/misc/ipts/ipts.h
create mode 100644 include/linux/intel_ipts_if.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 1787e1299b1b..43df660cd309 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -164,6 +164,9 @@ i915-y += dvo_ch7017.o \
vlv_dsi_pll.o \
intel_vdsc.o
+# intel precise touch & stylus
+i915-y += intel_ipts.o
+
# Post-mortem debug and GPU hang state capture
i915-$(CONFIG_DRM_I915_CAPTURE_ERROR) += i915_gpu_error.o
i915-$(CONFIG_DRM_I915_SELFTEST) += \
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9df65d386d11..40f24ebf88ba 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -56,6 +56,7 @@
#include "intel_drv.h"
#include "intel_uc.h"
#include "intel_workarounds.h"
+#include "intel_ipts.h"
static struct drm_driver driver;
@@ -711,6 +712,9 @@ static int i915_load_modeset_init(struct drm_device *dev)
intel_init_ipc(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
+ intel_ipts_init(dev);
+
return 0;
cleanup_gem:
@@ -1748,6 +1752,9 @@ void i915_driver_unload(struct drm_device *dev)
disable_rpm_wakeref_asserts(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
+ intel_ipts_cleanup(dev);
+
i915_driver_unregister(dev_priv);
/* Flush any external code that still may be under the RCU lock */
@@ -1884,6 +1891,9 @@ static int i915_drm_suspend(struct drm_device *dev)
struct pci_dev *pdev = dev_priv->drm.pdev;
pci_power_t opregion_target_state;
+ if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
+ intel_ipts_suspend(dev);
+
disable_rpm_wakeref_asserts(dev_priv);
/* We do a lot of poking in a lot of registers, make sure they work
@@ -2080,6 +2090,9 @@ static int i915_drm_resume(struct drm_device *dev)
enable_rpm_wakeref_asserts(dev_priv);
+ if (INTEL_GEN(dev_priv) >= 9 && i915_modparams.enable_guc && i915_modparams.enable_ipts)
+ intel_ipts_resume(dev);
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a67a63b5aa84..dcb51f687a44 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3115,6 +3115,9 @@ void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
struct sg_table *pages);
+struct i915_gem_context *
+i915_gem_context_create_ipts(struct drm_device *dev);
+
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 280813a4bf82..0e9a93bcf72b 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -555,6 +555,18 @@ static bool needs_preempt_context(struct drm_i915_private *i915)
return HAS_LOGICAL_RING_PREEMPTION(i915);
}
+struct i915_gem_context *i915_gem_context_create_ipts(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = to_i915(dev);
+ struct i915_gem_context *ctx;
+
+ BUG_ON(!mutex_is_locked(&dev->struct_mutex));
+
+ ctx = i915_gem_create_context(dev_priv, NULL);
+
+ return ctx;
+}
+
int i915_gem_contexts_init(struct drm_i915_private *dev_priv)
{
struct i915_gem_context *ctx;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 441d2674b272..ad066f43cd4f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -37,6 +37,7 @@
#include "i915_drv.h"
#include "i915_trace.h"
#include "intel_drv.h"
+#include "intel_ipts.h"
/**
* DOC: interrupt handling
@@ -1452,6 +1453,9 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
tasklet |= USES_GUC_SUBMISSION(engine->i915);
}
+ if (iir & GT_RENDER_PIPECTL_NOTIFY_INTERRUPT && i915_modparams.enable_ipts)
+ intel_ipts_notify_complete();
+
if (tasklet)
tasklet_hi_schedule(&engine->execlists.tasklet);
}
@@ -3879,7 +3883,8 @@ static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
{
/* These are interrupts we'll toggle with the ring mask register */
u32 gt_interrupts[] = {
- GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+ GT_RENDER_PIPECTL_NOTIFY_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+ GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index b5be0abbba35..831f2bcae687 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -143,7 +143,10 @@ i915_param_named_unsafe(edp_vswing, int, 0400,
i915_param_named_unsafe(enable_guc, int, 0400,
"Enable GuC load for GuC submission and/or HuC load. "
"Required functionality can be selected using bitmask values. "
- "(-1=auto, 0=disable [default], 1=GuC submission, 2=HuC load)");
+ "(-1=auto [default], 0=disable, 1=GuC submission, 2=HuC load)");
+
+i915_param_named_unsafe(enable_ipts, int, 0400,
+ "Enable IPTS Touchscreen and Pen support (default: 1)");
i915_param_named(guc_log_level, int, 0400,
"GuC firmware logging level. Requires GuC to be loaded. "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 3f14e9881a0d..e314a2414041 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,7 +54,7 @@ struct drm_printer;
param(int, disable_power_well, -1) \
param(int, enable_ips, 1) \
param(int, invert_brightness, 0) \
- param(int, enable_guc, 0) \
+ param(int, enable_guc, -1) \
param(int, guc_log_level, -1) \
param(char *, guc_firmware_path, NULL) \
param(char *, huc_firmware_path, NULL) \
@@ -76,7 +76,8 @@ struct drm_printer;
param(bool, nuclear_pageflip, false) \
param(bool, enable_dp_mst, true) \
param(bool, enable_dpcd_backlight, false) \
- param(bool, enable_gvt, false)
+ param(bool, enable_gvt, false) \
+ param(int, enable_ipts, 1)
#define MEMBER(T, member, ...) T member;
struct i915_params {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 48da4a969a0a..c332d0686085 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -2874,8 +2874,8 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
return;
if (mode != DRM_MODE_DPMS_ON) {
- if (downstream_hpd_needs_d0(intel_dp))
- return;
+ //if (downstream_hpd_needs_d0(intel_dp))
+ // return;
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
DP_SET_POWER_D3);
diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 744220296653..459589588063 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -66,6 +66,7 @@ struct intel_guc {
struct intel_guc_client *execbuf_client;
struct intel_guc_client *preempt_client;
+ struct intel_guc_client *ipts_client;
struct guc_preempt_work preempt_work[I915_NUM_ENGINES];
struct workqueue_struct *preempt_wq;
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.c b/drivers/gpu/drm/i915/intel_guc_submission.c
index 8bc8aa54aa35..9ddd5ace6f6f 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/intel_guc_submission.c
@@ -94,12 +94,17 @@ static inline struct i915_priolist *to_priolist(struct rb_node *rb)
static inline bool is_high_priority(struct intel_guc_client *client)
{
- return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH ||
- client->priority == GUC_CLIENT_PRIORITY_HIGH);
+ return (client->priority == GUC_CLIENT_PRIORITY_HIGH);
+}
+
+static inline bool is_high_priority_kmd(struct intel_guc_client *client)
+{
+ return (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH);
}
static int reserve_doorbell(struct intel_guc_client *client)
{
+ struct drm_i915_private *dev_priv = guc_to_i915(client->guc);
unsigned long offset;
unsigned long end;
u16 id;
@@ -112,10 +117,15 @@ static int reserve_doorbell(struct intel_guc_client *client)
* priority contexts, the second half for high-priority ones.
*/
offset = 0;
- end = GUC_NUM_DOORBELLS / 2;
- if (is_high_priority(client)) {
- offset = end;
- end += offset;
+ if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
+ end = GUC_NUM_DOORBELLS;
+ }
+ else {
+ end = GUC_NUM_DOORBELLS/2;
+ if (is_high_priority(client)) {
+ offset = end;
+ end += offset;
+ }
}
id = find_next_zero_bit(client->guc->doorbell_bitmap, end, offset);
@@ -373,9 +383,15 @@ static void guc_stage_desc_init(struct intel_guc_client *client)
desc = __get_stage_desc(client);
memset(desc, 0, sizeof(*desc));
- desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE |
- GUC_STAGE_DESC_ATTR_KERNEL;
- if (is_high_priority(client))
+ desc->attribute = GUC_STAGE_DESC_ATTR_ACTIVE;
+ if ((client->priority == GUC_CLIENT_PRIORITY_KMD_NORMAL) ||
+ (client->priority == GUC_CLIENT_PRIORITY_KMD_HIGH)) {
+ desc->attribute |= GUC_STAGE_DESC_ATTR_KERNEL;
+ } else {
+ desc->attribute |= GUC_STAGE_DESC_ATTR_PCH;
+ }
+
+ if (is_high_priority_kmd(client))
desc->attribute |= GUC_STAGE_DESC_ATTR_PREEMPT;
desc->stage_id = client->stage_id;
desc->priority = client->priority;
@@ -1204,7 +1220,8 @@ static void guc_interrupts_capture(struct drm_i915_private *dev_priv)
I915_WRITE(RING_MODE_GEN7(engine), irqs);
/* route USER_INTERRUPT to Host, all others are sent to GuC. */
- irqs = GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
+ irqs = (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT)
+ << GEN8_RCS_IRQ_SHIFT |
GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT;
/* These three registers have the same bit definitions */
I915_WRITE(GUC_BCS_RCS_IER, ~irqs);
@@ -1345,6 +1362,59 @@ void intel_guc_submission_disable(struct intel_guc *guc)
guc_clients_disable(guc);
}
+int i915_guc_ipts_submission_enable(struct drm_i915_private *dev_priv,
+ struct i915_gem_context *ctx)
+{
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc_client *client;
+ int err;
+ int ret;
+
+ /* client for execbuf submission */
+ client = guc_client_alloc(dev_priv,
+ INTEL_INFO(dev_priv)->ring_mask,
+ IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ? GUC_CLIENT_PRIORITY_HIGH : GUC_CLIENT_PRIORITY_NORMAL,
+ ctx);
+ if (IS_ERR(client)) {
+ DRM_ERROR("Failed to create normal GuC client!\n");
+ return -ENOMEM;
+ }
+
+ guc->ipts_client = client;
+
+ err = intel_guc_sample_forcewake(guc);
+ if (err)
+ return err;
+
+ ret = __guc_client_enable(guc->ipts_client);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+void i915_guc_ipts_submission_disable(struct drm_i915_private *dev_priv)
+{
+ struct intel_guc *guc = &dev_priv->guc;
+
+ if (!guc->ipts_client)
+ return;
+
+ __guc_client_disable(guc->ipts_client);
+ guc_client_free(guc->ipts_client);
+ guc->ipts_client = NULL;
+}
+
+void i915_guc_ipts_reacquire_doorbell(struct drm_i915_private *dev_priv)
+{
+ struct intel_guc *guc = &dev_priv->guc;
+
+ int err = __guc_allocate_doorbell(guc, guc->ipts_client->stage_id);
+
+ if (err)
+ DRM_ERROR("Not able to reacquire IPTS doorbell\n");
+}
+
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
#include "selftests/intel_guc.c"
#endif
diff --git a/drivers/gpu/drm/i915/intel_guc_submission.h b/drivers/gpu/drm/i915/intel_guc_submission.h
index 169c54568340..245a8de1df2a 100644
--- a/drivers/gpu/drm/i915/intel_guc_submission.h
+++ b/drivers/gpu/drm/i915/intel_guc_submission.h
@@ -83,5 +83,9 @@ void intel_guc_submission_disable(struct intel_guc *guc);
void intel_guc_submission_fini(struct intel_guc *guc);
int intel_guc_preempt_work_create(struct intel_guc *guc);
void intel_guc_preempt_work_destroy(struct intel_guc *guc);
+int i915_guc_ipts_submission_enable(struct drm_i915_private *dev_priv,
+ struct i915_gem_context *ctx);
+void i915_guc_ipts_submission_disable(struct drm_i915_private *dev_priv);
+void i915_guc_ipts_reacquire_doorbell(struct drm_i915_private *dev_priv);
#endif
diff --git a/drivers/gpu/drm/i915/intel_ipts.c b/drivers/gpu/drm/i915/intel_ipts.c
new file mode 100644
index 000000000000..b276a2f7839c
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_ipts.c
@@ -0,0 +1,657 @@
+/*
+ * Copyright 2016 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/intel_ipts_if.h>
+#include <drm/drmP.h>
+
+#include "intel_guc_submission.h"
+#include "i915_drv.h"
+
+#define SUPPORTED_IPTS_INTERFACE_VERSION 1
+
+#define REACQUIRE_DB_THRESHOLD 10
+#define DB_LOST_CHECK_STEP1_INTERVAL 2500 /* ms */
+#define DB_LOST_CHECK_STEP2_INTERVAL 1000 /* ms */
+
+/* intel IPTS ctx for ipts support */
+typedef struct intel_ipts {
+ struct drm_device *dev;
+ struct i915_gem_context *ipts_context;
+ intel_ipts_callback_t ipts_clbks;
+
+ /* buffers' list */
+ struct {
+ spinlock_t lock;
+ struct list_head list;
+ } buffers;
+
+ void *data;
+
+ struct delayed_work reacquire_db_work;
+ intel_ipts_wq_info_t wq_info;
+ u32 old_tail;
+ u32 old_head;
+ bool need_reacquire_db;
+
+ bool connected;
+ bool initialized;
+} intel_ipts_t;
+
+intel_ipts_t intel_ipts;
+
+typedef struct intel_ipts_object {
+ struct list_head list;
+ struct drm_i915_gem_object *gem_obj;
+ void *cpu_addr;
+} intel_ipts_object_t;
+
+static intel_ipts_object_t *ipts_object_create(size_t size, u32 flags)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ intel_ipts_object_t *obj = NULL;
+ struct drm_i915_gem_object *gem_obj = NULL;
+ int ret = 0;
+
+ obj = kzalloc(sizeof(*obj), GFP_KERNEL);
+ if (!obj)
+ return NULL;
+
+ size = roundup(size, PAGE_SIZE);
+ if (size == 0) {
+ ret = -EINVAL;
+ goto err_out;
+ }
+
+ /* Allocate the new object */
+ gem_obj = i915_gem_object_create(dev_priv, size);
+ if (gem_obj == NULL) {
+ ret = -ENOMEM;
+ goto err_out;
+ }
+
+ if (flags & IPTS_BUF_FLAG_CONTIGUOUS) {
+ ret = i915_gem_object_attach_phys(gem_obj, PAGE_SIZE);
+ if (ret) {
+ pr_info(">> ipts no contiguous : %d\n", ret);
+ goto err_out;
+ }
+ }
+
+ obj->gem_obj = gem_obj;
+
+ spin_lock(&intel_ipts.buffers.lock);
+ list_add_tail(&obj->list, &intel_ipts.buffers.list);
+ spin_unlock(&intel_ipts.buffers.lock);
+
+ return obj;
+
+err_out:
+ if (gem_obj)
+ i915_gem_free_object(&gem_obj->base);
+
+ if (obj)
+ kfree(obj);
+
+ return NULL;
+}
+
+static void ipts_object_free(intel_ipts_object_t* obj)
+{
+ spin_lock(&intel_ipts.buffers.lock);
+ list_del(&obj->list);
+ spin_unlock(&intel_ipts.buffers.lock);
+
+ i915_gem_free_object(&obj->gem_obj->base);
+ kfree(obj);
+}
+
+static int ipts_object_pin(intel_ipts_object_t* obj,
+ struct i915_gem_context *ipts_ctx)
+{
+ struct i915_address_space *vm = NULL;
+ struct i915_vma *vma = NULL;
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ int ret = 0;
+
+ if (ipts_ctx->ppgtt) {
+ vm = &ipts_ctx->ppgtt->vm;
+ } else {
+ vm = &dev_priv->ggtt.vm;
+ }
+
+ vma = i915_vma_instance(obj->gem_obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("cannot find or create vma\n");
+ return -1;
+ }
+
+ ret = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_USER);
+
+ return ret;
+}
+
+static void ipts_object_unpin(intel_ipts_object_t *obj)
+{
+ /* TBD: Add support */
+}
+
+static void* ipts_object_map(intel_ipts_object_t *obj)
+{
+
+ return i915_gem_object_pin_map(obj->gem_obj, I915_MAP_WB);
+}
+
+static void ipts_object_unmap(intel_ipts_object_t* obj)
+{
+ i915_gem_object_unpin_map(obj->gem_obj);
+ obj->cpu_addr = NULL;
+}
+
+static int create_ipts_context(void)
+{
+ struct i915_gem_context *ipts_ctx = NULL;
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ struct intel_context *ce = NULL;
+ struct intel_context *pin_ret;
+ int ret = 0;
+
+ /* Initialize the context right away.*/
+ ret = i915_mutex_lock_interruptible(intel_ipts.dev);
+ if (ret) {
+ DRM_ERROR("i915_mutex_lock_interruptible failed \n");
+ return ret;
+ }
+
+ ipts_ctx = i915_gem_context_create_ipts(intel_ipts.dev);
+ if (IS_ERR(ipts_ctx)) {
+ DRM_ERROR("Failed to create IPTS context (error %ld)\n",
+ PTR_ERR(ipts_ctx));
+ ret = PTR_ERR(ipts_ctx);
+ goto err_unlock;
+ }
+
+ ce = to_intel_context(ipts_ctx, dev_priv->engine[RCS]);
+ if (IS_ERR(ce)) {
+ DRM_ERROR("Failed to create intel context (error %ld)\n",
+ PTR_ERR(ce));
+ ret = PTR_ERR(ce);
+ goto err_unlock;
+ }
+
+ ret = execlists_context_deferred_alloc(ipts_ctx, dev_priv->engine[RCS], ce);
+ if (ret) {
+ DRM_DEBUG("lr context allocation failed : %d\n", ret);
+ goto err_ctx;
+ }
+
+ pin_ret = execlists_context_pin(dev_priv->engine[RCS], ipts_ctx);
+ if (IS_ERR(pin_ret)) {
+ DRM_DEBUG("lr context pinning failed : %ld\n", PTR_ERR(pin_ret));
+ goto err_ctx;
+ }
+
+ /* Release the mutex */
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+
+ spin_lock_init(&intel_ipts.buffers.lock);
+ INIT_LIST_HEAD(&intel_ipts.buffers.list);
+
+ intel_ipts.ipts_context = ipts_ctx;
+
+ return 0;
+
+err_ctx:
+ if (ipts_ctx)
+ i915_gem_context_put(ipts_ctx);
+
+err_unlock:
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+
+ return ret;
+}
+
+static void destroy_ipts_context(void)
+{
+ struct i915_gem_context *ipts_ctx = NULL;
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ struct intel_context *ce = NULL;
+ int ret = 0;
+
+ ipts_ctx = intel_ipts.ipts_context;
+
+ ce = to_intel_context(ipts_ctx, dev_priv->engine[RCS]);
+
+ /* Initialize the context right away.*/
+ ret = i915_mutex_lock_interruptible(intel_ipts.dev);
+ if (ret) {
+ DRM_ERROR("i915_mutex_lock_interruptible failed \n");
+ return;
+ }
+
+ execlists_context_unpin(ce);
+ i915_gem_context_put(ipts_ctx);
+
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+}
+
+int intel_ipts_notify_complete(void)
+{
+ if (intel_ipts.ipts_clbks.workload_complete)
+ intel_ipts.ipts_clbks.workload_complete(intel_ipts.data);
+
+ return 0;
+}
+
+int intel_ipts_notify_backlight_status(bool backlight_on)
+{
+ if (intel_ipts.ipts_clbks.notify_gfx_status) {
+ if (backlight_on) {
+ intel_ipts.ipts_clbks.notify_gfx_status(
+ IPTS_NOTIFY_STA_BACKLIGHT_ON,
+ intel_ipts.data);
+ schedule_delayed_work(&intel_ipts.reacquire_db_work,
+ msecs_to_jiffies(DB_LOST_CHECK_STEP1_INTERVAL));
+ } else {
+ intel_ipts.ipts_clbks.notify_gfx_status(
+ IPTS_NOTIFY_STA_BACKLIGHT_OFF,
+ intel_ipts.data);
+ cancel_delayed_work(&intel_ipts.reacquire_db_work);
+ }
+ }
+
+ return 0;
+}
+
+static void intel_ipts_reacquire_db(intel_ipts_t *intel_ipts_p)
+{
+ int ret = 0;
+
+ ret = i915_mutex_lock_interruptible(intel_ipts_p->dev);
+ if (ret) {
+ DRM_ERROR("i915_mutex_lock_interruptible failed \n");
+ return;
+ }
+
+ /* Reacquire the doorbell */
+ i915_guc_ipts_reacquire_doorbell(intel_ipts_p->dev->dev_private);
+
+ mutex_unlock(&intel_ipts_p->dev->struct_mutex);
+
+ return;
+}
+
+static int intel_ipts_get_wq_info(uint64_t gfx_handle,
+ intel_ipts_wq_info_t *wq_info)
+{
+ if (gfx_handle != (uint64_t)&intel_ipts) {
+ DRM_ERROR("invalid gfx handle\n");
+ return -EINVAL;
+ }
+
+ *wq_info = intel_ipts.wq_info;
+
+ intel_ipts_reacquire_db(&intel_ipts);
+ schedule_delayed_work(&intel_ipts.reacquire_db_work,
+ msecs_to_jiffies(DB_LOST_CHECK_STEP1_INTERVAL));
+
+ return 0;
+}
+
+static int set_wq_info(void)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ struct intel_guc *guc = &dev_priv->guc;
+ struct intel_guc_client *client;
+ struct guc_process_desc *desc;
+ void *base = NULL;
+ intel_ipts_wq_info_t *wq_info;
+ u64 phy_base = 0;
+
+ wq_info = &intel_ipts.wq_info;
+
+ client = guc->ipts_client;
+ if (!client) {
+ DRM_ERROR("IPTS GuC client is NOT available\n");
+ return -EINVAL;
+ }
+
+ base = client->vaddr;
+ desc = (struct guc_process_desc *)((u64)base + client->proc_desc_offset);
+
+ desc->wq_base_addr = (u64)base + GUC_DB_SIZE;
+ desc->db_base_addr = (u64)base + client->doorbell_offset;
+
+ /* IPTS expects physical addresses to pass it to ME */
+ phy_base = sg_dma_address(client->vma->pages->sgl);
+
+ wq_info->db_addr = desc->db_base_addr;
+ wq_info->db_phy_addr = phy_base + client->doorbell_offset;
+ wq_info->db_cookie_offset = offsetof(struct guc_doorbell_info, cookie);
+ wq_info->wq_addr = desc->wq_base_addr;
+ wq_info->wq_phy_addr = phy_base + GUC_DB_SIZE;
+ wq_info->wq_head_addr = (u64)&desc->head;
+ wq_info->wq_head_phy_addr = phy_base + client->proc_desc_offset +
+ offsetof(struct guc_process_desc, head);
+ wq_info->wq_tail_addr = (u64)&desc->tail;
+ wq_info->wq_tail_phy_addr = phy_base + client->proc_desc_offset +
+ offsetof(struct guc_process_desc, tail);
+ wq_info->wq_size = desc->wq_size_bytes;
+
+ return 0;
+}
+
+static int intel_ipts_init_wq(void)
+{
+ int ret = 0;
+
+ ret = i915_mutex_lock_interruptible(intel_ipts.dev);
+ if (ret) {
+ DRM_ERROR("i915_mutex_lock_interruptible failed\n");
+ return ret;
+ }
+
+ /* disable IPTS submission */
+ i915_guc_ipts_submission_disable(intel_ipts.dev->dev_private);
+
+ /* enable IPTS submission */
+ ret = i915_guc_ipts_submission_enable(intel_ipts.dev->dev_private,
+ intel_ipts.ipts_context);
+ if (ret) {
+ DRM_ERROR("i915_guc_ipts_submission_enable failed : %d\n", ret);
+ goto out;
+ }
+
+ ret = set_wq_info();
+ if (ret) {
+ DRM_ERROR("set_wq_info failed\n");
+ goto out;
+ }
+
+out:
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+
+ return ret;
+}
+
+static void intel_ipts_release_wq(void)
+{
+ int ret = 0;
+
+ ret = i915_mutex_lock_interruptible(intel_ipts.dev);
+ if (ret) {
+ DRM_ERROR("i915_mutex_lock_interruptible failed\n");
+ return;
+ }
+
+ /* disable IPTS submission */
+ i915_guc_ipts_submission_disable(intel_ipts.dev->dev_private);
+
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+}
+
+static int intel_ipts_map_buffer(u64 gfx_handle, intel_ipts_mapbuffer_t *mapbuf)
+{
+ intel_ipts_object_t* obj;
+ struct i915_gem_context *ipts_ctx = NULL;
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ struct i915_address_space *vm = NULL;
+ struct i915_vma *vma = NULL;
+ int ret = 0;
+
+ if (gfx_handle != (uint64_t)&intel_ipts) {
+ DRM_ERROR("invalid gfx handle\n");
+ return -EINVAL;
+ }
+
+ /* Acquire mutex first */
+ ret = i915_mutex_lock_interruptible(intel_ipts.dev);
+ if (ret) {
+ DRM_ERROR("i915_mutex_lock_interruptible failed \n");
+ return -EINVAL;
+ }
+
+ obj = ipts_object_create(mapbuf->size, mapbuf->flags);
+ if (!obj)
+ return -ENOMEM;
+
+ ipts_ctx = intel_ipts.ipts_context;
+ ret = ipts_object_pin(obj, ipts_ctx);
+ if (ret) {
+ DRM_ERROR("Not able to pin iTouch obj\n");
+ ipts_object_free(obj);
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+ return -ENOMEM;
+ }
+
+ if (mapbuf->flags & IPTS_BUF_FLAG_CONTIGUOUS) {
+ obj->cpu_addr = obj->gem_obj->phys_handle->vaddr;
+ } else {
+ obj->cpu_addr = ipts_object_map(obj);
+ }
+
+ if (ipts_ctx->ppgtt) {
+ vm = &ipts_ctx->ppgtt->vm;
+ } else {
+ vm = &dev_priv->ggtt.vm;
+ }
+
+ vma = i915_vma_instance(obj->gem_obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ DRM_ERROR("cannot find or create vma\n");
+ return -EINVAL;
+ }
+
+ mapbuf->gfx_addr = (void*)vma->node.start;
+ mapbuf->cpu_addr = (void*)obj->cpu_addr;
+ mapbuf->buf_handle = (u64)obj;
+ if (mapbuf->flags & IPTS_BUF_FLAG_CONTIGUOUS) {
+ mapbuf->phy_addr = (u64)obj->gem_obj->phys_handle->busaddr;
+ }
+
+ /* Release the mutex */
+ mutex_unlock(&intel_ipts.dev->struct_mutex);
+
+ return 0;
+}
+
+static int intel_ipts_unmap_buffer(uint64_t gfx_handle, uint64_t buf_handle)
+{
+ intel_ipts_object_t* obj = (intel_ipts_object_t*)buf_handle;
+
+ if (gfx_handle != (uint64_t)&intel_ipts) {
+ DRM_ERROR("invalid gfx handle\n");
+ return -EINVAL;
+ }
+
+ if (!obj->gem_obj->phys_handle)
+ ipts_object_unmap(obj);
+ ipts_object_unpin(obj);
+ ipts_object_free(obj);
+
+ return 0;
+}
+
+int intel_ipts_connect(intel_ipts_connect_t *ipts_connect)
+{
+ struct drm_i915_private *dev_priv = to_i915(intel_ipts.dev);
+ int ret = 0;
+
+ if (!intel_ipts.initialized)
+ return -EIO;
+
+ if (ipts_connect && ipts_connect->if_version <=
+ SUPPORTED_IPTS_INTERFACE_VERSION) {
+
+ /* return gpu operations for ipts */
+ ipts_connect->ipts_ops.get_wq_info = intel_ipts_get_wq_info;
+ ipts_connect->ipts_ops.map_buffer = intel_ipts_map_buffer;
+ ipts_connect->ipts_ops.unmap_buffer = intel_ipts_unmap_buffer;
+ ipts_connect->gfx_version = INTEL_INFO(dev_priv)->gen;
+ ipts_connect->gfx_handle = (uint64_t)&intel_ipts;
+
+ /* save callback and data */
+ intel_ipts.data = ipts_connect->data;
+ intel_ipts.ipts_clbks = ipts_connect->ipts_cb;
+
+ intel_ipts.connected = true;
+ } else {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(intel_ipts_connect);
+
+void intel_ipts_disconnect(uint64_t gfx_handle)
+{
+ if (!intel_ipts.initialized)
+ return;
+
+ if (gfx_handle != (uint64_t)&intel_ipts ||
+ intel_ipts.connected == false) {
+ DRM_ERROR("invalid gfx handle\n");
+ return;
+ }
+
+ intel_ipts.data = 0;
+ memset(&intel_ipts.ipts_clbks, 0, sizeof(intel_ipts_callback_t));
+
+ intel_ipts.connected = false;
+}
+EXPORT_SYMBOL_GPL(intel_ipts_disconnect);
+
+static void reacquire_db_work_func(struct work_struct *work)
+{
+ struct delayed_work *d_work = container_of(work, struct delayed_work,
+ work);
+ intel_ipts_t *intel_ipts_p = container_of(d_work, intel_ipts_t,
+ reacquire_db_work);
+ u32 head;
+ u32 tail;
+ u32 size;
+ u32 load;
+
+ head = *(u32*)intel_ipts_p->wq_info.wq_head_addr;
+ tail = *(u32*)intel_ipts_p->wq_info.wq_tail_addr;
+ size = intel_ipts_p->wq_info.wq_size;
+
+ if (head >= tail)
+ load = head - tail;
+ else
+ load = head + size - tail;
+
+ if (load < REACQUIRE_DB_THRESHOLD) {
+ intel_ipts_p->need_reacquire_db = false;
+ goto reschedule_work;
+ }
+
+ if (intel_ipts_p->need_reacquire_db) {
+ if (intel_ipts_p->old_head == head && intel_ipts_p->old_tail == tail)
+ intel_ipts_reacquire_db(intel_ipts_p);
+ intel_ipts_p->need_reacquire_db = false;
+ } else {