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AXI read/write converter broken when slices depth > 0 #164

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johanpel opened this issue Jul 18, 2019 · 1 comment
Open

AXI read/write converter broken when slices depth > 0 #164

johanpel opened this issue Jul 18, 2019 · 1 comment
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bug Something isn't working lang:vhdl VHDL related issue

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@johanpel johanpel added the bug Something isn't working label Jul 18, 2019
johanpel added a commit that referenced this issue Jul 18, 2019
@johanpel
Temporarily work around for #164
467e2f1
johanpel added a commit that referenced this issue Jul 18, 2019
@johanpel
Merge pull request #166 from abs-tudelft/fletchgen-fixes
6407f00 
Temporary work around for #164
@johanpel
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seems it also applies to the read converter

@johanpel johanpel changed the title [Hardware] AXI write converter broken when slices depth > 0 [Hardware] AXI read/write converter broken when slices depth > 0 Jul 19, 2019
johanpel added a commit that referenced this issue Jul 19, 2019
@johanpel
Merge pull request #168 from abs-tudelft/fletchgen-fixes
c296da3 
[Fletchgen] Temporarily work around problem #164 with AXI read converter slices
@mbrobbel mbrobbel added the lang:vhdl VHDL related issue label Aug 28, 2019
@mbrobbel mbrobbel changed the title [Hardware] AXI read/write converter broken when slices depth > 0 AXI read/write converter broken when slices depth > 0 Aug 28, 2019
@johanpel johanpel added this to the v0.1 milestone Sep 24, 2019
@johanpel johanpel modified the milestones: v0.0.10, v0.0.11 Nov 6, 2019
@johanpel johanpel removed this from the v0.0.17 milestone Jan 11, 2021
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@mbrobbel @johanpel