This IP cannot be used in Vivado 2023.2 because of failing range check in synthesis

[cg-sat]

I found an old hardware design with this IP core in it made with Vivado 2021.1 and tried to synthesis it with Vivado 2023.2, but I get an error message saying me that the COUNT signal is leaving its range from 0..3 in some code. And the compiler is right, the following line tries to update COUNT from 3 to 4:

zynq-axi-dna/ip_repo/zynq_AXI_DNA_1.0/src/DNA_read.vhd

Line 148 in f5b7237

COUNT <= COUNT + 1;

I don't know how older Vivado versions handled that code, maybe they implicitly set COUNT to 0. For me the solution was to just delete the block from the design, because my focus was on testing something else.

This issue exists to inform others about it, because my internet search for the exact failure message uncovered nothing useful. Maybe this helps others to reduce their invested time.

The solution would be to change line 148 to:

COUNT <= 0;

The lines 149 and 150 can be deleted, because they are not reachble.