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axil.cpp
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////////////////////////////////////////////////////////////////////////////////
//
// Filename: sw/bus/axil.cpp
//
// Project: AutoFPGA, a utility for composing FPGA designs from peripherals
// {{{
// Purpose:
// Tags used:
//
// BUS.WIDTH
// BUS.AWID
//
// SLAVE.TYPE:
// - SINGLE
// - DOUBLE
// - OTHER/MEMORY/BUS
// SLAVE.OPTIONS=
// // string of case-insensitive options
// ROM (slave has no write ports)
// WOM (slave has no read ports)
// FULL (default:slave has no all ports, not just the ports used)
// SLAVE.SHARE=
// // slave shares parts of the interface with the other listed slaves
//
// MASTER.TYPE=
// (currently ignored)
//
// INTERCONNECT.TYPE
// - SINGLE
// - CROSSBAR
//
// INTERCONNECT.MASTERS
// = list of the PREFIXs of all of the masters of this bus
//
// INTERCONNECT.OPTIONS
// = string of case-insensitive options
// OPT_STARVATION_TIMEOUT
// OPT_LOWPOWER
// OPT_DBLBUFFER
//
//
// INTERCONNECT.OPTVAL=
// = Options that require values
// - OPT_TIMEOUT
// - LGMAXBURST
//
// Creates tags:
//
// BLIST: A list of bus interconnect parameters, somewhat like:
// @$(SLAVE.BUS)_cyc,
// @$(SLAVE.BUS)_stb,
// (if !ROM&!WOM) @$(SLAVE.BUS)_we,
// (if AWID>0) @$(SLAVE.BUS)_addr[@$(SLAVE.AWID)-1:0],
// (if !ROM) @$(SLAVE.BUS)_data,
// (if !ROM) @$(SLAVE.BUS)_sel,
// @$(PREFIX)_stall,
// @$(PREFIX)_ack,
// (if !WOM) @$(PREFIX)_data,
// (and possibly) @$(PREFIX)_err
//
// ASCBLIST.PREFIX: [%io] prefix
// ASCBLIST.SUFFIX:
// ASCBLIST.CAPS:
// ASCBLIST.DATA:
// .@$(ASCBLIST.PREFIX)cyc@$(ASCBLIST.SUFFIX)(@$SLAVE.BUS)_cyc),
// .@$(ASCBLIST.PREFIX)stb@$(ASCBLIST.SUFFIX)(@$SLAVE.BUS)_stb),
// .@$(ASCBLIST.PREFIX)we@$(ASCBLIST.SUFFIX)(@$SLAVE.BUS)_we),
// .
//
// Creator: Dan Gisselquist, Ph.D.
// Gisselquist Technology, LLC
//
////////////////////////////////////////////////////////////////////////////////
// }}}
// Copyright (C) 2017-2024, Gisselquist Technology, LLC
// {{{
// This program is free software (firmware): you can redistribute it and/or
// modify it under the terms of the GNU General Public License as published
// by the Free Software Foundation, either version 3 of the License, or (at
// your option) any later version.
//
// This program is distributed in the hope that it will be useful, but WITHOUT
// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
// for more details.
//
// You should have received a copy of the GNU General Public License along
// with this program. (It's in the $(ROOT)/doc directory. Run make with no
// target there if the PDF file isn't present.) If not, see
// <http://www.gnu.org/licenses/> for a copy.
// }}}
// License: GPL, v3, as defined and found on www.gnu.org,
// {{{
// http://www.gnu.org/licenses/gpl.html
//
//
////////////////////////////////////////////////////////////////////////////////
//
// }}}
#include <stdio.h>
#include <stdlib.h>
#include <string>
#include <vector>
#include <algorithm>
#include <string.h>
#include <unistd.h>
#include <ctype.h>
#include "../parser.h"
#include "../mapdhash.h"
#include "../keys.h"
#include "../kveval.h"
#include "../legalnotice.h"
#include "../bldtestb.h"
#include "../bitlib.h"
#include "../plist.h"
#include "../bldregdefs.h"
#include "../ifdefs.h"
#include "../bldsim.h"
#include "../predicates.h"
#include "../businfo.h"
#include "../globals.h"
#include "../subbus.h"
#include "../msgs.h"
#include "../genbus.h"
#include "axil.h"
#define PREFIX
extern AXILBUSCLASS axilclass;
const unsigned AXI_MIN_ADDRESS_WIDTH = 12;
AXILBUS::AXILBUS(BUSINFO *bi) {
// {{{
m_info = bi;
m_slist = NULL;
m_dlist = NULL;
m_is_single = false;
m_is_double = false;
m_num_single = 0;
m_num_double = 0;
m_num_total = 0;
}
// }}}
void AXILBUS::allocate_subbus(void) {
// {{{
PLIST *pl = m_info->m_plist;
BUSINFO *sbi = NULL, *dbi = NULL;
if (NULL == pl || pl->size() == 0) {
gbl_msg.warning("Bus %s has no attached slaves\n",
(name()) ? name()->c_str() : "(No-name)");
}
gbl_msg.info("Generating AXI-Lite bus logic generator for %s\n",
(name()) ? name()->c_str() : "(No-name)");
countsio();
if (m_num_single == m_num_total) {
m_num_single = 0;
m_is_single = true;
} else if ((m_num_single <= 2)&&(m_num_double > 0)) {
// Merge single and double busses, making single
// slaves into double slaves
m_num_double += m_num_single;
m_num_single = 0;
}
if (!m_is_single && m_num_single + m_num_double == m_num_total) {
m_is_double = true;
m_num_double = 0;
}
assert(!m_is_single || !m_is_double);
assert(m_num_single < 50);
assert(m_num_double < 50);
assert(m_num_total >= m_num_single + m_num_double);
//
// Master of multiple classes
//
if (!m_is_single && m_num_single > 0) {
sbi = create_sio();
m_num_total++;
}
if (!m_is_double && m_num_double > 0) {
m_num_total++;
dbi = create_dio();
}
if (!m_is_single && !m_is_double && pl) {
//
// There exist peripherals that are neither singles nor doubles
//
for(unsigned pi = 0; pi< pl->size(); pi++) {
PERIPHP p = (*pl)[pi];
STRINGP ptyp;
ptyp = getstring(p->p_phash, KYSLAVE_TYPE);
if (m_slist && ptyp != NULL
&& ptyp->compare(KYSINGLE) == 0) {
m_info->m_plist->erase(pl->begin()+pi);
pi--;
m_slist->add(p);
} else if (m_dlist && ptyp != NULL
&& ((ptyp->compare(KYDOUBLE) == 0)
|| (ptyp->compare(KYSINGLE) == 0))) {
m_info->m_plist->erase(pl->begin()+pi);
pi--;
m_dlist->add(p);
} else {
// Leave this peripheral in m_info->m_plist
}
}
}
if (sbi)
setstring(sbi->m_hash, KY_TYPE, axilclass.name());
if (dbi)
setstring(dbi->m_hash, KY_TYPE, axilclass.name());
REHASH;
}
// }}}
int AXILBUS::address_width(void) {
// {{{
assert(m_info);
return m_info->m_address_width;
}
// }}}
bool AXILBUS::get_base_address(MAPDHASH *phash, unsigned &base) {
// {{{
if (!m_info || !m_info->m_plist) {
gbl_msg.error("BUS[%s] has no peripherals!\n",
(name()) ? name()->c_str() : "(No name)");
return false;
} else
return m_info->m_plist->get_base_address(phash, base);
}
// }}}
void AXILBUS::assign_addresses(void) {
// {{{
int address_width;
if (m_info->m_addresses_assigned)
return;
if ((NULL == m_slist)&&(NULL == m_dlist))
allocate_subbus();
if (!m_info)
return;
gbl_msg.info("AXIL: Assigning addresses for bus %s\n",
(name()) ? name()->c_str() : "(No name bus)");
if (!m_info->m_plist||(m_info->m_plist->size() < 1)) {
m_info->m_address_width = 0;
} else if (!m_info->m_addresses_assigned) {
int dw = m_info->data_width(),
nullsz;
if (m_slist)
m_slist->assign_addresses(dw, 0);
if (m_dlist)
m_dlist->assign_addresses(dw, 0);
if (!getvalue(*m_info->m_hash, KY_NULLSZ, nullsz))
nullsz = 0;
m_info->m_plist->assign_addresses(dw, nullsz, AXI_MIN_ADDRESS_WIDTH);
address_width = m_info->m_plist->get_address_width();
m_info->m_address_width = address_width;
if (m_info->m_hash) {
setvalue(*m_info->m_hash, KY_AWID, m_info->m_address_width);
REHASH;
}
} m_info->m_addresses_assigned = true;
}
// }}}
BUSINFO *AXILBUS::create_sio(void) {
// {{{
assert(m_info);
BUSINFO *sbi;
SUBBUS *subp;
STRINGP sioname;
MAPDHASH *bushash, *shash;
MAPT elm;
sioname = new STRING(STRING("" PREFIX) + (*name()) + "_sio");
bushash = new MAPDHASH();
shash = new MAPDHASH();
setstring(*shash, KYPREFIX, sioname);
setstring(*shash, KYSLAVE_TYPE, new STRING(KYDOUBLE));
setstring(*shash, KYSLAVE_PREFIX, sioname);
elm.m_typ = MAPT_MAP;
elm.u.m_m = bushash;
shash->insert(KEYVALUE(KYSLAVE_BUS, elm));
elm.u.m_m = m_info->m_hash;
shash->insert(KEYVALUE(KYMASTER_BUS, elm));
setstring(shash, KYMASTER_TYPE, KYARBITER);
sbi = new BUSINFO(sioname);
sbi->prefix(new STRING("_sio"));
setstring(bushash, KY_TYPE, new STRING("axil"));
sbi->m_data_width = m_info->m_data_width;
sbi->m_clock = m_info->m_clock;
sbi->addmaster(m_info->m_hash);
subp = new SUBBUS(shash, sioname, sbi);
subp->p_slave_bus = m_info;
// subp->p_master_bus = set by the SUBBUS to be sbi
m_info->m_plist->add(subp);
assert(subp->p_master_bus);
assert(subp->p_slave_bus == m_info);
assert(subp->p_master_bus == sbi);
// m_plist->integrity_check();
sbi->add();
m_slist = sbi->m_plist;
return sbi;
}
// }}}
BUSINFO *AXILBUS::create_dio(void) {
// {{{
assert(m_info);
BUSINFO *dbi;
SUBBUS *subp;
STRINGP dioname;
MAPDHASH *bushash, *shash;
MAPT elm;
dioname = new STRING(STRING("" PREFIX) + (*name()) + "_dio");
bushash = new MAPDHASH();
shash = new MAPDHASH();
setstring(*bushash, KY_NAME, dioname);
setstring(*shash, KYPREFIX, dioname);
setstring(*shash, KYSLAVE_TYPE, new STRING(KYOTHER));
setstring(*shash, KYSLAVE_PREFIX, dioname);
elm.m_typ = MAPT_MAP;
elm.u.m_m = m_info->m_hash;
shash->insert(KEYVALUE(KYSLAVE_BUS, elm));
elm.u.m_m = bushash;
shash->insert(KEYVALUE(KYMASTER_BUS, elm));
setstring(shash, KYMASTER_TYPE, KYARBITER);
dbi = new BUSINFO(dioname);
dbi->prefix(new STRING("_dio"));
setstring(bushash, KY_TYPE, new STRING("axil"));
assert(m_info->data_width() > 0);
setvalue(*bushash, KY_WIDTH, m_info->data_width());
dbi->m_data_width = m_info->m_data_width;
dbi->m_clock = m_info->m_clock;
dbi->addmaster(m_info->m_hash);
subp = new SUBBUS(shash, dioname, dbi);
subp->p_slave_bus = m_info;
m_info->m_plist->add(subp);
assert(subp->p_master_bus);
assert(subp->p_master_bus == dbi);
assert(subp->p_slave_bus == m_info);
// subp->p_master_bus = set by the slave to be dbi
dbi->add();
m_dlist = dbi->m_plist;
assert(isbusmaster(*shash));
assert(isarbiter(*shash));
return dbi;
}
// }}}
void AXILBUS::countsio(void) {
// {{{
PLIST *pl = m_info->m_plist;
STRINGP strp;
m_num_single = 0;
m_num_double = 0;
m_num_total = 0;
if (NULL == pl)
return;
for(unsigned pi=0; pi< pl->size(); pi++) {
strp = getstring((*pl)[pi]->p_phash, KYSLAVE_TYPE);
if (NULL != strp) {
if (0==strp->compare(KYSINGLE)) {
m_num_single++;
} else if (0==strp->compare(KYDOUBLE)) {
m_num_double++;
} m_num_total++;
} else
m_num_total++; // Default to OTHER if no type is given
}
}
// }}}
void AXILBUS::integrity_check(void) {
// {{{
// GENBUS::integrity_check();
if (m_info && m_info->m_data_width <= 0) {
gbl_msg.error("ERR: BUS width not defined for %s\n",
name()->c_str());
}
}
// }}}
void AXILBUS::writeout_defn_v(FILE *fp, const char *mstype,
const char *pname, const char* busp, const char *btyp){
// {{{
STRINGP n = name();
int aw = address_width();
fprintf(fp, "\t//\n\t// AXI-lite %s definitions for bus %s%s,\n"
"\t// component %s, with prefix %s\n\t// {{{\n",
mstype, n->c_str(), btyp, pname, busp);
fprintf(fp, "\t// Verilator lint_off UNUSED\n");
fprintf(fp, "\twire\t\t%s_awready, %s_wready,\n\t\t\t%s_arready;\n",
busp, busp, busp);
fprintf(fp, "\twire\t\t%s_bvalid, %s_rvalid;\n",
busp, busp);
fprintf(fp, "\twire\t[1:0]\t%s_bresp, %s_rresp;\n",
busp, busp);
fprintf(fp, "\twire\t[%d:0]\t%s_rdata;\n\n",
m_info->data_width()-1, busp);
fprintf(fp, "\twire\t\t%s_awvalid, %s_wvalid,\n\t\t\t%s_arvalid,\n"
"\t\t\t%s_bready, %s_rready;\n"
"\twire\t[%d:0]\t%s_araddr, %s_awaddr;\n"
"\twire\t[2:0]\t%s_arprot, %s_awprot;\n"
"\twire\t[%d:0]\t%s_wdata;\n"
"\twire\t[%d:0]\t%s_wstrb;\n\n",
busp, busp, busp,
busp, busp,
aw-1, busp, busp,
busp, busp,
m_info->data_width()-1, busp,
(m_info->data_width()/8)-1, busp);
fprintf(fp,
"\t// Verilator lint_on UNUSED\n"
"\t// }}}\n");
}
// }}}
void AXILBUS::writeout_bus_slave_defns_v(FILE *fp) {
// {{{
PLIST *p = m_info->m_plist;
STRINGP n = name();
if (m_slist) {
for(PLIST::iterator pp=m_slist->begin();
pp != m_slist->end(); pp++) {
writeout_defn_v(fp, "slave", (*pp)->p_name->c_str(),
(*pp)->bus_prefix()->c_str(), "(SIO)");
}
} else if (!m_is_single)
fprintf(fp, "\n\t// Bus %s has no SINGLE slaves\n\t//\n", n->c_str());
else
fprintf(fp, "\n\t// Bus %s is all SINGLE slaves\n\t//\n", n->c_str());
if (m_dlist) {
for(PLIST::iterator pp=m_dlist->begin();
pp != m_dlist->end(); pp++) {
writeout_defn_v(fp, "slave", (*pp)->p_name->c_str(),
(*pp)->bus_prefix()->c_str(), "(DIO)");
}
} else if (!m_is_double)
fprintf(fp, "\n\t// Bus %s has no DOUBLE slaves\n\t//\n", n->c_str());
else
fprintf(fp, "\n\t// Bus %s is all DOUBLE slaves\n\t//\n", n->c_str());
if (p) {
for(PLIST::iterator pp=p->begin(); pp != p->end(); pp++) {
writeout_defn_v(fp, "slave", (*pp)->p_name->c_str(),
(*pp)->bus_prefix()->c_str());
}
} else {
gbl_msg.error("%s has no slaves\n", n->c_str());
}
}
// }}}
void AXILBUS::writeout_bus_master_defns_v(FILE *fp) {
// {{{
MLIST *m = m_info->m_mlist;
STRINGP n = name();
if (m) {
for(MLIST::iterator pp=m->begin(); pp != m->end(); pp++) {
writeout_defn_v(fp, "master", (*pp)->name()->c_str(),
(*pp)->bus_prefix()->c_str());
}
} else {
gbl_msg.warning("Bus %s has no masters\n", n->c_str());
}
}
// }}}
void AXILBUS::write_addr_range(FILE *fp, const PERIPHP p, const int dalines) {
// {{{
unsigned w = address_width();
w = (w+3)/4;
if (p->p_naddr == 1)
fprintf(fp, " // 0x%0*lx", w, p->p_base);
else
fprintf(fp, " // 0x%0*lx - 0x%0*lx", w, p->p_base,
w, p->p_base + (p->p_naddr << (dalines))-1);
}
// }}}
void AXILBUS::writeout_no_slave_v(FILE *fp, STRINGP prefix) {
// {{{
}
// }}}
void AXILBUS::writeout_no_master_v(FILE *fp) {
if (!m_info || !name())
gbl_msg.error("(Unnamed bus) has no name!\n");
}
STRINGP AXILBUS::master_name(int k) {
// {{{
MLISTP ml = m_info->m_mlist;
return (*ml)[k]->name();
}
// }}}
//
// Connect this master to the crossbar. Specifically, we want to output
// a list of master connections to fill the given port.
//
void AXILBUS::xbarcon_master(FILE *fp, const char *tabs,
const char *pfx,const char *sig, bool comma) {
STRING lcase = STRING(sig);
for(unsigned k=0; k<lcase.size(); k++)
lcase[k] = tolower(lcase[k]);
fprintf(fp, "%s%s%s({\n", tabs, pfx, sig);
for(unsigned k=m_info->m_mlist->size()-1; k> 0; k--) {
BMASTER *m = (*m_info->m_mlist)[k];
STRINGP busp = m->bus_prefix();
fprintf(fp, "%s\t%s_%s,\n", tabs, busp->c_str(), lcase.c_str());
}
fprintf(fp, "%s\t%s_%s\n", tabs, (*m_info->m_mlist)[0]->bus_prefix()->c_str(),
lcase.c_str());
fprintf(fp, "%s})%s\n", tabs, comma ? ",":"");
}
//
// Output a list of connections to slave bus wires. Used in connecting the
// slaves to the various crossbar inputs.
//
void AXILBUS::xbarcon_slave(FILE *fp, PLIST *pl, const char *tabs,
const char *pfx,const char *sig, bool comma) {
STRING lcase = STRING(sig);
for(unsigned k=0; k<lcase.size(); k++)
lcase[k] = tolower(lcase[k]);
fprintf(fp, "%s%s%s({\n", tabs, pfx, sig);
for(unsigned k=pl->size()-1; k> 0; k--)
fprintf(fp, "%s\t%s_%s,\n", tabs, (*pl)[k]->bus_prefix()->c_str(), lcase.c_str());
fprintf(fp, "%s\t%s_%s\n", tabs, (*pl)[0]->bus_prefix()->c_str(), lcase.c_str());
fprintf(fp, "%s})%s\n", tabs, comma ? ",":"");
}
void AXILBUS::writeout_bus_logic_v(FILE *fp) {
STRINGP n = name(), rst;
CLOCKINFO *c = m_info->m_clock;
PLIST::iterator pp;
PLISTP pl;
// unsigned unused_lsbs;
MLISTP m_mlist = m_info->m_mlist;
if (NULL == m_info->m_plist)
return;
if (NULL == m_info->m_mlist) {
gbl_msg.warning("No masters assigned to bus %s\n",
n->c_str());
}
if (NULL == (rst = m_info->reset_wire())) {
gbl_msg.warning("Bus %s has no associated reset wire, using \'i_reset\'\n", n->c_str());
rst = new STRING("i_reset");
setstring(m_info->m_hash, KY_RESET, rst);
REHASH;
}
if (NULL == c || NULL == c->m_wire) {
gbl_msg.fatal("Bus %s has no associated clock\n", n->c_str());
}
// unused_lsbs = nextlg(m_info->data_width())-3;
if (m_info->m_plist->size() == 0) { // No slaves
// {{{
fprintf(fp, "\t//\n"
"\t// Bus %s has no slaves\n"
"\t//\n\n", n->c_str());
// Since this bus has no slaves, any attempt to access it
// needs to cause a bus error.
//
// Need to loop through all possible masters ...
for(unsigned m=0; m_info && m < m_info->m_mlist->size(); m++) {
STRINGP mstr = master_name(m);
const char *mp = mstr->c_str();
fprintf(fp,
"\t//\n"
"\t// The %s bus has no slaves assigned to it\n"
"\t//\n", mp);
fprintf(fp,
"\t// The no-slave peripheral\n"
"\t//\n"
"\taxilempty #(\n"
"\t\t// {{{\n"
"\t\t.C_AXI_ADDR_WIDTH(%d),\n"
"\t\t.C_AXI_DATA_WIDTH(%d)\n"
"\t\t// }}}\n",
address_width(),
m_info->data_width());
fprintf(fp,
"\t) %s_no_slavep (\n"
"\t\t// {{{\n"
"\t\t.S_AXI_ACLK(%s), .S_AXI_ARESETN(%s),\n"
"\t\t//\n",
mp, c->m_wire->c_str(), rst->c_str());
fprintf(fp,
"\t\t.S_AXI_AWVALID(%s_awvalid), .S_AXI_AWREADY(%s_awready),\n"
"\t\t.S_AXI_WVALID(%s_wvalid), .S_AXI_WREADY(%s_wready),\n"
"\t\t.S_AXI_BVALID(%s_bvalid), .S_AXI_BREADY(%s_bready),\n"
"\t\t.S_AXI_BRESP(%s_bresp),\n"
"\t\t//\n"
"\t\t.S_AXI_ARVALID(%s_arvalid), .S_AXI_ARREADY(%s_arready),\n"
"\t\t.S_AXI_RVALID(%s_rvalid), .S_AXI_RREADY(%s_rready),\n"
"\t\t.S_AXI_RDATA(%s_rdata), .S_AXI_RRESP(%s_rresp)\n"
"\t);\n\n",
mp, mp, mp, mp, mp, mp, mp,
mp, mp, mp, mp, mp, mp);
}
return;
// }}}
} else if (NULL == m_mlist || m_mlist->size() == 0) { // No masters
// {{{
for(unsigned p=0; p < m_info->m_plist->size(); p++) {
STRINGP pstr = (*m_info->m_plist)[p]->bus_prefix();
fprintf(fp,
"\t//\n"
"\t// The %s bus has no masters assigned to it\n"
"\t//\n"
"\tassign %s_awvalid = 1\'b0;\n"
"\tassign %s_awaddr = 0;\n"
"\tassign %s_awprot = 3\'h0;\n"
"\t//\n",
pstr->c_str(), pstr->c_str(), pstr->c_str(), pstr->c_str());
fprintf(fp,
"\tassign %s_wvalid = 1\'b0;\n"
"\tassign %s_wdata = 0;\n"
"\tassign %s_wstrb = 0;\n"
"\t//\n",
pstr->c_str(), pstr->c_str(),
pstr->c_str());
fprintf(fp,
"\tassign %s_bready = 1\'b0;\n",
pstr->c_str());
fprintf(fp,
"\t//\n"
"\tassign %s_arvalid = 1\'b0;\n"
"\tassign %s_araddr = 0;\n"
"\tassign %s_arprot = 3\'h0;\n"
"\t//\n",
pstr->c_str(), pstr->c_str(), pstr->c_str());
fprintf(fp,
"\tassign %s_rready = 1\'b1;\n",
pstr->c_str());
fprintf(fp,
"\t//\n"
"\t//\n"
"\twire %s_unused;\n"
"\tassign %s_unused = &{ 1\'b0, %s_awready, %s_wready,\n"
"\t\t%s_bvalid, %s_bresp,\n"
"\t\t%s_arready,\n"
"\t\t%s_rvalid, %s_rdata, %s_rresp\n"
"\t\t};\n",
pstr->c_str(), pstr->c_str(),
pstr->c_str(), pstr->c_str(),
pstr->c_str(), pstr->c_str(),
pstr->c_str(),
pstr->c_str(),pstr->c_str(),pstr->c_str()
);
}
return;
// }}}
} else if ((m_info->m_plist->size() == 1)&&(m_mlist && m_mlist->size() == 1)) {
// {{{
// Only one master connected to only one slave--skip all the
// extra connection logic.
//
// Can only simplify if there's only one peripheral and only
// one master
//
STRINGP slv = (*m_info->m_plist)[0]->bus_prefix();
STRINGP mstr = (*m_mlist)[0]->bus_prefix();
const char *sp = slv->c_str(),
*mp = mstr->c_str();
fprintf(fp,
"\t//\n"
"\t// Bus %s has only one master (%s) and one slave (%s)\n"
"\t// connected to it -- skipping the interconnect\n"
"\t//\n",
n->c_str(), master_name(0)->c_str(), sp);
fprintf(fp,
"\tassign %s_awvalid = %s_awvalid;\n"
"\tassign %s_awready = %s_awready;\n"
"\tassign %s_awaddr = %s_awaddr;\n"
"\tassign %s_awprot = %s_awprot;\n"
"\t//\n",
sp, mp, mp, sp,
sp, mp, sp, mp);
fprintf(fp,
"\tassign %s_wvalid = %s_wvalid;\n"
"\tassign %s_wready = %s_wready;\n"
"\tassign %s_wdata = %s_wdata;\n"
"\tassign %s_wstrb = %s_wstrb;\n"
"\t//\n",
sp, mp, mp, sp,
sp, mp, sp, mp);
fprintf(fp,
"\tassign %s_bvalid = %s_bvalid;\n"
"\tassign %s_bready = %s_bready;\n"
"\tassign %s_bresp = %s_bresp;\n",
mp, sp, sp, mp,
mp, sp);
fprintf(fp,
"\t//\n"
"\tassign %s_arvalid = %s_arvalid;\n"
"\tassign %s_arready = %s_arready;\n"
"\tassign %s_araddr = %s_araddr;\n"
"\tassign %s_arprot = %s_arprot;\n"
"\t//\n",
sp, mp, mp, sp,
sp, mp, sp, mp);
fprintf(fp,
"\tassign %s_rvalid = %s_rvalid;\n"
"\tassign %s_rready = %s_rready;\n"
"\tassign %s_rdata = %s_rdata;\n"
"\tassign %s_rresp = %s_rresp;\n\n",
mp, sp, sp, mp,
mp, sp, mp, sp);
return;
// }}}
}
// Start with the slist
if (m_is_single || m_slist) {
// {{{
assert(1 == m_info->m_mlist->size());
PLIST *slist = (m_is_single) ? m_info->m_plist : m_slist;
const char *np = n->c_str();
STRING s = STRING(*(*m_mlist)[0]->bus_prefix());
int aw = nextlg(slist->size())+nextlg(m_info->data_width())-3;
fprintf(fp,
"\t// Some extra wires to capture combined values--values\n"
"\t// that will be the same across all slaves of the\n"
"\t// class\n"
"\twire [2:0]\t%s_siow_awprot;\n"
"\twire [%d:0]\t%s_siow_wdata;\n"
"\twire [%d:0]\t%s_siow_wstrb;\n"
"\twire [2:0]\t%s_siow_arprot;\n\n",
n->c_str(), m_info->data_width()-1, n->c_str(),
m_info->data_width()/8-1, n->c_str(), n->c_str());
fprintf(fp,
"\taxilsingle #(\n"
"\t\t// {{{\n"
"\t\t// .C_AXI_ADDR_WIDTH(%d), // must be only one word address\n"
"\t\t.C_AXI_DATA_WIDTH(%d),\n"
"\t\t.NS(%ld)",
aw, m_info->data_width(),
slist->size());
xbar_option(fp, KY_OPT_LOWPOWER, ",\n\t\t.OPT_LOWPOWER(%)",
"1\'b1");
fprintf(fp,
"\n\t\t// }}}\n"
"\t) %s_axilsingle(\n", np);
fprintf(fp,
"\t\t// {{{\n"
"\t\t.S_AXI_ACLK(%s),\n"
"\t\t.S_AXI_ARESETN(%s),\n",
c->m_wire->c_str(), rst->c_str());
fprintf(fp, "\t\t// Connect our SIO slave wires to axilsingle\n"
"\t\t// {{{\n");
fprintf(fp,
"\t\t.S_AXI_AWVALID(%s_awvalid),\n"
"\t\t.S_AXI_AWREADY(%s_awready),\n"
"\t\t.S_AXI_AWADDR( %s_awaddr[%d:0]),\n"
"\t\t.S_AXI_AWPROT( %s_awprot),\n"
"\t\t//\n"
"\t\t.S_AXI_WVALID( %s_wvalid),\n"
"\t\t.S_AXI_WREADY( %s_wready),\n"
"\t\t.S_AXI_WDATA( %s_wdata),\n"
"\t\t.S_AXI_WSTRB( %s_wstrb),\n"
"\t\t//\n"
"\t\t.S_AXI_BVALID( %s_bvalid),\n"
"\t\t.S_AXI_BREADY( %s_bready),\n"
"\t\t.S_AXI_BRESP( %s_bresp),\n"
"\t\t// Read connections\n"
"\t\t.S_AXI_ARVALID(%s_arvalid),\n"
"\t\t.S_AXI_ARREADY(%s_arready),\n"
"\t\t.S_AXI_ARADDR( %s_araddr[%d:0]),\n"
"\t\t.S_AXI_ARPROT( %s_arprot),\n"
"\t\t//\n"
"\t\t.S_AXI_RVALID( %s_rvalid),\n"
"\t\t.S_AXI_RREADY( %s_rready),\n"
"\t\t.S_AXI_RDATA( %s_rdata),\n"
"\t\t.S_AXI_RRESP( %s_rresp),\n"
"\t\t// }}}\n"
"\t\t// Connections to varous AXI-lite (SINGLE) slaves\n"
"\t\t// {{{\n",
s.c_str(), s.c_str(), s.c_str(), aw-1, s.c_str(),
s.c_str(), s.c_str(), s.c_str(), s.c_str(),
s.c_str(), s.c_str(), s.c_str(),
s.c_str(), s.c_str(), s.c_str(), aw-1, s.c_str(),
s.c_str(), s.c_str(), s.c_str(), s.c_str());
xbarcon_slave(fp, slist, "\t\t",".M_AXI_","AWVALID");
fprintf(fp,
"\t\t.M_AXI_AWPROT(%s_siow_awprot),\n"
"\t\t.M_AXI_WDATA( %s_siow_wdata),\n"
"\t\t.M_AXI_WSTRB( %s_siow_wstrb),\n",
n->c_str(), n->c_str(), n->c_str());
fprintf(fp, "\t\t//\n"
"\t\t//\n");
xbarcon_slave(fp, slist, "\t\t",".M_AXI_","BRESP");
fprintf(fp, "\t\t// Read connections\n");
xbarcon_slave(fp, slist, "\t\t",".M_AXI_","ARVALID");
fprintf(fp,
"\t\t.M_AXI_ARPROT(%s_siow_arprot),\n"
"\t\t//\n", n->c_str());
xbarcon_slave(fp, slist, "\t\t",".M_AXI_","RDATA");
xbarcon_slave(fp, slist, "\t\t",".M_AXI_","RRESP", false);
fprintf(fp, "\t\t// }}}\n"
"\t\t// }}}\n"
"\t);\n\n");
fprintf(fp,"\t//\n\t// Now connecting the extra slaves wires "
"to the AXILSINGLE controller\n"
"\t// {{{\n");
for(int k=slist->size(); k>0; k--) {
PERIPHP p = (*slist)[k-1];
const char *pn = p->p_name->c_str(),
*ns = n->c_str();
fprintf(fp, "\t// %s\n", pn);
pn = p->bus_prefix()->c_str();
fprintf(fp, "\tassign %s_awaddr = 0;\n", pn);
fprintf(fp, "\tassign %s_awprot = %s_siow_awprot;\n", pn, ns);
fprintf(fp, "\tassign %s_wvalid = %s_awvalid;\n", pn, pn);
fprintf(fp, "\tassign %s_wdata = %s_siow_wdata;\n", pn, ns);
fprintf(fp, "\tassign %s_wstrb = %s_siow_wstrb;\n", pn, ns);
fprintf(fp, "\tassign %s_bready = 1\'b1;\n", pn);
fprintf(fp, "\tassign %s_araddr = 0;\n", pn);
fprintf(fp, "\tassign %s_arprot = %s_siow_arprot;\n", pn, ns);
fprintf(fp, "\tassign %s_rready = 1\'b1;\n", pn);
} fprintf(fp, "\t// }}}\n");
// }}}
return;
// }}}
} else if (!m_slist)
fprintf(fp, "\t//\n\t// No class SINGLE peripherals on the \"%s\" bus\n\t//\n\n", n->c_str());
// Then the dlist
if (m_is_double || m_dlist) {
// {{{
if (m_dlist)
pl = m_dlist;
else
pl = m_info->m_plist;
STRING s = STRING(*(*m_mlist)[0]->bus_prefix());
int aw = address_width();
if (!m_is_double)
s = (*n) + "_dio";
fprintf(fp,
"\t//\n"
"\t// %s Bus logic to handle %ld DOUBLE slaves\n"
"\t//\n"
"\t//\n", n->c_str(), pl->size());
fprintf(fp,
"\t// Some extra wires to capture combined values--values\n"
"\t// that will be the same across all slaves of the\n"
"\t// class\n"
"\twire [%d:0]\t%s_diow_awaddr;\n"
"\twire [2:0]\t%s_diow_awprot;\n"
"\twire [%d:0]\t%s_diow_wdata;\n"
"\twire [%d:0]\t%s_diow_wstrb;\n"
"\twire [%d:0]\t%s_diow_araddr;\n"
"\twire [2:0]\t%s_diow_arprot;\n\n",
address_width()-1, n->c_str(),
n->c_str(),
m_info->data_width()-1, n->c_str(),
m_info->data_width()/8-1, n->c_str(),
address_width()-1, n->c_str(),
n->c_str());
fprintf(fp,
"\taxildouble #(\n"
"\t\t// {{{\n"
"\t\t.C_AXI_ADDR_WIDTH(%d),\n"
"\t\t.C_AXI_DATA_WIDTH(%d),\n"
"\t\t.NS(%ld),\n",
address_width(), m_info->data_width(),
pl->size());
xbar_option(fp, KY_OPT_LOWPOWER, "\t\t.OPT_LOWPOWER(%),\n",
"1\'b1");
slave_addr(fp, pl); fprintf(fp, ",\n");
slave_mask(fp, pl); fprintf(fp, "\n");
fprintf(fp,
"\t\t// }}}\n"
"\t) %s_axildouble(\n",
n->c_str());
fprintf(fp,
"\t\t// {{{\n"
"\t\t.S_AXI_ACLK(%s),\n"
"\t\t.S_AXI_ARESETN(%s),\n",
c->m_wire->c_str(), rst->c_str());
fprintf(fp, "\t\t//\n");
fprintf(fp,
"\t\t// Slave port\n"
"\t\t// {{{\n"
"\t\t.S_AXI_AWVALID(%s_awvalid),\n"
"\t\t.S_AXI_AWREADY(%s_awready),\n"
"\t\t.S_AXI_AWADDR( %s_awaddr[%d:0]),\n"
"\t\t.S_AXI_AWPROT( %s_awprot),\n"
"\t\t//\n"
"\t\t.S_AXI_WVALID( %s_wvalid),\n"
"\t\t.S_AXI_WREADY( %s_wready),\n"
"\t\t.S_AXI_WDATA( %s_wdata),\n"
"\t\t.S_AXI_WSTRB( %s_wstrb),\n"
"\t\t//\n"
"\t\t.S_AXI_BVALID( %s_bvalid),\n"
"\t\t.S_AXI_BREADY( %s_bready),\n"
"\t\t.S_AXI_BRESP( %s_bresp),\n"
"\t\t//\n",
// AW
s.c_str(), s.c_str(), s.c_str(), aw-1, s.c_str(),
// W
s.c_str(), s.c_str(), s.c_str(), s.c_str(),
// B
s.c_str(), s.c_str(), s.c_str());
fprintf(fp,
"\t\t// Read connections\n"
"\t\t.S_AXI_ARVALID(%s_arvalid),\n"
"\t\t.S_AXI_ARREADY(%s_arready),\n"
"\t\t.S_AXI_ARADDR( %s_araddr[%d:0]),\n"
"\t\t.S_AXI_ARPROT( %s_arprot),\n"
"\t\t//\n"
"\t\t.S_AXI_RVALID( %s_rvalid),\n"
"\t\t.S_AXI_RREADY( %s_rready),\n"
"\t\t.S_AXI_RDATA( %s_rdata),\n"
"\t\t.S_AXI_RRESP( %s_rresp),\n"
"\t\t// }}}\n"
"\t\t// Connections to slaves\n"
"\t\t// {{{\n",