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Improve explanation of hierarchical selector polynomials in Plonk book #112
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After speaking with @LukePearson1 and @lopeetall, we think that Hierarchical selectors only make sense whenever the multiplying term has some subterm with no selector for example Kobi's MIMC gate:
But there's an advantage to not having a hierarchy like this, because then we can more readily take advantage of other gates. This could have also been written:
And the
since we could have composed this gate out of the ones above. The main idea is to find the smallest polynomials so that when added together we get the gates we want rather than constructing entire gates as their own polynomial. This clashes a bit with the per-gate separation challenges but I think those should be removed too and we can consider all the gates combined as one large gate with many possible terms. This is in line with the common mental representation of the PLONK circuit as a large matrix with one column per wire + selector and one witness constraint per row. |
If we don't use selector polynomials like |
What are the per-gate separation challenges and what does it mean to remove them? My suspicion is that there is potentially a trade-off between optimal performance and modularity. I.e. while it is unlikely that one would use a MiMC gates without arithemetic gates, for more complicated gates this is not necessarily the case. I might lift the difficulty of this issue to D-high, but maybe the Plonk book can describe more than one approach and help us in finding the correct design that we implement. |
The |
Yes for only |
I think |
Actually, I think this is a semantic issue with the fixed-based scalar mul gate, since it is just using This also affects the logic gate which uses the constant selector. |
We can consider that
q_arith
is hierarchically at a higher level.q_l, q_r, q_c, q_m, q_o, q_4
could be considered wire selectors in arithmetic gates, and auxiliary values in other custom gates.On the other hand
q_arith, q_logic, ...
are gate selectors which determine which gate is activated at any point in the circuit.The explanation should be expanded.
Originally posted by @davidnevadoc in #107 (comment)
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