diff --git a/kernel/constids.inc b/kernel/constids.inc
index 7db21debb0e..00db94af441 100644
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -222,6 +222,8 @@ X(_TECHMAP_REPLACE_)
 X(techmap_simplemap)
 X(_techmap_special_)
 X(techmap_wrap)
+X(_TECHMAP_PLACEHOLDER_)
+X(techmap_chtype)
 X(T_FALL_MAX)
 X(T_FALL_MIN)
 X(T_FALL_TYP)
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index db395315ce6..eda7c2f6c3b 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -336,6 +336,9 @@ struct TechmapWorker
 
 			if (c->type.begins_with("\\$"))
 				c->type = c->type.substr(1);
+			
+			if (c->type == ID::_TECHMAP_PLACEHOLDER_ && tpl_cell->has_attribute(ID::techmap_chtype))
+				c->type = RTLIL::escape_id(tpl_cell->get_string_attribute(ID::techmap_chtype));
 
 			vector<IdString> autopurge_ports;
 
@@ -1135,6 +1138,10 @@ struct TechmapPass : public Pass {
 		log("new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'\n");
 		log("prefix also substituted.\n");
 		log("\n");
+		log("A cell with the type _TECHMAP_PLACEHOLDER_ in the map file will have its type\n");
+		log("changed to the content of the techmap_chtype attribute. This allows for choosing\n");
+		log("the cell type dynamically.\n");
+		log("\n");
 		log("See 'help extract' for a pass that does the opposite thing.\n");
 		log("\n");
 		log("See 'help flatten' for a pass that does flatten the design (which is\n");