From b3e7390c0eb89544c0da6d9bc3b381f6ce450228 Mon Sep 17 00:00:00 2001 From: Stephen Tong <14918218+stong@users.noreply.github.com> Date: Sun, 21 Jan 2024 16:32:05 -0500 Subject: [PATCH 1/4] Fix typo in stat help --- passes/cmds/stat.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index f0021cf8769..d34373c1c0e 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -366,7 +366,7 @@ struct StatPass : public Pass { log(" use cell area information from the provided liberty file\n"); log("\n"); log(" -tech \n"); - log(" print area estemate for the specified technology. Currently supported\n"); + log(" print area estimate for the specified technology. Currently supported\n"); log(" values for : xilinx, cmos\n"); log("\n"); log(" -width\n"); From 3d9e44d18227c136cea031c667a5158fe31ac996 Mon Sep 17 00:00:00 2001 From: Catherine Date: Fri, 19 Jan 2024 14:23:08 +0000 Subject: [PATCH 2/4] hierarchy: keep display statements, like formal assertions. --- passes/hierarchy/hierarchy.cc | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index bf013750365..69cc6fb914d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -655,6 +655,17 @@ void hierarchy_clean(RTLIL::Design *design, RTLIL::Module *top, bool purge_lib) log("Removed %d unused modules.\n", del_counter); } +bool set_keep_print(std::map &cache, RTLIL::Module *mod) +{ + if (cache.count(mod) == 0) + for (auto c : mod->cells()) { + RTLIL::Module *m = mod->design->module(c->type); + if ((m != nullptr && set_keep_print(cache, m)) || c->type == ID($print)) + return cache[mod] = true; + } + return cache[mod]; +} + bool set_keep_assert(std::map &cache, RTLIL::Module *mod) { if (cache.count(mod) == 0) @@ -762,6 +773,11 @@ struct HierarchyPass : public Pass { log(" -nodefaults\n"); log(" do not resolve input port default values\n"); log("\n"); + log(" -nokeep_prints\n"); + log(" per default this pass sets the \"keep\" attribute on all modules\n"); + log(" that directly or indirectly display text on the terminal.\n"); + log(" This option disables this behavior.\n"); + log("\n"); log(" -nokeep_asserts\n"); log(" per default this pass sets the \"keep\" attribute on all modules\n"); log(" that directly or indirectly contain one or more formal properties.\n"); @@ -818,6 +834,7 @@ struct HierarchyPass : public Pass { bool keep_positionals = false; bool keep_portwidths = false; bool nodefaults = false; + bool nokeep_prints = false; bool nokeep_asserts = false; std::vector generate_cells; std::vector generate_ports; @@ -893,6 +910,10 @@ struct HierarchyPass : public Pass { nodefaults = true; continue; } + if (args[argidx] == "-nokeep_prints") { + nokeep_prints = true; + continue; + } if (args[argidx] == "-nokeep_asserts") { nokeep_asserts = true; continue; @@ -1091,6 +1112,15 @@ struct HierarchyPass : public Pass { } } + if (!nokeep_prints) { + std::map cache; + for (auto mod : design->modules()) + if (set_keep_print(cache, mod)) { + log("Module %s directly or indirectly displays text -> setting \"keep\" attribute.\n", log_id(mod)); + mod->set_bool_attribute(ID::keep); + } + } + if (!nokeep_asserts) { std::map cache; for (auto mod : design->modules()) From cfcd0b57299a9f2b13453e396c7a7b72d0aee16e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 22 Jan 2024 17:18:39 +0100 Subject: [PATCH 3/4] Checkout specific iverilog version (can be master as well) --- .github/workflows/test-linux.yml | 5 ++++- .github/workflows/test-macos.yml | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test-linux.yml b/.github/workflows/test-linux.yml index a16481726d3..103c060a2c0 100644 --- a/.github/workflows/test-linux.yml +++ b/.github/workflows/test-linux.yml @@ -85,13 +85,16 @@ jobs: shell: bash run: | git clone https://github.com/steveicarus/iverilog.git + cd iverilog + git checkout ${{ vars.IVERILOG_VERSION }} + echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV - name: Cache iverilog id: cache-iverilog uses: actions/cache@v3 with: path: .local/ - key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }} + key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }} - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' diff --git a/.github/workflows/test-macos.yml b/.github/workflows/test-macos.yml index 2b48b725237..62fbc59e82f 100644 --- a/.github/workflows/test-macos.yml +++ b/.github/workflows/test-macos.yml @@ -41,13 +41,16 @@ jobs: shell: bash run: | git clone https://github.com/steveicarus/iverilog.git + cd iverilog + git checkout ${{ vars.IVERILOG_VERSION }} + echo "IVERILOG_GIT=$(git rev-parse HEAD)" >> $GITHUB_ENV - name: Cache iverilog id: cache-iverilog uses: actions/cache@v3 with: path: .local/ - key: ${{ matrix.os.id }}-${{ hashFiles('iverilog/.git/refs/heads/master') }} + key: ${{ matrix.os.id }}-${{ env.IVERILOG_GIT }} - name: Build iverilog if: steps.cache-iverilog.outputs.cache-hit != 'true' From 2f9fcc2e501b5f0a449d315738c4a8d06cf38434 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Tue, 23 Jan 2024 00:16:43 +0000 Subject: [PATCH 4/4] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 88dfb43740c..83642584724 100644 --- a/Makefile +++ b/Makefile @@ -141,7 +141,7 @@ LDLIBS += -lrt endif endif -YOSYS_VER := 0.37+21 +YOSYS_VER := 0.37+27 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo