diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index d3946a620de..847c7085cfa 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -889,7 +889,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_module(it.first) && !it.second->get_blackbox_attribute())
+		if (selected_module(it.first))
 			result.push_back(it.second);
 	return result;
 }
@@ -899,7 +899,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_whole_module(it.first) && !it.second->get_blackbox_attribute())
+		if (selected_whole_module(it.first))
 			result.push_back(it.second);
 	return result;
 }
diff --git a/tests/select/cutpoint_blackboxes.ys b/tests/select/cutpoint_blackboxes.ys
new file mode 100644
index 00000000000..65116e72450
--- /dev/null
+++ b/tests/select/cutpoint_blackboxes.ys
@@ -0,0 +1,30 @@
+read_verilog <<EOT
+module passthrough(
+    input wire in,  // Input signal
+    output wire out // Output signal
+);
+
+    // Assign the output to be the same as the input
+    assign out = in;
+
+endmodule
+EOT
+cutpoint =*
+select -assert-count 1 =t:$anyseq
+
+design -reset
+
+read_verilog <<EOT
+(* blackbox *)
+module passthrough(
+    input wire in,  // Input signal
+    output wire out // Output signal
+);
+
+    // Assign the output to be the same as the input
+    assign out = in;
+
+endmodule
+EOT
+cutpoint =*
+select -assert-count 1 =t:$anyseq
\ No newline at end of file