diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 7f9e8117044..c4b1535567a 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1833,7 +1833,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictsecond.flags & RTLIL::CONST_FLAG_STRING) != 0) child->children[0] = AstNode::mkconst_str(it->second.decode_string()); else - child->children[0] = AstNode::mkconst_bits(it->second.bits(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); + child->children[0] = AstNode::mkconst_bits(it->second.bits().to_vec(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0); rewritten.insert(it->first); } @@ -1846,7 +1846,7 @@ std::string AstModule::derive_common(RTLIL::Design *design, const dictchildren.push_back(AstNode::mkconst_str(param.second.decode_string())); else - defparam->children.push_back(AstNode::mkconst_bits(param.second.bits(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); + defparam->children.push_back(AstNode::mkconst_bits(param.second.bits().to_vec(), (param.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0)); new_ast->children.push_back(defparam); } diff --git a/kernel/calc.cc b/kernel/calc.cc index 77d8d78c983..87814ac5927 100644 --- a/kernel/calc.cc +++ b/kernel/calc.cc @@ -641,7 +641,7 @@ RTLIL::Const RTLIL::const_pmux(const RTLIL::Const &arg1, const RTLIL::Const &arg RTLIL::Const RTLIL::const_bmux(const RTLIL::Const &arg1, const RTLIL::Const &arg2) { - std::vector t = arg1.bits(); + std::vector t = arg1.bits().to_vec(); for (int i = GetSize(arg2)-1; i >= 0; i--) { diff --git a/kernel/macc.h b/kernel/macc.h index be3ea14683f..e8322a2568e 100644 --- a/kernel/macc.h +++ b/kernel/macc.h @@ -104,7 +104,7 @@ struct Macc ports.clear(); bit_ports = cell->getPort(ID::B); - std::vector config_bits = cell->getParam(ID::CONFIG).bits(); + auto config_bits = cell->getParam(ID::CONFIG).bits(); int config_cursor = 0; int config_width = cell->getParam(ID::CONFIG_WIDTH).as_int(); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 37d1935511d..1068db7c06d 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -340,13 +340,6 @@ std::vector& RTLIL::Const::bits() return get_bits(); } -const std::vector& RTLIL::Const::bits() const -{ - bitvectorize(); - return get_bits(); -} - - std::vector RTLIL::Const::to_bits() const { if (auto bv = get_if_bits()) { diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 71524d3f2fd..84952ce26dc 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -707,7 +707,6 @@ struct RTLIL::Const bool operator ==(const RTLIL::Const &other) const; bool operator !=(const RTLIL::Const &other) const; - const std::vector& bits() const; std::vector& bits(); bool as_bool() const; int as_int(bool is_signed = false) const; @@ -762,7 +761,7 @@ struct RTLIL::Const inline RTLIL::State &operator[](int index) { return bits().at(index); } - inline const RTLIL::State &operator[](int index) const { + inline RTLIL::State operator[](int index) const { return bits().at(index); } inline bitvectype::iterator begin() { @@ -772,6 +771,100 @@ struct RTLIL::Const return bits().end(); } + class const_bit_view { + private: + const Const& parent; + public: + const_bit_view(const Const& c) : parent(c) {} + + class const_iterator { + private: + const Const& parent; + size_t idx; + + public: + using iterator_category = std::random_access_iterator_tag; + using value_type = bool; + using difference_type = std::ptrdiff_t; + using pointer = const bool*; + using reference = bool; + + const_iterator(const Const& c, size_t i) : parent(c), idx(i) {} + + State operator*() const { + if (auto bv = parent.get_if_bits()) + return (*bv)[idx]; + + bool bit = (parent.get_str()[idx / 8] & (1 << (7 - (idx % 8)))); + return bit ? State::S1 : State::S0; + } + const_iterator& operator++() { + ++idx; + return *this; + } + const_iterator& operator--() { + --idx; + return *this; + } + const_iterator& operator++(int) { + ++idx; + return *this; + } + const_iterator& operator--(int) { + --idx; + return *this; + } + const_iterator& operator+=(int i) { + idx += i; + return *this; + } + + const_iterator operator+(int add) { + return const_iterator(parent, idx + add); + } + int operator-(const const_iterator& other) { + return idx - other.idx; + } + + bool operator==(const const_iterator& other) const { + return idx == other.idx; + } + + bool operator!=(const const_iterator& other) const { + return !(*this == other); + } + }; + + const_iterator begin() const { + return const_iterator(parent, 0); + } + const_iterator end() const { + return const_iterator(parent, parent.size()); + } + State back() const { + return *const_iterator(parent, parent.size() - 1); + } + size_t size() const { + return (size_t)parent.size(); + } + State at(size_t i) const { + return *const_iterator(parent, i); + } + State operator[](size_t i) const { + return *const_iterator(parent, i); + } + std::vector to_vec() const { + std::vector v; + for (auto bit : *this) + v.push_back(bit); + return v; + } + }; + + const const_bit_view bits() const { + return const_bit_view(*this); + } + bool is_fully_zero() const; bool is_fully_ones() const; bool is_fully_def() const; @@ -780,7 +873,7 @@ struct RTLIL::Const bool is_onehot(int *pos = nullptr) const; inline RTLIL::Const extract(int offset, int len = 1, RTLIL::State padding = RTLIL::State::S0) const { - auto& bv = bits(); + const auto& bv = bits(); bitvectype ret_bv; ret_bv.reserve(len); for (int i = offset; i < offset + len; i++) diff --git a/kernel/satgen.cc b/kernel/satgen.cc index df0e9111c19..9786b679a6d 100644 --- a/kernel/satgen.cc +++ b/kernel/satgen.cc @@ -974,7 +974,7 @@ bool SatGen::importCell(RTLIL::Cell *cell, int timestep) int width = cell->getParam(ID::WIDTH).as_int(); int depth = cell->getParam(ID::DEPTH).as_int(); - vector table_raw = cell->getParam(ID::TABLE).bits(); + vector table_raw = cell->getParam(ID::TABLE).bits().to_vec(); while (GetSize(table_raw) < 2*width*depth) table_raw.push_back(State::S0);