From 66c629374c92babe7ffddfa50c826ef769b73e3a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Fri, 21 Jun 2024 11:56:36 +0200 Subject: [PATCH] fix proc, reduce warnings --- passes/cmds/glift.cc | 2 +- passes/proc/proc_mux.cc | 2 +- passes/tests/test_cell.cc | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index b7a6770d207..f857ad4bc68 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -343,7 +343,7 @@ struct GliftWorker { //recurse to GLIFT model the child module. However, we need to augment the ports list //with taint signals and connect the new ports to the corresponding taint signals. RTLIL::Module *cell_module_def = module->design->module(cell->type); - auto orig_ports = cell->connections(); + auto orig_ports = cell->connections().as_dict(); log("Adding cell %s\n", cell_module_def->name.c_str()); for (auto &&it : orig_ports) { RTLIL::SigSpec port = it.second; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 412f45ea7c7..0149b46494d 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -252,7 +252,7 @@ RTLIL::SigSpec gen_mux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const s return RTLIL::SigSpec(result_wire); } -void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) +void append_pmux(RTLIL::Module *mod, const RTLIL::SigSpec &signal, const std::vector &compare, RTLIL::SigSpec when_signal, RTLIL::Cell *&last_mux_cell, RTLIL::SwitchRule *sw, RTLIL::CaseRule *cs, bool ifxmode) { log_assert(last_mux_cell != NULL); log_assert(when_signal.size() == last_mux_cell->getPort(ID::A).size()); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 66f75e6032c..a09af9972d7 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -344,7 +344,7 @@ static void create_gold_module(RTLIL::Design *design, RTLIL::IdString cell_type, if (constmode) { - auto conn_list = cell->connections(); + auto conn_list = cell->connections().as_dict(); for (auto conn : conn_list) { RTLIL::SigSpec sig = conn.second;