From 120fedbf681e242441a8bf58d9b1ca70a2e5c725 Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Mon, 24 Jun 2024 17:55:44 +0200 Subject: [PATCH] experimental src decomposition, broken RTLIL dump --- frontends/ast/ast.cc | 2 +- frontends/verific/verific.cc | 3 ++- kernel/constids.inc | 1 + kernel/rtlil.h | 18 ++++++++++++++---- passes/sat/assertpmux.cc | 2 +- passes/sat/sat.cc | 2 +- passes/techmap/abc.cc | 2 +- passes/techmap/extract_counter.cc | 2 +- passes/techmap/simplemap.cc | 30 +++++++++++++++--------------- 9 files changed, 37 insertions(+), 25 deletions(-) diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 996f6715d05..43fe0a12afa 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1056,7 +1056,7 @@ std::string AstNode::loc_string() const void AST::set_src_attr(RTLIL::AttrObject *obj, const AstNode *ast) { - obj->attributes[ID::src] = ast->loc_string(); + obj->set_src_attribute(ast->loc_string()); } static bool param_has_no_default(const AstNode *param) { diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index f7c2cefd288..3e5539c71e9 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -409,7 +409,8 @@ void VerificImporter::import_attributes(dict &att Att *attr; if (obj->Linefile()) - attributes[ID::src] = stringf("%s:%d.%d-%d.%d", LineFile::GetFileName(obj->Linefile()), obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol()); + attributes[ID::src] = LineFile::GetFileName(obj->Linefile()); + attributes[ID::src_post] = stringf("%d.%d-%d.%d", obj->Linefile()->GetLeftLine(), obj->Linefile()->GetLeftCol(), obj->Linefile()->GetRightLine(), obj->Linefile()->GetRightCol()); FOREACH_ATTRIBUTE(obj, mi, attr) { if (attr->Key()[0] == ' ' || attr->Value() == nullptr) diff --git a/kernel/constids.inc b/kernel/constids.inc index 00db94af441..334d188752b 100644 --- a/kernel/constids.inc +++ b/kernel/constids.inc @@ -187,6 +187,7 @@ X(SET_POLARITY) X(SIZE) X(SRC) X(src) +X(src_post) X(SRC_DST_PEN) X(SRC_DST_POL) X(SRC_EN) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f9da2949508..af79a2c40a2 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -165,8 +165,8 @@ namespace RTLIL return it->second; } - log_assert(p[0] == '$' || p[0] == '\\'); - log_assert(p[1] != 0); + // log_assert(p[0] == '$' || p[0] == '\\'); + // log_assert(p[1] != 0); for (const char *c = p; *c; c++) if ((unsigned)*c <= (unsigned)' ') log_error("Found control character or space (0x%02x) in string '%s' which is not allowed in RTLIL identifiers\n", *c, p); @@ -721,6 +721,7 @@ struct RTLIL::Const struct RTLIL::AttrObject { dict attributes; + IdString raw_src; bool has_attribute(const RTLIL::IdString &id) const; @@ -739,10 +740,19 @@ struct RTLIL::AttrObject pool get_strpool_attribute(const RTLIL::IdString &id) const; void set_src_attribute(const std::string &src) { - set_string_attribute(ID::src, src); + if (std::count(src.begin(), src.end(), ':') == 1) { + auto idx = src.find(':'); + raw_src = src.substr(0, idx); + set_string_attribute(ID::src_post, src.substr(idx)); + } else { + raw_src = src; + } } std::string get_src_attribute() const { - return get_string_attribute(ID::src); + if (has_attribute(ID::src_post)) + return raw_src.str() + ":" + get_string_attribute(ID::src_post); + else + return raw_src.str(); } void set_hdlname_attribute(const vector &hierarchy); diff --git a/passes/sat/assertpmux.cc b/passes/sat/assertpmux.cc index abdcb224096..d214d3a62d3 100644 --- a/passes/sat/assertpmux.cc +++ b/passes/sat/assertpmux.cc @@ -175,7 +175,7 @@ struct AssertpmuxWorker Cell *assert_cell = module->addAssert(NEW_ID, assert_a, assert_en); if (pmux->attributes.count(ID::src) != 0) - assert_cell->attributes[ID::src] = pmux->attributes.at(ID::src); + assert_cell->set_src_attribute(pmux->get_src_attribute()); } }; diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 69f81e3df07..eadb313fc70 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -685,7 +685,7 @@ struct SatHelper std::string module_fname = "unknown"; auto apos = module->attributes.find(ID::src); if(apos != module->attributes.end()) - module_fname = module->attributes[ID::src].decode_string(); + module_fname = module->get_src_attribute(); fprintf(f, "$date\n"); fprintf(f, " %s\n", stime); diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index b33e1a17df4..c21ad867aa7 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -1178,7 +1178,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin RTLIL::Wire *orig_wire = nullptr; RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire)); if (orig_wire != nullptr && orig_wire->attributes.count(ID::src)) - wire->attributes[ID::src] = orig_wire->attributes[ID::src]; + wire->set_src_attribute(orig_wire->get_src_attribute()); if (markgroups) wire->attributes[ID::abcgroup] = map_autoidx; design->select(module, wire); } diff --git a/passes/techmap/extract_counter.cc b/passes/techmap/extract_counter.cc index b780f7df06c..f9354471837 100644 --- a/passes/techmap/extract_counter.cc +++ b/passes/techmap/extract_counter.cc @@ -532,7 +532,7 @@ void counter_worker( RTLIL::Wire* port_wire = port.as_wire(); bool force_extract = false; bool never_extract = false; - string count_reg_src = port_wire->attributes[ID::src].decode_string().c_str(); + string count_reg_src = port_wire->get_src_attribute(); if(port_wire->attributes.find(ID(COUNT_EXTRACT)) != port_wire->attributes.end()) { pool sa = port_wire->get_strpool_attribute(ID(COUNT_EXTRACT)); diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc index 7461460fed8..9976df68fae 100644 --- a/passes/techmap/simplemap.cc +++ b/passes/techmap/simplemap.cc @@ -36,7 +36,7 @@ void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::Y, sig_y[i]); } @@ -73,7 +73,7 @@ void simplemap_bitop(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::Y, sig_y[i]); @@ -124,7 +124,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_a[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -137,7 +137,7 @@ void simplemap_reduce(RTLIL::Module *module, RTLIL::Cell *cell) if (cell->type == ID($reduce_xnor)) { RTLIL::SigSpec sig_t = module->addWire(NEW_ID); RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_t); last_output_cell = gate; @@ -165,7 +165,7 @@ static void logic_reduce(RTLIL::Module *module, RTLIL::SigSpec &sig, RTLIL::Cell } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_OR_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig[i]); gate->setPort(ID::B, sig[i+1]); gate->setPort(ID::Y, sig_t[i/2]); @@ -194,7 +194,7 @@ void simplemap_lognot(RTLIL::Module *module, RTLIL::Cell *cell) } RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_NOT_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a); gate->setPort(ID::Y, sig_y); } @@ -223,7 +223,7 @@ void simplemap_logbin(RTLIL::Module *module, RTLIL::Cell *cell) log_assert(!gate_type.empty()); RTLIL::Cell *gate = module->addCell(NEW_ID, gate_type); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a); gate->setPort(ID::B, sig_b); gate->setPort(ID::Y, sig_y); @@ -239,19 +239,19 @@ void simplemap_eqne(RTLIL::Module *module, RTLIL::Cell *cell) RTLIL::SigSpec xor_out = module->addWire(NEW_ID, max(GetSize(sig_a), GetSize(sig_b))); RTLIL::Cell *xor_cell = module->addXor(NEW_ID, sig_a, sig_b, xor_out, is_signed); - xor_cell->attributes[ID::src] = cell->attributes[ID::src]; + xor_cell->set_src_attribute(cell->get_src_attribute()); simplemap_bitop(module, xor_cell); module->remove(xor_cell); RTLIL::SigSpec reduce_out = is_ne ? sig_y : module->addWire(NEW_ID); RTLIL::Cell *reduce_cell = module->addReduceOr(NEW_ID, xor_out, reduce_out); - reduce_cell->attributes[ID::src] = cell->attributes[ID::src]; + reduce_cell->set_src_attribute(cell->get_src_attribute()); simplemap_reduce(module, reduce_cell); module->remove(reduce_cell); if (!is_ne) { RTLIL::Cell *not_cell = module->addLogicNot(NEW_ID, reduce_out, sig_y); - not_cell->attributes[ID::src] = cell->attributes[ID::src]; + not_cell->set_src_attribute(cell->get_src_attribute()); simplemap_lognot(module, not_cell); module->remove(not_cell); } @@ -265,7 +265,7 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, cell->getPort(ID::S)); @@ -282,7 +282,7 @@ void simplemap_bwmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::B, sig_b[i]); gate->setPort(ID::S, sig_s[i]); @@ -298,7 +298,7 @@ void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(sig_y); i++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_TBUF_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, sig_a[i]); gate->setPort(ID::E, sig_e); gate->setPort(ID::Y, sig_y[i]); @@ -316,7 +316,7 @@ void simplemap_bmux(RTLIL::Module *module, RTLIL::Cell *cell) for (int i = 0; i < GetSize(new_data); i += width) { for (int k = 0; k < width; k++) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, data[i*2+k]); gate->setPort(ID::B, data[i*2+width+k]); gate->setPort(ID::S, sel[idx]); @@ -339,7 +339,7 @@ void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell) SigSpec new_lut_data = module->addWire(NEW_ID, GetSize(lut_data)/2); for (int i = 0; i < GetSize(lut_data); i += 2) { RTLIL::Cell *gate = module->addCell(NEW_ID, ID($_MUX_)); - gate->attributes[ID::src] = cell->attributes[ID::src]; + gate->set_src_attribute(cell->get_src_attribute()); gate->setPort(ID::A, lut_data[i]); gate->setPort(ID::B, lut_data[i+1]); gate->setPort(ID::S, lut_ctrl[idx]);