From 08a8e667d5bcbf924ae239f85a2cf43943fbd95d Mon Sep 17 00:00:00 2001 From: YosysHQ CI <105224853+yosyshq-ci@users.noreply.github.com> Date: Mon, 25 Mar 2024 15:03:30 +0000 Subject: [PATCH] Update --- source/cmd/write_jny.rst | 4 ++-- source/code_examples/extensions/test0.log | 4 ++-- source/code_examples/extensions/test1.log | 6 +++--- source/code_examples/extensions/test2.log | 6 +++--- source/getting_started/example_synth.rst | 4 ++-- source/temp/yosys-abc | 2 +- source/test_suites.rst | 4 ++-- .../more_scripting/interactive_investigation.rst | 4 ++-- source/using_yosys/more_scripting/model_checking.rst | 4 ++-- source/using_yosys/more_scripting/selections.rst | 2 +- source/using_yosys/synthesis/cell_libs.rst | 2 +- source/using_yosys/synthesis/extract.rst | 2 +- source/using_yosys/synthesis/memory.rst | 4 ++-- source/using_yosys/synthesis/proc.rst | 2 +- source/yosys_internals/extending_yosys/extensions.rst | 4 ++-- source/yosys_internals/techmap.rst | 2 +- 16 files changed, 28 insertions(+), 28 deletions(-) diff --git a/source/cmd/write_jny.rst b/source/cmd/write_jny.rst index d9a3033..f2d22e9 100644 --- a/source/cmd/write_jny.rst +++ b/source/cmd/write_jny.rst @@ -50,7 +50,7 @@ write_jny - generate design metadata :: The JSON schema for JNY output files is located in the "jny.schema.json" file - which is located at "https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json" + which is located at "https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json" .. raw:: latex @@ -75,5 +75,5 @@ write_jny - generate design metadata Don't include property information in the netlist output. The JSON schema for JNY output files is located in the "jny.schema.json" file - which is located at "https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json" + which is located at "https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json" diff --git a/source/code_examples/extensions/test0.log b/source/code_examples/extensions/test0.log index 487d97f..aa65c5d 100644 --- a/source/code_examples/extensions/test0.log +++ b/source/code_examples/extensions/test0.log @@ -12,6 +12,6 @@ Arguments to my_cmd: bar Modules in current design: -End of script. Logfile hash: 44d624038e, CPU: user 0.01s system 0.00s, MEM: 15.44 MB peak -Yosys 0.39+124 (git sha1 d73f71e81, ccache clang++ 10.0.0-4ubuntu1 -fPIC -Os) +End of script. Logfile hash: 44d624038e, CPU: user 0.00s system 0.00s, MEM: 15.47 MB peak +Yosys 0.39+124 (git sha1 6248d5901, ccache clang++ 10.0.0-4ubuntu1 -fPIC -Os) Time spent: 97% 1x verific (0 sec), 1% 1x read (0 sec), ... diff --git a/source/code_examples/extensions/test1.log b/source/code_examples/extensions/test1.log index ed233f8..af6539d 100644 --- a/source/code_examples/extensions/test1.log +++ b/source/code_examples/extensions/test1.log @@ -35,6 +35,6 @@ module \absval end end -End of script. Logfile hash: 15054a22aa, CPU: user 0.00s system 0.01s, MEM: 15.49 MB peak -Yosys 0.39+124 (git sha1 d73f71e81, ccache clang++ 10.0.0-4ubuntu1 -fPIC -Os) -Time spent: 57% 1x verific (0 sec), 36% 1x clean (0 sec), ... +End of script. Logfile hash: 15054a22aa, CPU: user 0.00s system 0.00s, MEM: 15.48 MB peak +Yosys 0.39+124 (git sha1 6248d5901, ccache clang++ 10.0.0-4ubuntu1 -fPIC -Os) +Time spent: 49% 1x verific (0 sec), 42% 1x clean (0 sec), ... diff --git a/source/code_examples/extensions/test2.log b/source/code_examples/extensions/test2.log index 97fbf2d..f10dc17 100644 --- a/source/code_examples/extensions/test2.log +++ b/source/code_examples/extensions/test2.log @@ -38,6 +38,6 @@ Log message #7. Log message #8. Log message #9. -End of script. Logfile hash: 42640299db, CPU: user 0.00s system 0.00s, MEM: 18.87 MB peak -Yosys 0.39+124 (git sha1 d73f71e81, ccache clang++ 10.0.0-4ubuntu1 -fPIC -Os) -Time spent: 56% 1x hierarchy (0 sec), 39% 1x verific (0 sec), ... +End of script. Logfile hash: 42640299db, CPU: user 0.00s system 0.00s, MEM: 18.83 MB peak +Yosys 0.39+124 (git sha1 6248d5901, ccache clang++ 10.0.0-4ubuntu1 -fPIC -Os) +Time spent: 61% 1x hierarchy (0 sec), 34% 1x verific (0 sec), ... diff --git a/source/getting_started/example_synth.rst b/source/getting_started/example_synth.rst index 799b4ec..916bef9 100644 --- a/source/getting_started/example_synth.rst +++ b/source/getting_started/example_synth.rst @@ -633,9 +633,9 @@ with the mapping to ``SB_RAM40_4K`` done by :cmd:ref:`techmap` using into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`. .. |techlibs/ice40/brams.txt| replace:: :file:`techlibs/ice40/brams.txt` -.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/master/techlibs/ice40/brams.txt +.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams.txt .. |techlibs/ice40/brams_map.v| replace:: :file:`techlibs/ice40/brams_map.v` -.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/master/techlibs/ice40/brams_map.v +.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams_map.v .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt diff --git a/source/temp/yosys-abc b/source/temp/yosys-abc index db527bf..7b8c963 100644 --- a/source/temp/yosys-abc +++ b/source/temp/yosys-abc @@ -15,4 +15,4 @@ usage: ./yosys-abc [-c cmd] [-q cmd] [-C cmd] [-Q cmd] [-f script] [-h] [-o file -x equivalent to '-t none -T none' -b running in bridge mode -UC Berkeley, ABC 1.01 (compiled Mar 19 2024 00:21:11) +UC Berkeley, ABC 1.01 (compiled Mar 25 2024 15:02:15) diff --git a/source/test_suites.rst b/source/test_suites.rst index 2edb0e6..7a6b749 100644 --- a/source/test_suites.rst +++ b/source/test_suites.rst @@ -16,8 +16,8 @@ Automatic testing .. _Yosys Git repo: https://github.com/YosysHQ/yosys -.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=master -.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=master +.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=main +.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=main For up to date information, including OS versions, refer to `the git actions page`_. diff --git a/source/using_yosys/more_scripting/interactive_investigation.rst b/source/using_yosys/more_scripting/interactive_investigation.rst index ed798d6..f56543b 100644 --- a/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/source/using_yosys/more_scripting/interactive_investigation.rst @@ -18,7 +18,7 @@ in the circuit diagrams generated by it. The code used is included in the Yosys code base under |code_examples/show|_. .. |code_examples/show| replace:: :file:`docs/source/code_examples/show` -.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/show +.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show A simple circuit ^^^^^^^^^^^^^^^^ @@ -337,7 +337,7 @@ The code used is included in the Yosys code base under |code_examples/scrambler|_. .. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler` -.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/scrambler +.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/scrambler Changing design hierarchy ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/source/using_yosys/more_scripting/model_checking.rst b/source/using_yosys/more_scripting/model_checking.rst index 0b97d38..92a9d85 100644 --- a/source/using_yosys/more_scripting/model_checking.rst +++ b/source/using_yosys/more_scripting/model_checking.rst @@ -29,7 +29,7 @@ Let's take a look at an example included in the Yosys code base under |code_examples/synth_flow|_: .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow` -.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow +.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow .. literalinclude:: /code_examples/synth_flow/techmap_01_map.v :language: verilog @@ -81,7 +81,7 @@ The code used in this section is included in the Yosys code base under |code_examples/axis|_. .. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis` -.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/axis +.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis The following AXI4 Stream Master has a bug. But the bug is not exposed if the slave keeps ``tready`` asserted all the time. (Something a test bench might do.) diff --git a/source/using_yosys/more_scripting/selections.rst b/source/using_yosys/more_scripting/selections.rst index d4def88..6aa3465 100644 --- a/source/using_yosys/more_scripting/selections.rst +++ b/source/using_yosys/more_scripting/selections.rst @@ -405,7 +405,7 @@ those cases selection variables must be used to capture more complex selections. Example code from |code_examples/selections|_: .. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections` -.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/selections +.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/selections .. literalinclude:: /code_examples/selections/select.v :language: verilog diff --git a/source/using_yosys/synthesis/cell_libs.rst b/source/using_yosys/synthesis/cell_libs.rst index a723845..476269a 100644 --- a/source/using_yosys/synthesis/cell_libs.rst +++ b/source/using_yosys/synthesis/cell_libs.rst @@ -21,7 +21,7 @@ detail in the :doc:`/getting_started/example_synth` document. To learn more about these commands, check out :ref:`interactive_show`. -.. _example project: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/intro +.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro A simple counter ~~~~~~~~~~~~~~~~ diff --git a/source/using_yosys/synthesis/extract.rst b/source/using_yosys/synthesis/extract.rst index 678efba..bbe1870 100644 --- a/source/using_yosys/synthesis/extract.rst +++ b/source/using_yosys/synthesis/extract.rst @@ -15,7 +15,7 @@ The extract pass Example code can be found in |code_examples/macc|_. .. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc` -.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/macc +.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/macc .. literalinclude:: /code_examples/macc/macc_simple_test.ys diff --git a/source/using_yosys/synthesis/memory.rst b/source/using_yosys/synthesis/memory.rst index 7df75fb..3dbafea 100644 --- a/source/using_yosys/synthesis/memory.rst +++ b/source/using_yosys/synthesis/memory.rst @@ -36,7 +36,7 @@ Example |code_examples/synth_flow|_. .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow` -.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow +.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow .. figure:: /_images/code_examples/synth_flow/memory_01.* :class: width-helper @@ -92,7 +92,7 @@ leftover memory cells unable to be converted are then picked up by For more on the lib format for :cmd:ref:`memory_libmap`, see `passes/memory/memlib.md -`_ +`_ Supported memory patterns ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/source/using_yosys/synthesis/proc.rst b/source/using_yosys/synthesis/proc.rst index 785be7a..b498343 100644 --- a/source/using_yosys/synthesis/proc.rst +++ b/source/using_yosys/synthesis/proc.rst @@ -31,7 +31,7 @@ Example |code_examples/synth_flow|_. .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow` -.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow +.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow .. literalinclude:: /code_examples/synth_flow/proc_01.v :language: verilog diff --git a/source/yosys_internals/extending_yosys/extensions.rst b/source/yosys_internals/extending_yosys/extensions.rst index 2c159e3..68e1740 100644 --- a/source/yosys_internals/extending_yosys/extensions.rst +++ b/source/yosys_internals/extending_yosys/extensions.rst @@ -24,7 +24,7 @@ Code examples from this section are included in the |code_examples/extensions|_ directory of the Yosys source code. .. |code_examples/extensions| replace:: :file:`docs/source/code_examples/extensions` -.. _code_examples/extensions: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/extensions +.. _code_examples/extensions: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/extensions Program components and data formats @@ -254,7 +254,7 @@ The following is the complete code of the "stubnets" example module. It is included in the Yosys source distribution under |code_examples/stubnets|_. .. |code_examples/stubnets| replace:: :file:`docs/source/code_examples/stubnets` -.. _code_examples/stubnets: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/stubnets +.. _code_examples/stubnets: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/stubnets .. literalinclude:: /code_examples/stubnets/stubnets.cc :language: c++ diff --git a/source/yosys_internals/techmap.rst b/source/yosys_internals/techmap.rst index ef2bbd8..ab161ed 100644 --- a/source/yosys_internals/techmap.rst +++ b/source/yosys_internals/techmap.rst @@ -16,7 +16,7 @@ Code examples used in this document are included in the Yosys code base under |code_examples/techmap|_. .. |code_examples/techmap| replace:: :file:`docs/source/code_examples/techmap` -.. _code_examples/techmap: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/techmap +.. _code_examples/techmap: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/techmap Mapping OR3X1