diff --git a/cv32e40x/cv32e40x.sby b/cv32e40x/cv32e40x.sby
index 16002ad..0dc75cc 100644
--- a/cv32e40x/cv32e40x.sby
+++ b/cv32e40x/cv32e40x.sby
@@ -53,9 +53,8 @@ verific -formal formal_setup.sv
 ## import from verific to yosys
 hierarchy -top uvmt_cv32e40x_tb
 ## cut mult
-### ex_stage name includes parameters:
-### e.g. cv32e40x_ex_stage(B_EXT=B_NONE_cv32e40x_pkg,M_EXT=M_cv32e40x_pkg)_0
-cutpoint cv32e40x_ex_stage*_0/mul.mult_i
+### should match cv32e40x_ex_stage(B_EXT=B_NONE_cv32e40x_pkg,M_EXT=M_cv32e40x_pkg)_0/mul.mult_i
+cutpoint t:$mul
 ## this flatten is needed to work around an issue with SV interfaces
 flatten
 ## prepare design
diff --git a/veer/veer_benchmark.sby b/veer/veer_benchmark.sby
index 73fab31..276ef9b 100644
--- a/veer/veer_benchmark.sby
+++ b/veer/veer_benchmark.sby
@@ -26,7 +26,7 @@ fail: expect fail
 
 [engines]
 bmc: smtbmc
-pdr: abc pdr
+pdr: abc --keep-going pdr
 cover: smtbmc
 
 [script]
@@ -37,6 +37,8 @@ verific -import -extnets veer_wrapper
 
 tee -o ../hierarchy.log hierarchy -top veer_wrapper
 
+cutpoint t:$mul
+
 prep -flatten
 
 # dma_axi requires axi to be setup