diff --git a/xai_components/base.py b/xai_components/base.py
index d3810ea2..c04f69a2 100644
--- a/xai_components/base.py
+++ b/xai_components/base.py
@@ -64,19 +64,22 @@ class BaseComponent:
     def __init__(self):
         all_ports = self.__annotations__
         for key, type_arg in all_ports.items():
-            port_class = type_arg.__origin__
-            port_type = type_arg.__args__[0]
-            if port_class in (InArg, InCompArg, OutArg):
-                if hasattr(port_type, 'initial_value'):
-                    port_value = port_type.initial_value()
+            if hasattr(type_arg, '__origin__'):
+                port_class = type_arg.__origin__
+                port_type = type_arg.__args__[0]
+                if port_class in (InArg, InCompArg, OutArg):
+                    if hasattr(port_type, 'initial_value'):
+                        port_value = port_type.initial_value()
+                    else:
+                        port_value = None
+
+                    if hasattr(port_type, 'getter'):
+                        port_getter = port_type.getter
+                    else:
+                        port_getter = lambda x: x
+                    setattr(self, key, port_class(port_value, port_getter))
                 else:
-                    port_value = None
-
-                if hasattr(port_type, 'getter'):
-                    port_getter = port_type.getter
-                else:
-                    port_getter = lambda x: x
-                setattr(self, key, port_class(port_value, port_getter))
+                    setattr(self, key, None)
             else:
                 setattr(self, key, None)
 
diff --git a/xai_components/xai_template/example_components.py b/xai_components/xai_template/example_components.py
index 23772aac..e7505dbc 100644
--- a/xai_components/xai_template/example_components.py
+++ b/xai_components/xai_template/example_components.py
@@ -1,4 +1,4 @@
-from xai_components.base import InArg, OutArg, InCompArg, Component, BaseComponent, xai_component, dynalist, dynatuple, dynadict
+from xai_components.base import InArg, OutArg, InCompArg, Component, BaseComponent, xai_component, dynalist, dynatuple
 
 from typing import Union
 @xai_component(color="red")
@@ -138,23 +138,19 @@ def do(self, ctx) -> BaseComponent:
 
 @xai_component
 class DynaPorts(Component):
-    """A component showcasing dynamic ports: `dynalist`, `dynatuple`, and `dynadict`.
+    """A component showcasing dynamic ports: `dynalist` and `dynatuple`.
     
     ##### inPorts:
     - dlist: A `dynalist` port. 
     - dtuple: A `dynatuple` port.
-    - ddict: A `dynadict` port. Accepts only Literal Dicts.
     
     """
     
     dlist: InArg[dynalist]
     dtuple: InArg[dynatuple]
-    ddict: InArg[dynadict]
     
     def execute(self, ctx) -> None:
         print("Printing dynalist value:")
         print(self.dlist.value)
         print("Printing dynatuple value:")
-        print(self.dtuple.value)
-        print("Printing dynadict value:")
-        print(self.ddict.value)
\ No newline at end of file
+        print(self.dtuple.value)
\ No newline at end of file