From 2bbcab68cee8d5b7075de03018560a69b9236b84 Mon Sep 17 00:00:00 2001 From: AndraBisca Date: Tue, 7 May 2024 08:08:12 -0600 Subject: [PATCH 01/49] Update alloc scheme flags --- include/aie/Dialect/AIE/Transforms/AIEPasses.td | 4 ++-- lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp | 12 +++++++++--- python/compiler/aiecc/cl_arguments.py | 9 ++++----- python/compiler/aiecc/main.py | 4 ++-- 4 files changed, 17 insertions(+), 12 deletions(-) diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index dd87f98a8c..2ec5c50389 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -27,8 +27,8 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let constructor = "xilinx::AIE::createAIEAssignBufferAddressesPass()"; let options = [ - Option<"clBasicAlloc", "basic-alloc", "bool", /*default=*/"false", - "Flag to enable the basic sequential allocation scheme (not bank-aware)."> + Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", + "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, bank-aware is tried followed by basic-sequential if it fails.">, ]; } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index b260e0d275..73d074ee0c 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -53,7 +53,7 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int address, return success(); } -LogicalResult basicAllocation(TileOp &tile) { +LogicalResult basicAllocation(TileOp tile) { auto device = tile->getParentOfType(); if (!device) return failure(); @@ -379,16 +379,22 @@ struct AIEAssignBufferAddressesPass }); // Select allocation scheme - if (clBasicAlloc) { + if (clBasicAlloc == "basic-sequential") { for (auto tile : device.getOps()) { if (auto res = basicAllocation(tile); res.failed()) return signalPassFailure(); } - } else { + } else if (clBasicAlloc == "bank-aware") { for (auto tile : device.getOps()) { if (auto res = simpleBankAwareAllocation(tile); res.failed()) return signalPassFailure(); } + } else { + for (auto tile : device.getOps()) { + if (auto res = simpleBankAwareAllocation(tile); res.failed()) + if (auto res2 = basicAllocation(tile); res2.failed()) + return signalPassFailure(); + } } } }; diff --git a/python/compiler/aiecc/cl_arguments.py b/python/compiler/aiecc/cl_arguments.py index cbfb5edcd3..3812e5ad89 100644 --- a/python/compiler/aiecc/cl_arguments.py +++ b/python/compiler/aiecc/cl_arguments.py @@ -139,11 +139,10 @@ def parse_args(args=None): help="Disable linking of AIE code", ) parser.add_argument( - "--basic-alloc-scheme", - dest="basic_alloc_scheme", - default=False, - action="store_true", - help="Use basic memory allocation scheme for AIE buffer address assignment", + "--alloc-scheme", + dest="alloc_scheme", + default=None, + help="Choose allocation scheme for AIE buffer address assignment; possibilities: basic-sequential, bank-aware. By default, bank-aware is tried followed by basic-sequential if it fails.", ) parser.add_argument( "--aie-generate-airbin", diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index ef0e62d0f8..9e364c03da 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -992,11 +992,11 @@ async def run_flow(self): ) file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") - if opts.basic_alloc_scheme: + if opts.alloc_scheme: r = do_run( [ "aie-opt", - "--aie-assign-buffer-addresses=basic-alloc", + "--aie-assign-buffer-addresses=alloc-scheme=basic-sequential", file_with_switchboxes, "-o", file_with_addresses, From 7f45c9f97e95fcd2e69888942a7ed53c849ba8e1 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Tue, 18 Jun 2024 17:39:55 -0600 Subject: [PATCH 02/49] Add alloc scheme to run command --- test/assign-buffer-addresses/basic_alloc_error.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_memtile_error.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir | 4 ++-- test/assign-buffer-addresses/basic_alloc_simple.mlir | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/test/assign-buffer-addresses/basic_alloc_error.mlir b/test/assign-buffer-addresses/basic_alloc_error.mlir index 9c2d85f4f3..a4585196a7 100644 --- a/test/assign-buffer-addresses/basic_alloc_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory // CHECK: (stack) : 0x0-0x3FF (1024 bytes) // CHECK: b : 0x400-0x83FF (32768 bytes) diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir index b179f8e842..ddf58c5e6b 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory module @test { diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index ef468d1e63..f01c7af150 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -8,8 +8,8 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s 2>&1 | FileCheck %s +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> module @test { aie.device(xcve2302) { diff --git a/test/assign-buffer-addresses/basic_alloc_simple.mlir b/test/assign-buffer-addresses/basic_alloc_simple.mlir index 51254e4f41..43b668814b 100644 --- a/test/assign-buffer-addresses/basic_alloc_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="basic-alloc" %s | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> From 4aeb18046d415c6b15707483f36e2ad47bbe1271 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Tue, 18 Jun 2024 18:12:39 -0600 Subject: [PATCH 03/49] Add alloc-scheme to run command --- test/assign-buffer-addresses/basic_alloc_error.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_memtile_error.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_simple.mlir | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/test/assign-buffer-addresses/basic_alloc_error.mlir b/test/assign-buffer-addresses/basic_alloc_error.mlir index a4585196a7..03bb66e4cc 100644 --- a/test/assign-buffer-addresses/basic_alloc_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory // CHECK: (stack) : 0x0-0x3FF (1024 bytes) // CHECK: b : 0x400-0x83FF (32768 bytes) diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir index ddf58c5e6b..0828732051 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory module @test { diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index f01c7af150..94b95d7eef 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s 2>&1 | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> module @test { diff --git a/test/assign-buffer-addresses/basic_alloc_simple.mlir b/test/assign-buffer-addresses/basic_alloc_simple.mlir index 43b668814b..73447208f6 100644 --- a/test/assign-buffer-addresses/basic_alloc_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> From d95e1c5da9bb47a23fc25483ca5a3863960f924f Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 26 Jun 2024 12:35:52 -0600 Subject: [PATCH 04/49] Add getNumBanks() to TargetModel --- include/aie-c/TargetModel.h | 3 +++ include/aie/Dialect/AIE/IR/AIETargetModel.h | 5 +++++ .../aie/Dialect/AIE/Transforms/AIEPasses.td | 2 +- lib/CAPI/TargetModel.cpp | 4 ++++ .../AIE/Transforms/AIEAssignBuffers.cpp | 20 +++++++++---------- 5 files changed, 22 insertions(+), 12 deletions(-) diff --git a/include/aie-c/TargetModel.h b/include/aie-c/TargetModel.h index 3248618795..60a91bedf4 100644 --- a/include/aie-c/TargetModel.h +++ b/include/aie-c/TargetModel.h @@ -137,6 +137,9 @@ aieTargetModelGetNumMemTileRows(AieTargetModel targetModel); MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel); +MLIR_CAPI_EXPORTED uint32_t +aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row); + /// Returns true if this is an NPU target model. MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel); diff --git a/include/aie/Dialect/AIE/IR/AIETargetModel.h b/include/aie/Dialect/AIE/IR/AIETargetModel.h index a6ec03d230..b57b08ac41 100644 --- a/include/aie/Dialect/AIE/IR/AIETargetModel.h +++ b/include/aie/Dialect/AIE/IR/AIETargetModel.h @@ -181,6 +181,8 @@ class AIETargetModel { virtual uint32_t getNumMemTileRows() const = 0; /// Return the size (in bytes) of a MemTile. virtual uint32_t getMemTileSize() const = 0; + /// Return the number of memory banks of a given tile. + virtual uint32_t getNumBanks(int col, int row) const = 0; /// Return the number of destinations of connections inside a switchbox. These /// are the targets of connect operations in the switchbox. virtual uint32_t getNumDestSwitchboxConnections(int col, int row, @@ -264,6 +266,7 @@ class AIE1TargetModel : public AIETargetModel { uint32_t getNumBDs(int col, int row) const override { return 16; } uint32_t getNumMemTileRows() const override { return 0; } uint32_t getMemTileSize() const override { return 0; } + uint32_t getNumBanks(int col, int row) const override { return 4; } uint32_t getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const override; @@ -334,6 +337,8 @@ class AIE2TargetModel : public AIETargetModel { uint32_t getMemTileSize() const override { return 0x00080000; } + uint32_t getNumBanks(int col, int row) const override { return isMemTile(col, row) ? 8 : 4; } + uint32_t getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const override; uint32_t getNumSourceSwitchboxConnections(int col, int row, diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index 2ec5c50389..7d1e611d05 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -28,7 +28,7 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let options = [ Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", - "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, bank-aware is tried followed by basic-sequential if it fails.">, + "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, basic-sequential is selected for the Tile's memory and bank-aware is selected for the rest.">, ]; } diff --git a/lib/CAPI/TargetModel.cpp b/lib/CAPI/TargetModel.cpp index b609c9abc2..7d046d82ae 100644 --- a/lib/CAPI/TargetModel.cpp +++ b/lib/CAPI/TargetModel.cpp @@ -149,6 +149,10 @@ uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel) { return unwrap(targetModel).getMemTileSize(); } +uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row) { + return unwrap(targetModel).getNumBanks(col, row); +} + bool aieTargetModelIsNPU(AieTargetModel targetModel) { return unwrap(targetModel).isNPU(); } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 39646d4a02..bd61fed697 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -113,14 +113,6 @@ typedef struct BankLimits { int64_t endAddr; } BankLimits; -// TODO: add to target model -int getNumBanks(TileOp tile) { - if (tile.isMemTile()) - return 1; - else - return 4; -} - // Function that given a number of banks and their size, computes // the start and end addresses for each bank and fills in the entry // in the bankLimits vector. @@ -294,7 +286,7 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { else maxDataMemorySize = targetModel.getLocalMemorySize(); - int numBanks = getNumBanks(tile); + int numBanks = targetModel.getNumBanks(tile.getCol(), tile.getRow()); int bankSize = maxDataMemorySize / numBanks; // Address range owned by the MemTile is 0x80000. @@ -391,9 +383,15 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { - if (auto res = simpleBankAwareAllocation(tile); res.failed()) - if (auto res2 = basicAllocation(tile); res2.failed()) + if (tile.isMemTile()) + if(auto res = simpleBankAwareAllocation(tile); res.failed()) + return signalPassFailure(); + if (!tile.isMemTile()) + if(auto res = basicAllocation(tile); res.failed()) return signalPassFailure(); + // if(auto res = simpleBankAwareAllocation(tile); res.failed()) + // if(auto res2 = basicAllocation(tile); res2.failed()) + // return signalPassFailure(); } } } From b0a128f55b9c692df53af181c8c3f7d5752093fa Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 26 Jun 2024 13:55:28 -0600 Subject: [PATCH 05/49] Updated --alloc-scheme in run command --- programming_examples/ml/bottleneck/Makefile | 2 +- programming_examples/ml/resnet/layers_conv2_x/Makefile | 2 +- programming_examples/vision/color_detect/Makefile | 2 +- programming_examples/vision/color_threshold/Makefile | 2 +- programming_examples/vision/edge_detect/Makefile | 2 +- programming_examples/vision/vision_passthrough/Makefile | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/programming_examples/ml/bottleneck/Makefile b/programming_examples/ml/bottleneck/Makefile index 5c696af170..e2682d00b3 100755 --- a/programming_examples/ml/bottleneck/Makefile +++ b/programming_examples/ml/bottleneck/Makefile @@ -33,7 +33,7 @@ build/conv2dk1_skip.o: conv2dk1_skip.cc build/final.xclbin: build/${mlirFileName}.mlir build/conv2dk1.o build/conv2dk3.o build/conv2dk1_skip.o cd build && aiecc.py -v --aie-generate-cdo --aie-generate-npu --no-compile-host \ - --basic-alloc-scheme \ + --alloc-scheme=basic-sequential \ --xclbin-name=${@F} --npu-insts-name=insts.txt ${ Date: Wed, 3 Jul 2024 13:10:46 -0600 Subject: [PATCH 06/49] Placement Errors --- .../AIE/Transforms/AIEAssignBuffers.cpp | 32 +++++++++++++------ 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index bd61fed697..5f226fbe14 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -29,7 +29,7 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int address, SmallVector buffers) { if (address > maxDataMemorySize) { InFlightDiagnostic error = - tile.emitOpError("allocated buffers exceeded available memory\n"); + tile.emitOpError("allocated buffers exceeded available memory: Sequential\n"); auto ¬e = error.attachNote() << "MemoryMap:\n"; auto printbuffer = [&](StringRef name, int address, int size) { note << "\t" << name << " \t" @@ -230,7 +230,7 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, } if (foundOverflow) { InFlightDiagnostic error = - tile.emitOpError("allocated buffers exceeded available memory\n"); + tile.emitOpError("allocated buffers exceeded available memory: Bank aware\n"); auto ¬e = error.attachNote() << "Error in bank(s) : "; for (auto bank : overflow_banks) note << bank << " "; @@ -383,15 +383,27 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { - if (tile.isMemTile()) - if(auto res = simpleBankAwareAllocation(tile); res.failed()) - return signalPassFailure(); - if (!tile.isMemTile()) - if(auto res = basicAllocation(tile); res.failed()) - return signalPassFailure(); - // if(auto res = simpleBankAwareAllocation(tile); res.failed()) - // if(auto res2 = basicAllocation(tile); res2.failed()) + // if (tile.isMemTile()) + // if(auto res = simpleBankAwareAllocation(tile); res.failed()) + // return signalPassFailure(); + // if (!tile.isMemTile()) + // if(auto res = basicAllocation(tile); res.failed()) // return signalPassFailure(); + if(auto res = simpleBankAwareAllocation(tile); res.failed()){ + // Collect all the buffers for this tile. + device.walk([&](BufferOp buffer) { + if(buffer.getTileOp() == tile){ + buffer->removeAttr("address"); + buffer->removeAttr("mem_bank"); + } + }); + if(auto res2 = basicAllocation(tile); res2.failed()) + return signalPassFailure(); + else + tile.emitOpError("Passed tile: sequential"); + } + else + tile.emitOpError("Passed tile: bank-aware"); } } } From 2c8d17da7f2e78148d995da8feadce0f9bdd36fb Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 3 Jul 2024 13:33:57 -0600 Subject: [PATCH 07/49] Failing check --- .../else_condition_check.mlir | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 test/assign-buffer-addresses/else_condition_check.mlir diff --git a/test/assign-buffer-addresses/else_condition_check.mlir b/test/assign-buffer-addresses/else_condition_check.mlir new file mode 100644 index 0000000000..a0565bdef5 --- /dev/null +++ b/test/assign-buffer-addresses/else_condition_check.mlir @@ -0,0 +1,31 @@ +//===- else_condition_check.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses : Fails +// +// malloc(): unaligned tcache chunk detected +// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. +// Stack dump: +// 0. Program arguments: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses else_condition_check.mlir +// malloc(): unaligned tcache chunk detected +// Aborted (core dumped) + + +// RUN: aie-opt --aie-objectFifo-stateful-transform else_condition_check.mlir | aie-opt --aie-assign-buffer-addresses : Passes + +module @test { + aie.device(xcvc1902) { + %tile12 = aie.tile(1, 2) + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes + %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes + %tile13 = aie.tile(1, 3) + aie.objectfifo @act_3_4(%tile12, {%tile13}, 2 : i32) : !aie.objectfifo> + } +} From a8677c4750e09e1e2af368be6934264d8c942c7f Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 3 Jul 2024 13:38:51 -0600 Subject: [PATCH 08/49] Add alloc-scheme to run command --- test/assign-buffer-addresses/bank_aware_alloc_error.mlir | 2 +- .../assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir | 2 +- .../bank_aware_alloc_memtile_simple.mlir | 2 +- test/assign-buffer-addresses/bank_aware_alloc_simple.mlir | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index 77b7996d76..a048e6db18 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory // CHECK: Error in bank(s) : 3 // CHECK: MemoryMap: diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index 7c639528d4..14d621e6bc 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory // CHECK: Error in bank(s) : 0 // CHECK: MemoryMap: diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir index aee7b03b91..f41d28547c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> module @test { diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index 84812a14c8..e479fb1fd2 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses %s | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> From cecdf7669be0401479a30b02cc917f3912a326fc Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 3 Jul 2024 14:42:01 -0600 Subject: [PATCH 09/49] Failed check --- test/assign-buffer-addresses/else_condition_check.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/assign-buffer-addresses/else_condition_check.mlir b/test/assign-buffer-addresses/else_condition_check.mlir index a0565bdef5..395a054efd 100644 --- a/test/assign-buffer-addresses/else_condition_check.mlir +++ b/test/assign-buffer-addresses/else_condition_check.mlir @@ -26,6 +26,6 @@ module @test { %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes %tile13 = aie.tile(1, 3) - aie.objectfifo @act_3_4(%tile12, {%tile13}, 2 : i32) : !aie.objectfifo> + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> } } From 613b84557df40930cc4ee5e2faaacdfafd837beb Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Mon, 15 Jul 2024 12:03:49 -0600 Subject: [PATCH 10/49] Fallback routine for bank-aware allocation failure --- .../AIE/Transforms/AIEAssignBuffers.cpp | 52 ++++++++++--------- programming_examples/ml/bottleneck/Makefile | 1 - .../ml/resnet/layers_conv2_x/Makefile | 2 +- 3 files changed, 28 insertions(+), 27 deletions(-) diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 5f226fbe14..61c35b58c6 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -197,23 +197,35 @@ bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, // of the next bank to search (which should be given to subsequent // calls of this function to ensure a round-robin allocation scheme // over the available banks). -int setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, +bool setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, std::vector &nextAddrInBanks, std::vector &bankLimits) { int bankIndex = startBankIndex; + bool allocated = false; for (int i = 0; i < numBanks; i++) { int64_t startAddr = nextAddrInBanks[bankIndex]; int64_t endAddr = startAddr + buffer.getAllocationSize(); - if (endAddr <= bankLimits[bankIndex].endAddr || i == numBanks - 1) { + //if (endAddr <= bankLimits[bankIndex].endAddr || i == numBanks - 1) { //Trying to fit if it is on the last bank + if (endAddr <= bankLimits[bankIndex].endAddr){ + if (endAddr > bankLimits[bankIndex].endAddr){ //That trying to fit is the problem which created the overflow + buffer->emitWarning("Potential overflow in bank"); + } buffer.setMemBank(bankIndex); setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); + allocated = true; bankIndex++; break; } + // Move to the next bank bankIndex++; + bankIndex %= numBanks; + } + // If allocation was not successful, handle the error + if(!allocated){ + buffer.emitError("Failed to allocated buffer: insufficient memory in all banks"); + return false; } - bankIndex %= numBanks; - return bankIndex; + return true; } LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, @@ -334,8 +346,16 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { // Set addresses for remaining buffers. int bankIndex = 0; for (auto buffer : buffersToAlloc) - bankIndex = setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, - bankLimits); + if(!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, + bankLimits)){ + device.walk([&](BufferOp buffer) { + if(buffer.getTileOp() == tile){ + buffer->removeAttr("address"); + buffer->removeAttr("mem_bank"); + } + }); + return basicAllocation(tile); + } // Sort by smallest address before printing memory map. std::sort(allBuffers.begin(), allBuffers.end(), [](BufferOp a, BufferOp b) { @@ -383,27 +403,9 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { - // if (tile.isMemTile()) - // if(auto res = simpleBankAwareAllocation(tile); res.failed()) - // return signalPassFailure(); - // if (!tile.isMemTile()) - // if(auto res = basicAllocation(tile); res.failed()) - // return signalPassFailure(); if(auto res = simpleBankAwareAllocation(tile); res.failed()){ - // Collect all the buffers for this tile. - device.walk([&](BufferOp buffer) { - if(buffer.getTileOp() == tile){ - buffer->removeAttr("address"); - buffer->removeAttr("mem_bank"); - } - }); - if(auto res2 = basicAllocation(tile); res2.failed()) - return signalPassFailure(); - else - tile.emitOpError("Passed tile: sequential"); + return signalPassFailure(); } - else - tile.emitOpError("Passed tile: bank-aware"); } } } diff --git a/programming_examples/ml/bottleneck/Makefile b/programming_examples/ml/bottleneck/Makefile index e2682d00b3..b6b8caa8cc 100755 --- a/programming_examples/ml/bottleneck/Makefile +++ b/programming_examples/ml/bottleneck/Makefile @@ -33,7 +33,6 @@ build/conv2dk1_skip.o: conv2dk1_skip.cc build/final.xclbin: build/${mlirFileName}.mlir build/conv2dk1.o build/conv2dk3.o build/conv2dk1_skip.o cd build && aiecc.py -v --aie-generate-cdo --aie-generate-npu --no-compile-host \ - --alloc-scheme=basic-sequential \ --xclbin-name=${@F} --npu-insts-name=insts.txt ${ Date: Wed, 17 Jul 2024 11:04:40 -0600 Subject: [PATCH 11/49] Fall back routine --- .../AIE/Transforms/AIEAssignBuffers.cpp | 11 +- .../fallback_routine.mlir | 140 ++++++++++++++++++ 2 files changed, 147 insertions(+), 4 deletions(-) create mode 100644 test/assign-buffer-addresses/fallback_routine.mlir diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 61c35b58c6..0cffd40ac1 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -207,9 +207,9 @@ bool setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, int64_t endAddr = startAddr + buffer.getAllocationSize(); //if (endAddr <= bankLimits[bankIndex].endAddr || i == numBanks - 1) { //Trying to fit if it is on the last bank if (endAddr <= bankLimits[bankIndex].endAddr){ - if (endAddr > bankLimits[bankIndex].endAddr){ //That trying to fit is the problem which created the overflow - buffer->emitWarning("Potential overflow in bank"); - } + // if (endAddr > bankLimits[bankIndex].endAddr){ //That trying to fit is the problem which created the overflow + // buffer->emitWarning("Potential overflow in bank"); + // } buffer.setMemBank(bankIndex); setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); allocated = true; @@ -219,10 +219,12 @@ bool setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, // Move to the next bank bankIndex++; bankIndex %= numBanks; + } // If allocation was not successful, handle the error if(!allocated){ buffer.emitError("Failed to allocated buffer: insufficient memory in all banks"); + //Print the memory map and the buffer that caused the error return false; } return true; @@ -349,12 +351,13 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { if(!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, bankLimits)){ device.walk([&](BufferOp buffer) { + // Handle only the buffersToAlloc if(buffer.getTileOp() == tile){ buffer->removeAttr("address"); buffer->removeAttr("mem_bank"); } }); - return basicAllocation(tile); + return failure();//basicAllocation(tile); } // Sort by smallest address before printing memory map. diff --git a/test/assign-buffer-addresses/fallback_routine.mlir b/test/assign-buffer-addresses/fallback_routine.mlir new file mode 100644 index 0000000000..69611e72ad --- /dev/null +++ b/test/assign-buffer-addresses/fallback_routine.mlir @@ -0,0 +1,140 @@ +//===- else_condition_check.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses : Fails +// +// malloc(): unaligned tcache chunk detected +// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. +// Stack dump: +// 0. Program arguments: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses else_condition_check.mlir +// malloc(): unaligned tcache chunk detected +// Aborted (core dumped) + + +// RUN: aie-opt --aie-objectFifo-stateful-transform else_condition_check.mlir | aie-opt --aie-assign-buffer-addresses : Passes + +// After merging the main with alloc-flags branch and using all the Passes, rather than just the 2. +// free(): invalid next size (fast) +// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. +// Stack dump: +// 0. Program arguments: aie-opt --aie-canonicalize-device --aie-assign-lock-ids --aie-register-objectFifos --aie-objectFifo-stateful-transform --aie-assign-bd-ids --aie-assign-buffer-addresses else_condition_check.mlir +// #0 0x000060e11514cc30 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) Signals.cpp:0:0 +// #1 0x000060e11514a56e SignalHandler(int) Signals.cpp:0:0 +// #2 0x00007d0a82a42520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520) +// #3 0x00007d0a82a969fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 +// #4 0x00007d0a82a969fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10 +// #5 0x00007d0a82a969fc pthread_kill ./nptl/pthread_kill.c:89:10 +// #6 0x00007d0a82a42476 gsignal ./signal/../sysdeps/posix/raise.c:27:6 +// #7 0x00007d0a82a287f3 abort ./stdlib/abort.c:81:7 +// #8 0x00007d0a82a89676 __libc_message ./libio/../sysdeps/posix/libc_fatal.c:155:5 +// #9 0x00007d0a82aa0cfc ./malloc/malloc.c:5668:3 +// #10 0x00007d0a82aa2a9d _int_free ./malloc/malloc.c:4522:4 +// #11 0x00007d0a82aa5453 __libc_free ./malloc/malloc.c:3394:3 +// #12 0x000060e114ef3f2e mlir::detail::OpToOpPassAdaptor::~OpToOpPassAdaptor() Pass.cpp:0:0 +// #13 0x000060e114ef5e8b mlir::PassManager::~PassManager() Pass.cpp:0:0 +// #14 0x000060e114a78453 performActions(llvm::raw_ostream&, std::shared_ptr const&, mlir::MLIRContext*, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 +// #15 0x000060e114a79683 processBuffer(llvm::raw_ostream&, std::unique_ptr>, mlir::MlirOptMainConfig const&, mlir::DialectRegistry&, llvm::ThreadPoolInterface*) MlirOptMain.cpp:0:0 +// #16 0x000060e114a797bd mlir::LogicalResult llvm::function_ref>, llvm::raw_ostream&)>::callback_fn>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&)::'lambda'(std::unique_ptr>, llvm::raw_ostream&)>(long, std::unique_ptr>, llvm::raw_ostream&) MlirOptMain.cpp:0:0 +// #17 0x000060e1150db529 mlir::splitAndProcessBuffer(std::unique_ptr>, llvm::function_ref>, llvm::raw_ostream&)>, llvm::raw_ostream&, llvm::StringRef, llvm::StringRef) ToolUtilities.cpp:0:0 +// #18 0x000060e114a72677 mlir::MlirOptMain(llvm::raw_ostream&, std::unique_ptr>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 +// #19 0x000060e114a7990c mlir::MlirOptMain(int, char**, llvm::StringRef, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 +// #20 0x000060e114a79e17 mlir::MlirOptMain(int, char**, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 +// #21 0x000060e112a3a526 main aie-opt.cpp:0:0 +// #22 0x00007d0a82a29d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16 +// #23 0x00007d0a82a29e40 call_init ./csu/../csu/libc-start.c:128:20 +// #24 0x00007d0a82a29e40 __libc_start_main ./csu/../csu/libc-start.c:379:5 +// #25 0x000060e112a298e5 _start (/scratch/pvasired/mlir-aie/install/bin/aie-opt+0xbd18e5) +// Aborted (core dumped) + +// Jeff's Output: +// #11 0x000055b3a1a27224 std::vector>::operator[](unsigned long) /usr/bin/../lib/gcc/x86_64-linux-gnu/13/../../../../include/c++/13/bits/stl_vector.h:1125:2 +// #12 0x000055b3a1a22ba0 setBufferAddress(xilinx::AIE::BufferOp, int, int, std::vector>&, std::vector>&) +// /work/acdc/aie/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp:205:25 + + +// Justifies that error occurs only from bank-aware allocation fail +// else_condition_check.mlir:63:13: error: 'aie.tile' op allocated buffers exceeded available memory: Bank aware +// (no stack allocated) + +// malloc(): unaligned tcache chunk detected +// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. +// Stack dump: +// 0. Program arguments: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses=alloc-scheme=bank-aware else_condition_check.mlir +// malloc(): unaligned tcache chunk detected +// Aborted (core dumped) + +// module @test { +// aie.device(xcvc1902) { +// %tile12 = aie.tile(1, 2) +// %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes +// %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes +// %tile13 = aie.tile(1, 3) +// aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> +// } +// } + + +// If objectFifo's source and destination is the same tile +// corrupted size vs. prev_size +// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. +// Stack dump: +// 0. Program arguments: aie-opt --aie-canonicalize-device --aie-assign-lock-ids --aie-register-objectFifos --aie-objectFifo-stateful-transform --aie-assign-bd-ids --aie-assign-buffer-addresses else_condition_check.mlir +// #0 0x0000576916c1fd00 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) Signals.cpp:0:0 +// #1 0x0000576916c1d63e SignalHandler(int) Signals.cpp:0:0 +// #2 0x0000708a2bc42520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520) +// #3 0x0000708a2bc969fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 +// #4 0x0000708a2bc969fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10 +// #5 0x0000708a2bc969fc pthread_kill ./nptl/pthread_kill.c:89:10 +// #6 0x0000708a2bc42476 gsignal ./signal/../sysdeps/posix/raise.c:27:6 +// #7 0x0000708a2bc287f3 abort ./stdlib/abort.c:81:7 +// #8 0x0000708a2bc89676 __libc_message ./libio/../sysdeps/posix/libc_fatal.c:155:5 +// #9 0x0000708a2bca0cfc ./malloc/malloc.c:5668:3 +// #10 0x0000708a2bca17e2 unlink_chunk ./malloc/malloc.c:1643:2 +// #11 0x0000708a2bca1969 malloc_consolidate ./malloc/malloc.c:4780:6 +// #12 0x0000708a2bca3bdb _int_malloc ./malloc/malloc.c:3965:9 +// #13 0x0000708a2bca5262 __libc_malloc ./malloc/malloc.c:3322:7 +// #14 0x0000708a2c0b751c operator new(unsigned long) (/lib/x86_64-linux-gnu/libstdc++.so.6+0xb751c) +// #15 0x0000576916c00ef4 llvm::raw_ostream::SetBuffered() raw_ostream.cpp:0:0 +// #16 0x0000576916c01bad llvm::raw_ostream::write(char const*, unsigned long) raw_ostream.cpp:0:0 +// #17 0x0000576916b18351 void llvm::detail::UniqueFunctionBase::CallImpl::getPrintAssemblyFn()::'lambda'(mlir::Operation*, mlir::OpAsmPrinter&, llvm::StringRef) const>(void*, mlir::Operation*, mlir::OpAsmPrinter&, llvm::StringRef) BuiltinDialect.cpp:0:0 +// #18 0x0000576916b10314 mlir::RegisteredOperationName::Model::printAssembly(mlir::Operation*, mlir::OpAsmPrinter&, llvm::StringRef) BuiltinDialect.cpp:0:0 +// #19 0x0000576916ad712e mlir::Operation::print(llvm::raw_ostream&, mlir::AsmState&) AsmPrinter.cpp:0:0 +// #20 0x000057691655162e performActions(llvm::raw_ostream&, std::shared_ptr const&, mlir::MLIRContext*, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 +// #21 0x0000576916551bd3 processBuffer(llvm::raw_ostream&, std::unique_ptr>, mlir::MlirOptMainConfig const&, mlir::DialectRegistry&, llvm::ThreadPoolInterface*) MlirOptMain.cpp:0:0 +// #22 0x0000576916551d0d mlir::LogicalResult llvm::function_ref>, llvm::raw_ostream&)>::callback_fn>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&)::'lambda'(std::unique_ptr>, llvm::raw_ostream&)>(long, std::unique_ptr>, llvm::raw_ostream&) MlirOptMain.cpp:0:0 +// #23 0x0000576916bacc49 mlir::splitAndProcessBuffer(std::unique_ptr>, llvm::function_ref>, llvm::raw_ostream&)>, llvm::raw_ostream&, llvm::StringRef, llvm::StringRef) ToolUtilities.cpp:0:0 +// #24 0x000057691654abc7 mlir::MlirOptMain(llvm::raw_ostream&, std::unique_ptr>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 +// #25 0x0000576916551e5c mlir::MlirOptMain(int, char**, llvm::StringRef, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 +// #26 0x0000576916552367 mlir::MlirOptMain(int, char**, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 +// #27 0x0000576914485056 main aie-opt.cpp:0:0 +// #28 0x0000708a2bc29d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16 +// #29 0x0000708a2bc29e40 call_init ./csu/../csu/libc-start.c:128:20 +// #30 0x0000708a2bc29e40 __libc_start_main ./csu/../csu/libc-start.c:379:5 +// #31 0x0000576914473fa5 _start (/scratch/pvasired/mlir-aie/install/bin/aie-opt+0xbf2fa5) +// Aborted (core dumped) +// module @test { +// aie.device(xcvc1902) { +// %tile12 = aie.tile(1, 2) +// %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes +// %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes +// %tile13 = aie.tile(1, 3) +// aie.objectfifo @act_3_4(%tile12, {%tile12}, 4 : i32) : !aie.objectfifo> +// } +// } + +module @test { + aie.device(xcvc1902) { + %tile12 = aie.tile(1, 2) + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes + %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes + %tile13 = aie.tile(1, 3) + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> + } +} From 8d5eeb0b008de2d21cdc11601b9ac22eab162ff8 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 12:26:18 -0600 Subject: [PATCH 12/49] Fallback routine --- .../AIE/Transforms/AIEAssignBuffers.cpp | 91 ++++++++++++++----- .../else_condition_check.mlir | 31 ------- 2 files changed, 67 insertions(+), 55 deletions(-) delete mode 100644 test/assign-buffer-addresses/else_condition_check.mlir diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 0cffd40ac1..cb9edad066 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -187,29 +187,58 @@ bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, return false; } +// Prints the memory map across banks +// void printMemMap(TileOp tile, SmallVector allBuffers, +// int numBanks, std::vector &bankLimits, +// int stacksize) { +// InFlightDiagnostic error = +// tile.emitOpError("All requested buffers doesn't fit in the available memory: Bank aware\n"); +// auto ¬e = error.attachNote() << "Current configuration of buffers in bank(s) : "; +// note << "MemoryMap:\n"; +// auto printbuffer = [&](StringRef name, int address, int size) { +// note << "\t" +// << "\t" << name << " \t" +// << ": 0x" << llvm::utohexstr(address) << "-0x" +// << llvm::utohexstr(address + size - 1) << " \t(" << size +// << " bytes)\n"; +// }; +// for (int i = 0; i < numBanks; i++) { +// note << "\t" +// << "bank : " << i << "\t" +// << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" +// << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; +// if (i == 0) { +// if (stacksize > 0) +// printbuffer("(stack)", 0, stacksize); +// else +// error << "(no stack allocated)\n"; +// } +// for (auto buffer : allBuffers) { +// auto addr = buffer.getAddress().value(); +// auto mem_bank = buffer.getMemBank().value(); +// if (mem_bank == i) +// printbuffer(buffer.name(), addr, buffer.getAllocationSize()); +// } +// } +// } + // Function that given a buffer will iterate over all the memory banks // starting from the given index to try and find a bank with enough // space. If it does, it will set the buffer's address and mem_bank // attributes and update the nextAddrInBanks vector. -// If it does not find one with enough space, it will allocate the -// buffer in the last checked bank (this will be picked up during -// overflow error checking). Finally, the function returns the index -// of the next bank to search (which should be given to subsequent +// If it does not find one with enough space, it will throw an error. +// Finally, the function returns a pass or a fail. +// The index of the next bank to search (which should be given to subsequent // calls of this function to ensure a round-robin allocation scheme // over the available banks). -bool setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, +bool setBufferAddress(BufferOp buffer, int numBanks, int &bankIndex, std::vector &nextAddrInBanks, std::vector &bankLimits) { - int bankIndex = startBankIndex; bool allocated = false; for (int i = 0; i < numBanks; i++) { int64_t startAddr = nextAddrInBanks[bankIndex]; int64_t endAddr = startAddr + buffer.getAllocationSize(); - //if (endAddr <= bankLimits[bankIndex].endAddr || i == numBanks - 1) { //Trying to fit if it is on the last bank if (endAddr <= bankLimits[bankIndex].endAddr){ - // if (endAddr > bankLimits[bankIndex].endAddr){ //That trying to fit is the problem which created the overflow - // buffer->emitWarning("Potential overflow in bank"); - // } buffer.setMemBank(bankIndex); setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); allocated = true; @@ -219,12 +248,12 @@ bool setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, // Move to the next bank bankIndex++; bankIndex %= numBanks; - } - // If allocation was not successful, handle the error + // If no bank has enough space, handle the error if(!allocated){ - buffer.emitError("Failed to allocated buffer: insufficient memory in all banks"); - //Print the memory map and the buffer that caused the error + buffer.emitError("Failed to allocate buffer: ") << buffer.name() + << " with size: " << buffer.getAllocationSize() + << " bytes."; return false; } return true; @@ -280,6 +309,14 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, return success(); } +// Function to deallocate attributes of buffers in case of a failure +void deallocationBuffers(SmallVector &buffers){ + for (auto buffer : buffers){ + buffer->removeAttr("address"); + buffer->removeAttr("mem_bank"); + } +} + LogicalResult simpleBankAwareAllocation(TileOp tile) { auto device = tile->getParentOfType(); if (!device) @@ -346,19 +383,24 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { }); // Set addresses for remaining buffers. + SmallVector allocatedBuffers; int bankIndex = 0; - for (auto buffer : buffersToAlloc) + for (auto buffer : buffersToAlloc){ + // If the buffer doesn't fit in any of the bank space then + // it prints the current memory map of the banks, + // deallocates all the buffers, and + // returns a failure. if(!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, bankLimits)){ - device.walk([&](BufferOp buffer) { - // Handle only the buffersToAlloc - if(buffer.getTileOp() == tile){ - buffer->removeAttr("address"); - buffer->removeAttr("mem_bank"); - } - }); - return failure();//basicAllocation(tile); + + //printMemMap(tile, allBuffers, numBanks, bankLimits, stacksize); + deallocationBuffers(allocatedBuffers); + return failure(); + } + else{ + allocatedBuffers.push_back(buffer); } + } // Sort by smallest address before printing memory map. std::sort(allBuffers.begin(), allBuffers.end(), [](BufferOp a, BufferOp b) { @@ -407,7 +449,8 @@ struct AIEAssignBufferAddressesPass } else { for (auto tile : device.getOps()) { if(auto res = simpleBankAwareAllocation(tile); res.failed()){ - return signalPassFailure(); + if (auto res2 = basicAllocation(tile); res2.failed()) + return signalPassFailure(); } } } diff --git a/test/assign-buffer-addresses/else_condition_check.mlir b/test/assign-buffer-addresses/else_condition_check.mlir deleted file mode 100644 index 395a054efd..0000000000 --- a/test/assign-buffer-addresses/else_condition_check.mlir +++ /dev/null @@ -1,31 +0,0 @@ -//===- else_condition_check.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses : Fails -// -// malloc(): unaligned tcache chunk detected -// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. -// Stack dump: -// 0. Program arguments: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses else_condition_check.mlir -// malloc(): unaligned tcache chunk detected -// Aborted (core dumped) - - -// RUN: aie-opt --aie-objectFifo-stateful-transform else_condition_check.mlir | aie-opt --aie-assign-buffer-addresses : Passes - -module @test { - aie.device(xcvc1902) { - %tile12 = aie.tile(1, 2) - %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes - %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes - %tile13 = aie.tile(1, 3) - aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> - } -} From 23477892b82a0d42b8ffaf798fedc643885d5dc6 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 14:08:20 -0600 Subject: [PATCH 13/49] Fallback routine --- .../AIE/Transforms/AIEAssignBuffers.cpp | 81 +++++----- .../fallback_routine.mlir | 140 ------------------ .../fallback_routine_error.mlir | 62 ++++++++ .../fallback_routine_simple.mlir | 54 +++++++ 4 files changed, 161 insertions(+), 176 deletions(-) delete mode 100644 test/assign-buffer-addresses/fallback_routine.mlir create mode 100644 test/assign-buffer-addresses/fallback_routine_error.mlir create mode 100644 test/assign-buffer-addresses/fallback_routine_simple.mlir diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index cb9edad066..f65c641d94 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -188,39 +188,45 @@ bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, } // Prints the memory map across banks -// void printMemMap(TileOp tile, SmallVector allBuffers, -// int numBanks, std::vector &bankLimits, -// int stacksize) { -// InFlightDiagnostic error = -// tile.emitOpError("All requested buffers doesn't fit in the available memory: Bank aware\n"); -// auto ¬e = error.attachNote() << "Current configuration of buffers in bank(s) : "; -// note << "MemoryMap:\n"; -// auto printbuffer = [&](StringRef name, int address, int size) { -// note << "\t" -// << "\t" << name << " \t" -// << ": 0x" << llvm::utohexstr(address) << "-0x" -// << llvm::utohexstr(address + size - 1) << " \t(" << size -// << " bytes)\n"; -// }; -// for (int i = 0; i < numBanks; i++) { -// note << "\t" -// << "bank : " << i << "\t" -// << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" -// << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; -// if (i == 0) { -// if (stacksize > 0) -// printbuffer("(stack)", 0, stacksize); -// else -// error << "(no stack allocated)\n"; -// } -// for (auto buffer : allBuffers) { -// auto addr = buffer.getAddress().value(); -// auto mem_bank = buffer.getMemBank().value(); -// if (mem_bank == i) -// printbuffer(buffer.name(), addr, buffer.getAllocationSize()); -// } -// } -// } +void printMemMap(TileOp tile, SmallVector allocatedBuffers, + SmallVector preAllocatedBuffers,int numBanks, + std::vector &bankLimits, int stacksize) { + InFlightDiagnostic error = + tile.emitOpError("All requested buffers doesn't fit in the available memory: Bank aware\n"); + auto ¬e = error.attachNote() << "Current configuration of buffers in bank(s) : "; + note << "MemoryMap:\n"; + auto printbuffer = [&](StringRef name, int address, int size) { + note << "\t" + << "\t" << name << " \t" + << ": 0x" << llvm::utohexstr(address) << "-0x" + << llvm::utohexstr(address + size - 1) << " \t(" << size + << " bytes)\n"; + }; + for (int i = 0; i < numBanks; i++) { + if (i == 0) { + if (stacksize > 0) + printbuffer("(stack)", 0, stacksize); + else + note << "(no stack allocated)\n"; + } + note << "\t" + << "bank : " << i << "\t" + << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" + << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; + for (auto buffer : preAllocatedBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + for (auto buffer : allocatedBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + } +} // Function that given a buffer will iterate over all the memory banks // starting from the given index to try and find a bank with enough @@ -310,7 +316,7 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, } // Function to deallocate attributes of buffers in case of a failure -void deallocationBuffers(SmallVector &buffers){ +void deAllocationBuffers(SmallVector &buffers){ for (auto buffer : buffers){ buffer->removeAttr("address"); buffer->removeAttr("mem_bank"); @@ -354,6 +360,7 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { fillBankLimits(numBanks, bankSize, bankLimits); SmallVector buffersToAlloc; + SmallVector preAllocatedBuffers; SmallVector allBuffers; // Collect all the buffers for this tile. device.walk([&](BufferOp buffer) { @@ -373,6 +380,8 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { nextAddrInBanks, bankLimits); if (!has_addr && !has_bank) buffersToAlloc.push_back(buffer); + else + preAllocatedBuffers.push_back(buffer); } } @@ -393,8 +402,8 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { if(!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, bankLimits)){ - //printMemMap(tile, allBuffers, numBanks, bankLimits, stacksize); - deallocationBuffers(allocatedBuffers); + printMemMap(tile, allocatedBuffers, preAllocatedBuffers, numBanks, bankLimits, stacksize); + deAllocationBuffers(allocatedBuffers); return failure(); } else{ diff --git a/test/assign-buffer-addresses/fallback_routine.mlir b/test/assign-buffer-addresses/fallback_routine.mlir deleted file mode 100644 index 69611e72ad..0000000000 --- a/test/assign-buffer-addresses/fallback_routine.mlir +++ /dev/null @@ -1,140 +0,0 @@ -//===- else_condition_check.mlir ---------------------------------------------*- MLIR -*-===// -// -// This file is licensed under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -// Copyright (C) 2024, Advanced Micro Devices, Inc. -// -//===----------------------------------------------------------------------===// - -// RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses : Fails -// -// malloc(): unaligned tcache chunk detected -// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. -// Stack dump: -// 0. Program arguments: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses else_condition_check.mlir -// malloc(): unaligned tcache chunk detected -// Aborted (core dumped) - - -// RUN: aie-opt --aie-objectFifo-stateful-transform else_condition_check.mlir | aie-opt --aie-assign-buffer-addresses : Passes - -// After merging the main with alloc-flags branch and using all the Passes, rather than just the 2. -// free(): invalid next size (fast) -// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. -// Stack dump: -// 0. Program arguments: aie-opt --aie-canonicalize-device --aie-assign-lock-ids --aie-register-objectFifos --aie-objectFifo-stateful-transform --aie-assign-bd-ids --aie-assign-buffer-addresses else_condition_check.mlir -// #0 0x000060e11514cc30 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) Signals.cpp:0:0 -// #1 0x000060e11514a56e SignalHandler(int) Signals.cpp:0:0 -// #2 0x00007d0a82a42520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520) -// #3 0x00007d0a82a969fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 -// #4 0x00007d0a82a969fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10 -// #5 0x00007d0a82a969fc pthread_kill ./nptl/pthread_kill.c:89:10 -// #6 0x00007d0a82a42476 gsignal ./signal/../sysdeps/posix/raise.c:27:6 -// #7 0x00007d0a82a287f3 abort ./stdlib/abort.c:81:7 -// #8 0x00007d0a82a89676 __libc_message ./libio/../sysdeps/posix/libc_fatal.c:155:5 -// #9 0x00007d0a82aa0cfc ./malloc/malloc.c:5668:3 -// #10 0x00007d0a82aa2a9d _int_free ./malloc/malloc.c:4522:4 -// #11 0x00007d0a82aa5453 __libc_free ./malloc/malloc.c:3394:3 -// #12 0x000060e114ef3f2e mlir::detail::OpToOpPassAdaptor::~OpToOpPassAdaptor() Pass.cpp:0:0 -// #13 0x000060e114ef5e8b mlir::PassManager::~PassManager() Pass.cpp:0:0 -// #14 0x000060e114a78453 performActions(llvm::raw_ostream&, std::shared_ptr const&, mlir::MLIRContext*, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 -// #15 0x000060e114a79683 processBuffer(llvm::raw_ostream&, std::unique_ptr>, mlir::MlirOptMainConfig const&, mlir::DialectRegistry&, llvm::ThreadPoolInterface*) MlirOptMain.cpp:0:0 -// #16 0x000060e114a797bd mlir::LogicalResult llvm::function_ref>, llvm::raw_ostream&)>::callback_fn>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&)::'lambda'(std::unique_ptr>, llvm::raw_ostream&)>(long, std::unique_ptr>, llvm::raw_ostream&) MlirOptMain.cpp:0:0 -// #17 0x000060e1150db529 mlir::splitAndProcessBuffer(std::unique_ptr>, llvm::function_ref>, llvm::raw_ostream&)>, llvm::raw_ostream&, llvm::StringRef, llvm::StringRef) ToolUtilities.cpp:0:0 -// #18 0x000060e114a72677 mlir::MlirOptMain(llvm::raw_ostream&, std::unique_ptr>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 -// #19 0x000060e114a7990c mlir::MlirOptMain(int, char**, llvm::StringRef, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 -// #20 0x000060e114a79e17 mlir::MlirOptMain(int, char**, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 -// #21 0x000060e112a3a526 main aie-opt.cpp:0:0 -// #22 0x00007d0a82a29d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16 -// #23 0x00007d0a82a29e40 call_init ./csu/../csu/libc-start.c:128:20 -// #24 0x00007d0a82a29e40 __libc_start_main ./csu/../csu/libc-start.c:379:5 -// #25 0x000060e112a298e5 _start (/scratch/pvasired/mlir-aie/install/bin/aie-opt+0xbd18e5) -// Aborted (core dumped) - -// Jeff's Output: -// #11 0x000055b3a1a27224 std::vector>::operator[](unsigned long) /usr/bin/../lib/gcc/x86_64-linux-gnu/13/../../../../include/c++/13/bits/stl_vector.h:1125:2 -// #12 0x000055b3a1a22ba0 setBufferAddress(xilinx::AIE::BufferOp, int, int, std::vector>&, std::vector>&) -// /work/acdc/aie/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp:205:25 - - -// Justifies that error occurs only from bank-aware allocation fail -// else_condition_check.mlir:63:13: error: 'aie.tile' op allocated buffers exceeded available memory: Bank aware -// (no stack allocated) - -// malloc(): unaligned tcache chunk detected -// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. -// Stack dump: -// 0. Program arguments: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses=alloc-scheme=bank-aware else_condition_check.mlir -// malloc(): unaligned tcache chunk detected -// Aborted (core dumped) - -// module @test { -// aie.device(xcvc1902) { -// %tile12 = aie.tile(1, 2) -// %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes -// %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes -// %tile13 = aie.tile(1, 3) -// aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> -// } -// } - - -// If objectFifo's source and destination is the same tile -// corrupted size vs. prev_size -// PLEASE submit a bug report to https://github.com/llvm/llvm-project/issues/ and include the crash backtrace. -// Stack dump: -// 0. Program arguments: aie-opt --aie-canonicalize-device --aie-assign-lock-ids --aie-register-objectFifos --aie-objectFifo-stateful-transform --aie-assign-bd-ids --aie-assign-buffer-addresses else_condition_check.mlir -// #0 0x0000576916c1fd00 llvm::sys::PrintStackTrace(llvm::raw_ostream&, int) Signals.cpp:0:0 -// #1 0x0000576916c1d63e SignalHandler(int) Signals.cpp:0:0 -// #2 0x0000708a2bc42520 (/lib/x86_64-linux-gnu/libc.so.6+0x42520) -// #3 0x0000708a2bc969fc __pthread_kill_implementation ./nptl/pthread_kill.c:44:76 -// #4 0x0000708a2bc969fc __pthread_kill_internal ./nptl/pthread_kill.c:78:10 -// #5 0x0000708a2bc969fc pthread_kill ./nptl/pthread_kill.c:89:10 -// #6 0x0000708a2bc42476 gsignal ./signal/../sysdeps/posix/raise.c:27:6 -// #7 0x0000708a2bc287f3 abort ./stdlib/abort.c:81:7 -// #8 0x0000708a2bc89676 __libc_message ./libio/../sysdeps/posix/libc_fatal.c:155:5 -// #9 0x0000708a2bca0cfc ./malloc/malloc.c:5668:3 -// #10 0x0000708a2bca17e2 unlink_chunk ./malloc/malloc.c:1643:2 -// #11 0x0000708a2bca1969 malloc_consolidate ./malloc/malloc.c:4780:6 -// #12 0x0000708a2bca3bdb _int_malloc ./malloc/malloc.c:3965:9 -// #13 0x0000708a2bca5262 __libc_malloc ./malloc/malloc.c:3322:7 -// #14 0x0000708a2c0b751c operator new(unsigned long) (/lib/x86_64-linux-gnu/libstdc++.so.6+0xb751c) -// #15 0x0000576916c00ef4 llvm::raw_ostream::SetBuffered() raw_ostream.cpp:0:0 -// #16 0x0000576916c01bad llvm::raw_ostream::write(char const*, unsigned long) raw_ostream.cpp:0:0 -// #17 0x0000576916b18351 void llvm::detail::UniqueFunctionBase::CallImpl::getPrintAssemblyFn()::'lambda'(mlir::Operation*, mlir::OpAsmPrinter&, llvm::StringRef) const>(void*, mlir::Operation*, mlir::OpAsmPrinter&, llvm::StringRef) BuiltinDialect.cpp:0:0 -// #18 0x0000576916b10314 mlir::RegisteredOperationName::Model::printAssembly(mlir::Operation*, mlir::OpAsmPrinter&, llvm::StringRef) BuiltinDialect.cpp:0:0 -// #19 0x0000576916ad712e mlir::Operation::print(llvm::raw_ostream&, mlir::AsmState&) AsmPrinter.cpp:0:0 -// #20 0x000057691655162e performActions(llvm::raw_ostream&, std::shared_ptr const&, mlir::MLIRContext*, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 -// #21 0x0000576916551bd3 processBuffer(llvm::raw_ostream&, std::unique_ptr>, mlir::MlirOptMainConfig const&, mlir::DialectRegistry&, llvm::ThreadPoolInterface*) MlirOptMain.cpp:0:0 -// #22 0x0000576916551d0d mlir::LogicalResult llvm::function_ref>, llvm::raw_ostream&)>::callback_fn>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&)::'lambda'(std::unique_ptr>, llvm::raw_ostream&)>(long, std::unique_ptr>, llvm::raw_ostream&) MlirOptMain.cpp:0:0 -// #23 0x0000576916bacc49 mlir::splitAndProcessBuffer(std::unique_ptr>, llvm::function_ref>, llvm::raw_ostream&)>, llvm::raw_ostream&, llvm::StringRef, llvm::StringRef) ToolUtilities.cpp:0:0 -// #24 0x000057691654abc7 mlir::MlirOptMain(llvm::raw_ostream&, std::unique_ptr>, mlir::DialectRegistry&, mlir::MlirOptMainConfig const&) MlirOptMain.cpp:0:0 -// #25 0x0000576916551e5c mlir::MlirOptMain(int, char**, llvm::StringRef, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 -// #26 0x0000576916552367 mlir::MlirOptMain(int, char**, llvm::StringRef, mlir::DialectRegistry&) MlirOptMain.cpp:0:0 -// #27 0x0000576914485056 main aie-opt.cpp:0:0 -// #28 0x0000708a2bc29d90 __libc_start_call_main ./csu/../sysdeps/nptl/libc_start_call_main.h:58:16 -// #29 0x0000708a2bc29e40 call_init ./csu/../csu/libc-start.c:128:20 -// #30 0x0000708a2bc29e40 __libc_start_main ./csu/../csu/libc-start.c:379:5 -// #31 0x0000576914473fa5 _start (/scratch/pvasired/mlir-aie/install/bin/aie-opt+0xbf2fa5) -// Aborted (core dumped) -// module @test { -// aie.device(xcvc1902) { -// %tile12 = aie.tile(1, 2) -// %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes -// %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes -// %tile13 = aie.tile(1, 3) -// aie.objectfifo @act_3_4(%tile12, {%tile12}, 4 : i32) : !aie.objectfifo> -// } -// } - -module @test { - aie.device(xcvc1902) { - %tile12 = aie.tile(1, 2) - %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes - %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> // 32 bytes - %tile13 = aie.tile(1, 3) - aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> - } -} diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir new file mode 100644 index 0000000000..f9e89fb523 --- /dev/null +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -0,0 +1,62 @@ +//===- fallback_routine.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "e" with size: 32 bytes. +// CHECK: %b1 = aie.buffer(%tile12) { sym_name = "e" } : memref<16xi16> // CHECK: 32 bytes +// CHECK: ^ +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware + +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: d : 0x4000-0x5FFF (8192 bytes) +// CHECK: bank : 3 0x6000-0x7FFF +// CHECK: a : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) + +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential +// CHECK: (no stack allocated) + +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: MemoryMap: +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: d : 0x4000-0x5FFF (8192 bytes) +// CHECK: a : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: e : 0x8000-0x801F (32 bytes) + +module @test { + aie.device(xcvc1902) { + %tile12 = aie.tile(1, 2) + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<1024xi32> //4096 bytes + %2 = aie.buffer(%tile12) { sym_name = "b" } : memref<2048xi32> //8192 bytes + %3 = aie.buffer(%tile12) { sym_name = "c" } : memref<2048xi32> //8192 bytes + %4 = aie.buffer(%tile12) { sym_name = "d" } : memref<2048xi32> //8192 bytes + %b1 = aie.buffer(%tile12) { sym_name = "e" } : memref<16xi16> //32 bytes + %tile13 = aie.tile(1, 3) + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1024 bytes + } +} diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir new file mode 100644 index 0000000000..40a3e4b4f1 --- /dev/null +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -0,0 +1,54 @@ +//===- fallback_routine.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: fallback_routine.mlir:17:8: error: Failed to allocate buffer: "a" with size: 16384 bytes. +// CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes +// CHECK: ^ +// CHECK: fallback_routine.mlir:17:8: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<4096xi32> +// CHECK: fallback_routine.mlir:16:13: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: (no stack allocated) + +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: fallback_routine.mlir:16:13: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: fallback_routine.mlir:16:13: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: bank : 3 0x6000-0x7FFF + +// CHECK: module @test { +// CHECK: aie.device(xcvc1902) { +// CHECK: memref.global "public" @act_3_4 : memref<8xi32> +// CHECK: %tile_1_2 = aie.tile(1, 2) +// CHECK: %a = aie.buffer(%tile_1_2) {address = 0 : i32, sym_name = "a"} : memref<4096xi32> +// CHECK: %b = aie.buffer(%tile_1_2) {address = 16384 : i32, sym_name = "b"} : memref<16xi16> +// CHECK: %tile_1_3 = aie.tile(1, 3) +// CHECK: %act_3_4_buff_0 = aie.buffer(%tile_1_2) {address = 16416 : i32, sym_name = "act_3_4_buff_0"} : memref<8xi32> +// CHECK: %act_3_4_buff_1 = aie.buffer(%tile_1_2) {address = 16448 : i32, sym_name = "act_3_4_buff_1"} : memref<8xi32> +// CHECK: %act_3_4_buff_2 = aie.buffer(%tile_1_2) {address = 16480 : i32, sym_name = "act_3_4_buff_2"} : memref<8xi32> +// CHECK: %act_3_4_buff_3 = aie.buffer(%tile_1_2) {address = 16512 : i32, sym_name = "act_3_4_buff_3"} : memref<8xi32> +// CHECK: %act_3_4_lock_0 = aie.lock(%tile_1_2, 0) {init = 0 : i32, sym_name = "act_3_4_lock_0"} +// CHECK: %act_3_4_lock_1 = aie.lock(%tile_1_2, 1) {init = 0 : i32, sym_name = "act_3_4_lock_1"} +// CHECK: %act_3_4_lock_2 = aie.lock(%tile_1_2, 2) {init = 0 : i32, sym_name = "act_3_4_lock_2"} +// CHECK: %act_3_4_lock_3 = aie.lock(%tile_1_2, 3) {init = 0 : i32, sym_name = "act_3_4_lock_3"} +// CHECK: } +// CHECK: } + +module @test { + aie.device(xcvc1902) { + %tile12 = aie.tile(1, 2) + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes + %b1 = aie.buffer(%tile12) { sym_name = "e" } : memref<16xi16> //32 bytes + %tile13 = aie.tile(1, 3) + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1 bytes + } +} From eb76073f775c2cb86fe529f7b2f29460a7637a7b Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 14:50:34 -0600 Subject: [PATCH 14/49] Fallback routine --- .../AIE/Transforms/AIEAssignBuffers.cpp | 2 +- .../fallback_routine_error.mlir | 81 ++++++++++--------- .../fallback_routine_simple.mlir | 2 +- 3 files changed, 45 insertions(+), 40 deletions(-) diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index f65c641d94..aa4948b2d7 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -255,7 +255,7 @@ bool setBufferAddress(BufferOp buffer, int numBanks, int &bankIndex, bankIndex++; bankIndex %= numBanks; } - // If no bank has enough space, handle the error + // If no bank has enough space, throws error if(!allocated){ buffer.emitError("Failed to allocate buffer: ") << buffer.name() << " with size: " << buffer.getAllocationSize() diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index f9e89fb523..567b3df2f3 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -1,4 +1,4 @@ -//===- fallback_routine.mlir ---------------------------------------------*- MLIR -*-===// +//===- fallback_routine_error.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -9,44 +9,48 @@ //===----------------------------------------------------------------------===// // RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s -// CHECK: error: Failed to allocate buffer: "e" with size: 32 bytes. -// CHECK: %b1 = aie.buffer(%tile12) { sym_name = "e" } : memref<16xi16> // CHECK: 32 bytes -// CHECK: ^ -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. +// CHECK: %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes +// CHECK: ^ +// CHECK: note: see current operation: %6 = "aie.buffer"(%0) <{sym_name = "f"}> : (index) -> memref<256xi16> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index -// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: -// CHECK: (no stack allocated) -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: d : 0x4000-0x5FFF (8192 bytes) -// CHECK: bank : 3 0x6000-0x7FFF -// CHECK: a : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: a : 0x4000-0x4FFF (4096 bytes) +// CHECK: e : 0x5000-0x5FFF (4096 bytes) +// CHECK: bank : 3 0x6000-0x7FFF +// CHECK: d : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) -// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential -// CHECK: (no stack allocated) +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential +// CHECK: (no stack allocated) -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: MemoryMap: -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: d : 0x4000-0x5FFF (8192 bytes) -// CHECK: a : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) -// CHECK: e : 0x8000-0x801F (32 bytes) +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: note: MemoryMap: +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: a : 0x4000-0x4FFF (4096 bytes) +// CHECK: d : 0x5000-0x5FFF (4096 bytes) +// CHECK: e : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: f : 0x8000-0x81FF (512 bytes) module @test { aie.device(xcvc1902) { @@ -54,8 +58,9 @@ module @test { %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<1024xi32> //4096 bytes %2 = aie.buffer(%tile12) { sym_name = "b" } : memref<2048xi32> //8192 bytes %3 = aie.buffer(%tile12) { sym_name = "c" } : memref<2048xi32> //8192 bytes - %4 = aie.buffer(%tile12) { sym_name = "d" } : memref<2048xi32> //8192 bytes - %b1 = aie.buffer(%tile12) { sym_name = "e" } : memref<16xi16> //32 bytes + %4 = aie.buffer(%tile12) { sym_name = "d" } : memref<1024xi32> //4096 bytes + %5 = aie.buffer(%tile12) { sym_name = "e" } : memref<1024xi32> //4096 bytes + %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes %tile13 = aie.tile(1, 3) aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1024 bytes } diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir index 40a3e4b4f1..a534d35f14 100644 --- a/test/assign-buffer-addresses/fallback_routine_simple.mlir +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -1,4 +1,4 @@ -//===- fallback_routine.mlir ---------------------------------------------*- MLIR -*-===// +//===- fallback_routine_simple.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. From 1ee9a2a98f143ccbbb7bc065a5caeac8392890da Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 15:05:27 -0600 Subject: [PATCH 15/49] Code format --- python/compiler/aiecc/main.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index b6746caad4..22ce0f220a 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -979,9 +979,9 @@ async def run_flow(self): file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") if opts.alloc_scheme: - pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE(opts.alloc_scheme).materialize( - module=True - ) + pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( + opts.alloc_scheme + ).materialize(module=True) else: pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE().materialize(module=True) run_passes( From 181314de58b5d2e76d761f4d5b7a11163d14db43 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 15:12:58 -0600 Subject: [PATCH 16/49] Code formatting --- include/aie/Dialect/AIE/IR/AIETargetModel.h | 4 +- lib/CAPI/TargetModel.cpp | 3 +- .../AIE/Transforms/AIEAssignBuffers.cpp | 112 +++++++++--------- 3 files changed, 62 insertions(+), 57 deletions(-) diff --git a/include/aie/Dialect/AIE/IR/AIETargetModel.h b/include/aie/Dialect/AIE/IR/AIETargetModel.h index 34f071172e..01f40c60a6 100644 --- a/include/aie/Dialect/AIE/IR/AIETargetModel.h +++ b/include/aie/Dialect/AIE/IR/AIETargetModel.h @@ -323,7 +323,9 @@ class AIE2TargetModel : public AIETargetModel { uint32_t getMemTileSize() const override { return 0x00080000; } - uint32_t getNumBanks(int col, int row) const override { return isMemTile(col, row) ? 8 : 4; } + uint32_t getNumBanks(int col, int row) const override { + return isMemTile(col, row) ? 8 : 4; + } uint32_t getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const override; diff --git a/lib/CAPI/TargetModel.cpp b/lib/CAPI/TargetModel.cpp index 7d046d82ae..2eb5105917 100644 --- a/lib/CAPI/TargetModel.cpp +++ b/lib/CAPI/TargetModel.cpp @@ -149,7 +149,8 @@ uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel) { return unwrap(targetModel).getMemTileSize(); } -uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row) { +uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, + int row) { return unwrap(targetModel).getNumBanks(col, row); } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index aa4948b2d7..11a46ffd25 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -28,8 +28,8 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int address, int maxDataMemorySize, int stacksize, SmallVector buffers) { if (address > maxDataMemorySize) { - InFlightDiagnostic error = - tile.emitOpError("allocated buffers exceeded available memory: Sequential\n"); + InFlightDiagnostic error = tile.emitOpError( + "allocated buffers exceeded available memory: Sequential\n"); auto ¬e = error.attachNote() << "MemoryMap:\n"; auto printbuffer = [&](StringRef name, int address, int size) { note << "\t" << name << " \t" @@ -189,62 +189,64 @@ bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, // Prints the memory map across banks void printMemMap(TileOp tile, SmallVector allocatedBuffers, - SmallVector preAllocatedBuffers,int numBanks, - std::vector &bankLimits, int stacksize) { + SmallVector preAllocatedBuffers, int numBanks, + std::vector &bankLimits, int stacksize) { InFlightDiagnostic error = - tile.emitOpError("All requested buffers doesn't fit in the available memory: Bank aware\n"); - auto ¬e = error.attachNote() << "Current configuration of buffers in bank(s) : "; + tile.emitOpError("All requested buffers doesn't fit in the available " + "memory: Bank aware\n"); + auto ¬e = error.attachNote() + << "Current configuration of buffers in bank(s) : "; note << "MemoryMap:\n"; auto printbuffer = [&](StringRef name, int address, int size) { note << "\t" - << "\t" << name << " \t" - << ": 0x" << llvm::utohexstr(address) << "-0x" - << llvm::utohexstr(address + size - 1) << " \t(" << size - << " bytes)\n"; + << "\t" << name << " \t" + << ": 0x" << llvm::utohexstr(address) << "-0x" + << llvm::utohexstr(address + size - 1) << " \t(" << size + << " bytes)\n"; }; - for (int i = 0; i < numBanks; i++) { - if (i == 0) { - if (stacksize > 0) - printbuffer("(stack)", 0, stacksize); - else - note << "(no stack allocated)\n"; - } - note << "\t" - << "bank : " << i << "\t" - << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" - << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; - for (auto buffer : preAllocatedBuffers) { - auto addr = buffer.getAddress().value(); - auto mem_bank = buffer.getMemBank().value(); - if (mem_bank == i) - printbuffer(buffer.name(), addr, buffer.getAllocationSize()); - } - for (auto buffer : allocatedBuffers) { - auto addr = buffer.getAddress().value(); - auto mem_bank = buffer.getMemBank().value(); - if (mem_bank == i) - printbuffer(buffer.name(), addr, buffer.getAllocationSize()); - } + for (int i = 0; i < numBanks; i++) { + if (i == 0) { + if (stacksize > 0) + printbuffer("(stack)", 0, stacksize); + else + note << "(no stack allocated)\n"; } + note << "\t" + << "bank : " << i << "\t" + << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" + << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; + for (auto buffer : preAllocatedBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + for (auto buffer : allocatedBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + } } // Function that given a buffer will iterate over all the memory banks // starting from the given index to try and find a bank with enough // space. If it does, it will set the buffer's address and mem_bank // attributes and update the nextAddrInBanks vector. -// If it does not find one with enough space, it will throw an error. +// If it does not find one with enough space, it will throw an error. // Finally, the function returns a pass or a fail. // The index of the next bank to search (which should be given to subsequent // calls of this function to ensure a round-robin allocation scheme // over the available banks). bool setBufferAddress(BufferOp buffer, int numBanks, int &bankIndex, - std::vector &nextAddrInBanks, - std::vector &bankLimits) { + std::vector &nextAddrInBanks, + std::vector &bankLimits) { bool allocated = false; for (int i = 0; i < numBanks; i++) { int64_t startAddr = nextAddrInBanks[bankIndex]; int64_t endAddr = startAddr + buffer.getAllocationSize(); - if (endAddr <= bankLimits[bankIndex].endAddr){ + if (endAddr <= bankLimits[bankIndex].endAddr) { buffer.setMemBank(bankIndex); setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); allocated = true; @@ -256,10 +258,10 @@ bool setBufferAddress(BufferOp buffer, int numBanks, int &bankIndex, bankIndex %= numBanks; } // If no bank has enough space, throws error - if(!allocated){ - buffer.emitError("Failed to allocate buffer: ") << buffer.name() - << " with size: " << buffer.getAllocationSize() - << " bytes."; + if (!allocated) { + buffer.emitError("Failed to allocate buffer: ") + << buffer.name() << " with size: " << buffer.getAllocationSize() + << " bytes."; return false; } return true; @@ -278,8 +280,8 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, } } if (foundOverflow) { - InFlightDiagnostic error = - tile.emitOpError("allocated buffers exceeded available memory: Bank aware\n"); + InFlightDiagnostic error = tile.emitOpError( + "allocated buffers exceeded available memory: Bank aware\n"); auto ¬e = error.attachNote() << "Error in bank(s) : "; for (auto bank : overflow_banks) note << bank << " "; @@ -316,8 +318,8 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, } // Function to deallocate attributes of buffers in case of a failure -void deAllocationBuffers(SmallVector &buffers){ - for (auto buffer : buffers){ +void deAllocationBuffers(SmallVector &buffers) { + for (auto buffer : buffers) { buffer->removeAttr("address"); buffer->removeAttr("mem_bank"); } @@ -394,19 +396,19 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { // Set addresses for remaining buffers. SmallVector allocatedBuffers; int bankIndex = 0; - for (auto buffer : buffersToAlloc){ - // If the buffer doesn't fit in any of the bank space then - // it prints the current memory map of the banks, + for (auto buffer : buffersToAlloc) { + // If the buffer doesn't fit in any of the bank space then + // it prints the current memory map of the banks, // deallocates all the buffers, and // returns a failure. - if(!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, - bankLimits)){ - - printMemMap(tile, allocatedBuffers, preAllocatedBuffers, numBanks, bankLimits, stacksize); + if (!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, + bankLimits)) { + + printMemMap(tile, allocatedBuffers, preAllocatedBuffers, numBanks, + bankLimits, stacksize); deAllocationBuffers(allocatedBuffers); return failure(); - } - else{ + } else { allocatedBuffers.push_back(buffer); } } @@ -457,7 +459,7 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { - if(auto res = simpleBankAwareAllocation(tile); res.failed()){ + if (auto res = simpleBankAwareAllocation(tile); res.failed()) { if (auto res2 = basicAllocation(tile); res2.failed()) return signalPassFailure(); } From 6201c291fc1320a1c8e20dd682af512ccc9048c8 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 15:33:12 -0600 Subject: [PATCH 17/49] Check message --- .../bank_aware_alloc_error.mlir | 50 +++++++++---------- .../bank_aware_alloc_memtile_error.mlir | 39 ++++++++++----- .../bank_aware_alloc_memtile_simple.mlir | 37 ++++++++++---- .../bank_aware_alloc_simple.mlir | 35 +++++++------ 4 files changed, 96 insertions(+), 65 deletions(-) diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index a048e6db18..6106c7e82c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -8,32 +8,32 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s -// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory -// CHECK: Error in bank(s) : 3 -// CHECK: MemoryMap: -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: (stack) : 0x0-0x3FF (1024 bytes) -// CHECK: c : 0x400-0x41F (32 bytes) -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: a : 0x2000-0x200F (16 bytes) -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: bank : 3 0x6000-0x7FFF -// CHECK: b : 0x6000-0xDFFF (32768 bytes) +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s +// 2>&1 | FileCheck %s CHECK: error: Failed to allocate buffer: "b" with size: +// 32768 bytes. CHECK: %1 = aie.buffer(%0) { sym_name = "b" } : +// memref<8192xi32> CHECK: ^ CHECK: note: see current operation: %2 +// = "aie.buffer"(%0) <{sym_name = "b"}> : (index) -> memref<8192xi32> CHECK: +// error: 'aie.tile' op All requested buffers doesn't fit in the available +// memory: Bank aware + +// CHECK: %0 = aie.tile(3, 3) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row +// = 3 : i32}> : () -> index CHECK: note: Current configuration of buffers in +// bank(s) : MemoryMap: CHECK: (stack) : 0x0-0x3FF +// (1024 bytes) CHECK: bank : 0 0x0-0x1FFF CHECK: bank : 1 +// 0x2000-0x3FFF CHECK: bank : 2 0x4000-0x5FFF CHECK: bank : 3 +// 0x6000-0x7FFF module @test { - aie.device(xcvc1902) { - %0 = aie.tile(3, 3) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> - %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> - %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) - %4 = aie.buffer(%3) : memref<500xi32> - aie.core(%0) { - aie.end - } - aie.core(%3) { - aie.end + aie.device(xcvc1902) { + % 0 = aie.tile(3, 3) % b1 = + aie.buffer(% 0){sym_name = "a"} : memref<16xi8> % 1 = + aie.buffer(% 0){sym_name = "b"} : memref<8192xi32> % b2 = + aie.buffer(% 0){sym_name = "c"} : memref<16xi16> % 3 = + aie.tile(4, 4) % 4 = aie.buffer(% 3) + : memref<500xi32> aie.core(% 0){aie.end} aie.core(% 3) { + aie.end + } } - } } diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index 14d621e6bc..7e66b2d701 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -1,4 +1,5 @@ -//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- memtile_error.mlir ---------------------------------------*- MLIR +//-*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,20 +9,32 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s -// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory -// CHECK: Error in bank(s) : 0 -// CHECK: MemoryMap: -// CHECK: bank : 0 0x0-0x7FFFF -// CHECK: a : 0x0-0x80E7F (528000 bytes) +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s +// 2>&1 | FileCheck %s CHECK: error: Failed to allocate buffer: "a" with size: +// 528000 bytes. CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : +// memref<132000xi32> CHECK: ^ CHECK: note: see current operation: +// %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<132000xi32> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the +// available memory: Bank aware +// CHECK: %0 = aie.tile(3, 1) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row +// = 1 : i32}> : () -> index CHECK: note: Current configuration of buffers in +// bank(s) : MemoryMap: CHECK: (no stack allocated) CHECK: bank : +// 0 0x0-0xFFFF CHECK: bank : 1 0x10000-0x1FFFF CHECK: +// bank : 2 0x20000-0x2FFFF CHECK: bank : 3 0x30000-0x3FFFF +// CHECK: bank : 4 0x40000-0x4FFFF +// CHECK: bank : 5 0x50000-0x5FFFF +// CHECK: bank : 6 0x60000-0x6FFFF +// CHECK: bank : 7 0x70000-0x7FFFF module @test { - aie.device(xcve2302) { - %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> - aie.memtile_dma(%0) { - aie.end + aie.device(xcve2302) { + % 0 = aie.tile(3, 1) % b1 = + aie.buffer(% 0){sym_name = "a"} : memref<132000xi32> aie + .memtile_dma(% 0) { + aie.end + } } - } } diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir index f41d28547c..fa771a6090 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -1,4 +1,5 @@ -//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- memtile_simple.mlir --------------------------------------*- MLIR +//-*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,15 +9,33 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 +// | FileCheck %s CHECK: error: Failed to allocate buffer: "a" with size: +// 262144 bytes. CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : +// memref<65536xi32> CHECK: ^ CHECK: note: see current operation: +// %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<65536xi32> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the +// available memory: Bank aware + +// CHECK: %0 = aie.tile(3, 1) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row +// = 1 : i32}> : () -> index CHECK: note: Current configuration of buffers in +// bank(s) : MemoryMap: CHECK: (no stack allocated) CHECK: bank : +// 0 0x0-0xFFFF CHECK: bank : 1 0x10000-0x1FFFF CHECK: +// bank : 2 0x20000-0x2FFFF CHECK: bank : 3 0x30000-0x3FFFF +// CHECK: bank : 4 0x40000-0x4FFFF +// CHECK: bank : 5 0x50000-0x5FFFF +// CHECK: bank : 6 0x60000-0x6FFFF +// CHECK: bank : 7 0x70000-0x7FFFF module @test { - aie.device(xcve2302) { - %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> - aie.memtile_dma(%0) { - aie.end + aie.device(xcve2302) { + % 0 = + aie.tile(3, 1) % b1 = + aie.buffer(% 0){sym_name = "a"} : memref<65536xi32> aie.memtile_dma( + % 0) { + aie.end + } } - } } diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index e479fb1fd2..7dc499c8c0 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -8,25 +8,24 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | +// FileCheck %s CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, +// mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> CHECK: {{.*}} +// aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} +// : memref<512xi32> CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, +// mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> CHECK: {{.*}} +// aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = +// "_anonymous0"} : memref<500xi32> module @test { - aie.device(xcvc1902) { - %0 = aie.tile(3, 3) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> - %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> - %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) - %4 = aie.buffer(%3) : memref<500xi32> - aie.core(%0) { - aie.end + aie.device(xcvc1902) { + % 0 = aie.tile(3, 3) % b1 = + aie.buffer(% 0){sym_name = "a"} : memref<16xi8> % 1 = + aie.buffer(% 0){sym_name = "b"} : memref<512xi32> % b2 = + aie.buffer(% 0){sym_name = "c"} : memref<16xi16> % 3 = + aie.tile(4, 4) % 4 = aie.buffer(% 3) + : memref<500xi32> aie.core(% 0){aie.end} aie.core(% 3) { + aie.end + } } - aie.core(%3) { - aie.end - } - } } From 7d269455f170da74ce2007fae3177ae0a96bbdff Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 15:36:26 -0600 Subject: [PATCH 18/49] Check message --- test/assign-buffer-addresses/fallback_routine_simple.mlir | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir index a534d35f14..0d5986b2a8 100644 --- a/test/assign-buffer-addresses/fallback_routine_simple.mlir +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -12,14 +12,14 @@ // CHECK: fallback_routine.mlir:17:8: error: Failed to allocate buffer: "a" with size: 16384 bytes. // CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes // CHECK: ^ -// CHECK: fallback_routine.mlir:17:8: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<4096xi32> -// CHECK: fallback_routine.mlir:16:13: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<4096xi32> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware // CHECK: (no stack allocated) // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ -// CHECK: fallback_routine.mlir:16:13: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index -// CHECK: fallback_routine.mlir:16:13: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: // CHECK: bank : 0 0x0-0x1FFF // CHECK: bank : 1 0x2000-0x3FFF // CHECK: bank : 2 0x4000-0x5FFF From 71ba614ea36058c53846574c5f35f73fb587bbab Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 15:54:58 -0600 Subject: [PATCH 19/49] Check Message --- .../basic_alloc_memtile_simple.mlir | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index 94b95d7eef..b504d6cc43 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -9,8 +9,15 @@ //===----------------------------------------------------------------------===// // RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> - +// CHECK: module @test { +// CHECK: aie.device(xcve2302) { +// CHECK: %tile_3_1 = aie.tile(3, 1) +// CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> +// CHECK: %memtile_dma_3_1 = aie.memtile_dma(%tile_3_1) { +// CHECK: aie.end +// CHECK: } +// CHECK: } +// CHECK: } module @test { aie.device(xcve2302) { %0 = aie.tile(3, 1) From 383b6dbca2b5135853aabcc0a08b88d0525f14fc Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 15:56:44 -0600 Subject: [PATCH 20/49] Check Message --- test/assign-buffer-addresses/fallback_routine_simple.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir index 0d5986b2a8..63a8145443 100644 --- a/test/assign-buffer-addresses/fallback_routine_simple.mlir +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s -// CHECK: fallback_routine.mlir:17:8: error: Failed to allocate buffer: "a" with size: 16384 bytes. +// CHECK: error: Failed to allocate buffer: "a" with size: 16384 bytes. // CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes // CHECK: ^ // CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<4096xi32> From 33ac05dac211d047361feb9a6b774b7618b2f100 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 16:07:10 -0600 Subject: [PATCH 21/49] Allocation flags --- test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir | 2 +- test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir | 2 +- test/benchmarks/03_Flood_DDR/aie.mlir | 2 +- test/generate-mmap/allocation_error.mlir | 2 +- test/generate-mmap/allocation_error_chess.mlir | 2 +- test/npu-xrt/add_one_using_dma/run.lit | 2 +- test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir | 2 +- test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir index 02a31927cc..7598136b06 100755 --- a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir +++ b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark01_DDR_SHIM_fill_rate { diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir index 00c411181b..820c2a91af 100755 --- a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir +++ b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark_02_LM2DDR { diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir index f5d92661d8..f48c45ff79 100755 --- a/test/benchmarks/03_Flood_DDR/aie.mlir +++ b/test/benchmarks/03_Flood_DDR/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark03_Flood_DDR { diff --git a/test/generate-mmap/allocation_error.mlir b/test/generate-mmap/allocation_error.mlir index 602960bd57..1725cfb7a4 100644 --- a/test/generate-mmap/allocation_error.mlir +++ b/test/generate-mmap/allocation_error.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: peano -// RUN: not aiecc.py --basic-alloc-scheme --no-xchesscc --no-xbridge %s 2>&1 | FileCheck %s --check-prefix=PEANO +// RUN: not aiecc.py --alloc-scheme=basic-sequential --no-xchesscc --no-xbridge %s 2>&1 | FileCheck %s --check-prefix=PEANO // PEANO: ld.lld: error: section '.bss' will not fit in region 'data': overflowed by 4 bytes // If we use all of the local memory, then linking the AIE executable should fail. diff --git a/test/generate-mmap/allocation_error_chess.mlir b/test/generate-mmap/allocation_error_chess.mlir index 6bb1a97699..bd7139177b 100644 --- a/test/generate-mmap/allocation_error_chess.mlir +++ b/test/generate-mmap/allocation_error_chess.mlir @@ -9,7 +9,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: chess -// RUN: not aiecc.py --basic-alloc-scheme --xchesscc --xbridge %s 2>&1 | FileCheck %s --check-prefix=CHESS +// RUN: not aiecc.py --alloc-scheme=basic-sequential --xchesscc --xbridge %s 2>&1 | FileCheck %s --check-prefix=CHESS // CHESS: Error: could not find free space for SpaceSymbol x in memory DMb // If we use all of the local memory, then linking the AIE executable should fail. diff --git a/test/npu-xrt/add_one_using_dma/run.lit b/test/npu-xrt/add_one_using_dma/run.lit index 35aa0b374d..a3ce61f18b 100644 --- a/test/npu-xrt/add_one_using_dma/run.lit +++ b/test/npu-xrt/add_one_using_dma/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir index f8bb745176..f647e844c3 100644 --- a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir +++ b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_vck5000 ./test.elf module @test18_simple_shim_dma_routed { diff --git a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir index f8aa235f94..14c84504f5 100644 --- a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir +++ b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_vck5000 ./test.elf module @test20_shim_dma_broadcast { From 8fb7e05ca04cc8a58ad9598c087414de43db989e Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 16:19:15 -0600 Subject: [PATCH 22/49] Allocation Flags --- .../01_DDR_SHIM_LM_FillRate/aie.mlir | 81 +- .../02_LM_SHIM_DDR_FillRate/aie.mlir | 93 +- test/benchmarks/03_Flood_DDR/aie.mlir | 1821 ++++++++++------- test/generate-mmap/allocation_error.mlir | 53 +- .../generate-mmap/allocation_error_chess.mlir | 53 +- test/npu-xrt/add_one_using_dma/run.lit | 11 +- .../aie/18_simple_shim_dma_routed/aie.mlir | 89 +- .../aie/20_shim_dma_broadcast/aie.mlir | 137 +- 8 files changed, 1404 insertions(+), 934 deletions(-) mode change 100755 => 100644 test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir mode change 100755 => 100644 test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir mode change 100755 => 100644 test/benchmarks/03_Flood_DDR/aie.mlir diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir old mode 100755 new mode 100644 index 7598136b06..3024f8cf47 --- a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir +++ b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir @@ -8,57 +8,54 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf -// RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential +// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s +// -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib +// -ltest_lib %S/test.cpp -o test.elf RUN: %run_on_board ./test.elf module @benchmark01_DDR_SHIM_fill_rate { - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - //%t72 = aie.tile(7, 2) + % t70 = aie.tile(7, 0) % + t71 = aie.tile(7, 1) + //%t72 = aie.tile(7, 2) - %buffer = aie.external_buffer {sym_name = "buffer" } : memref<7168xi32> + % buffer = aie.external_buffer{sym_name = "buffer"} + : memref<7168xi32> - // Fixup - %sw = aie.switchbox(%t70) { - aie.connect<"South" : 3, "North" : 3> - } - %mux = aie.shim_mux(%t70) { - aie.connect<"DMA" : 0, "North": 3> - } + // Fixup + % sw = aie.switchbox(% t70){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux = aie.shim_mux(% t70){aie.connect < "DMA" : 0, "North" : 3 > } - %swdma = aie.switchbox(%t71) { - aie.connect<"South" : 3, "DMA" : 0> - } + % swdma = + aie.switchbox(% t71){aie.connect < "South" : 3, "DMA" : 0 > } - %dma = aie.shim_dma(%t70) { - %lock1 = aie.lock(%t70, 1) + % dma = aie.shim_dma(% t70){ + % lock1 = aie.lock(% t70, 1) - aie.dma_start(MM2S, 0, ^bd0, ^end) + aie.dma_start(MM2S, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %buf71_0 = aie.buffer(%t71) {sym_name = "buf71_0" } : memref<7168xi32> + ^ bd0 : aie.use_lock(% lock1, Acquire, 1) + aie.dma_bd(% buffer + : memref<7168xi32>, 0, 7168) + aie.use_lock(% lock1, Release, 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } - %l71_0 = aie.lock(%t71, 0) - %l71_1 = aie.lock(%t71, 1) + % buf71_0 = aie.buffer(% t71){sym_name = "buf71_0"} + : memref<7168xi32> - %m71 = aie.mem(%t71) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l71_0, "Acquire", 0) - aie.dma_bd(%buf71_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l71_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } -} + % l71_0 = aie.lock(% t71, 0) % l71_1 = + aie.lock(% t71, 1) + % m71 = aie.mem(% t71) { + % srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^ + bd0 : aie.use_lock(% l71_0, "Acquire", 0) + aie.dma_bd(% buf71_0 + : memref<7168xi32>, 0, 7168) + aie.use_lock(% l71_0, "Release", 1) aie.next_bd ^ + end ^ end : aie.end + } +} diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir old mode 100755 new mode 100644 index 820c2a91af..68e480da19 --- a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir +++ b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir @@ -8,55 +8,62 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf -// RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential +// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s +// -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib +// -ltest_lib %S/test.cpp -o test.elf RUN: %run_on_board ./test.elf module @benchmark_02_LM2DDR { - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - - %lock_a_ping = aie.lock(%t71, 3) // a_ping - - %buf71_0 = aie.buffer(%t71) {sym_name = "buf71_0" } : memref<7168xi32> - - //Declare the buffers - %buffer_out = aie.external_buffer {sym_name = "buffer" } : memref<7168xi32> - - %m71 = aie.mem(%t71) { - %srcDma = aie.dma_start(MM2S, 1, ^bd0, ^end) - ^bd0: - aie.use_lock(%lock_a_ping, "Acquire", 0) - aie.dma_bd(%buf71_0 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock_a_ping, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } + % t70 = + aie.tile(7, 0) % t71 = + aie.tile(7, 1) - %dma = aie.shim_dma(%t70) { - %lock1 = aie.lock(%t70, 2) + % lock_a_ping = + aie.lock(% t71, 3) // a_ping - aie.dma_start(S2MM, 0, ^bd0, ^end) + % buf71_0 = + aie.buffer(% t71){sym_name = "buf71_0"} : memref<7168xi32> - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } + // Declare the buffers + % buffer_out = aie.external_buffer{sym_name = "buffer"} + : memref<7168xi32> - // Shim DMA connection to kernel - %sw2 = aie.switchbox(%t71){ - aie.connect<"DMA" : 1, "South" : 2> - } - - %sw1 = aie.switchbox(%t70) { - aie.connect<"North" : 2, "South" : 2> - } - %mux1 = aie.shim_mux (%t70) { + % m71 = aie.mem(% t71){ + % srcDma = + aie.dma_start(MM2S, 1, ^bd0, ^end) ^ + bd0 : aie.use_lock(% lock_a_ping, "Acquire", 0) + aie.dma_bd(% buf71_0 + : memref<7168xi32>, 0, 7168) + aie.use_lock(% lock_a_ping, "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % + dma = aie.shim_dma(% t70){ + % lock1 = aie.lock(% t70, 2) + + aie.dma_start(S2MM, 0, ^bd0, ^end) + + ^ bd0 : aie.use_lock(% lock1, Acquire, 1) + aie.dma_bd(% buffer_out + : memref<7168xi32>, 0, 7168) + aie.use_lock(% lock1, Release, 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + // Shim DMA connection to kernel + % sw2 = aie.switchbox(% t71){ + aie.connect < "DMA" : 1, + "South" : 2 > + } + + % sw1 = aie.switchbox( + % t70){ + aie.connect < "North" : 2, + "South" : 2 > + } % mux1 = aie.shim_mux(% t70) { aie.connect<"North" : 2, "DMA" : 0> } - } diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir old mode 100755 new mode 100644 index f48c45ff79..25e1ab71f1 --- a/test/benchmarks/03_Flood_DDR/aie.mlir +++ b/test/benchmarks/03_Flood_DDR/aie.mlir @@ -8,708 +8,1135 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf -// RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential +// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s +// -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib +// -ltest_lib %S/test.cpp -o test.elf RUN: %run_on_board ./test.elf module @benchmark03_Flood_DDR { - - %t20 = aie.tile(2, 0) - %t21 = aie.tile(2, 1) - - %sw2 = aie.switchbox(%t20) { - aie.connect<"South" : 3, "North" : 3> - } - %mux2 = aie.shim_mux(%t20) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma2 = aie.switchbox(%t21) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf21_0 = aie.buffer(%t21) {sym_name = "buf21_0" } : memref<7168xi32> - %l21_0 = aie.lock(%t21, 0) - - %m21 = aie.mem(%t21) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l21_0, "Acquire", 0) - aie.dma_bd(%buf21_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l21_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_20 = aie.external_buffer {sym_name = "buffer_out_20" } : memref<7168xi32> - %l20 = aie.lock(%t20, 1) - %dma20 = aie.shim_dma(%t20) { - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%l20, Acquire, 1) - aie.dma_bd(%buffer_out_20 : memref<7168xi32>, 0, 7168) - aie.use_lock(%l20, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t30 = aie.tile(3, 0) - %t31 = aie.tile(3, 1) - - %sw3 = aie.switchbox(%t30) { - aie.connect<"South" : 3, "North" : 3> - } - %mux3 = aie.shim_mux(%t30) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma3 = aie.switchbox(%t31) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf31_0 = aie.buffer(%t31) {sym_name = "buf31_0" } : memref<7168xi32> - %l31_0 = aie.lock(%t31, 0) - - %m31 = aie.mem(%t31) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l31_0, "Acquire", 0) - aie.dma_bd(%buf31_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l31_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_30 = aie.external_buffer {sym_name = "buffer_out_30" } : memref<7168xi32> - %dma30 = aie.shim_dma(%t30) { - %lock1 = aie.lock(%t30, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_30 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t60 = aie.tile(6, 0) - %t61 = aie.tile(6, 1) - - %sw6 = aie.switchbox(%t60) { - aie.connect<"South" : 3, "North" : 3> - } - %mux6 = aie.shim_mux(%t60) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma6 = aie.switchbox(%t61) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf61_0 = aie.buffer(%t61) {sym_name = "buf61_0" } : memref<7168xi32> - %l61_0 = aie.lock(%t61, 0) - - %m61 = aie.mem(%t61) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l61_0, "Acquire", 0) - aie.dma_bd(%buf61_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l61_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_60 = aie.external_buffer {sym_name = "buffer_out_60" } : memref<7168xi32> - %dma60 = aie.shim_dma(%t60) { - %lock1 = aie.lock(%t60, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_60 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t70 = aie.tile(7, 0) - %t71 = aie.tile(7, 1) - - - %sw = aie.switchbox(%t70) { - aie.connect<"South" : 3, "North" : 3> - } - %mux = aie.shim_mux(%t70) { - aie.connect<"DMA" : 0, "North": 3> - } - - - %swdma = aie.switchbox(%t71) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf71_0 = aie.buffer(%t71) {sym_name = "buf71_0" } : memref<7168xi32> - - %l71_0 = aie.lock(%t71, 0) - - %m71 = aie.mem(%t71) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l71_0, "Acquire", 0) - aie.dma_bd(%buf71_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l71_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_70 = aie.external_buffer {sym_name = "buffer_out_70" } : memref<7168xi32> - %dma70 = aie.shim_dma(%t70) { - %lock1 = aie.lock(%t70, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_70 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t100 = aie.tile(10, 0) - %t101 = aie.tile(10, 1) - - - %sw10 = aie.switchbox(%t100) { - aie.connect<"South" : 3, "North" : 3> - } - %mux10 = aie.shim_mux(%t100) { - aie.connect<"DMA" : 0, "North": 3> - } - - - %swdma10 = aie.switchbox(%t101) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf101_0 = aie.buffer(%t101) {sym_name = "buf101_0" } : memref<7168xi32> - - %l101_0 = aie.lock(%t101, 0) - - %m101 = aie.mem(%t101) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l101_0, "Acquire", 0) - aie.dma_bd(%buf101_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l101_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_100 = aie.external_buffer {sym_name = "buffer_out_100" } : memref<7168xi32> - %dma100 = aie.shim_dma(%t100) { - %lock1 = aie.lock(%t100, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_100 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t110 = aie.tile(11, 0) - %t111 = aie.tile(11, 1) - - %sw11 = aie.switchbox(%t110) { - aie.connect<"South" : 3, "North" : 3> - } - %mux11 = aie.shim_mux(%t110) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma11 = aie.switchbox(%t111) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf111_0 = aie.buffer(%t111) {sym_name = "buf111_0" } : memref<7168xi32> - %l111_0 = aie.lock(%t111, 0) - - %m111 = aie.mem(%t111) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l111_0, "Acquire", 0) - aie.dma_bd(%buf111_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l111_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_110 = aie.external_buffer {sym_name = "buffer_out_110" } : memref<7168xi32> - %dma110 = aie.shim_dma(%t110) { - %lock1 = aie.lock(%t110, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_110 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t180 = aie.tile(18, 0) - %t181 = aie.tile(18, 1) - - %sw18 = aie.switchbox(%t180) { - aie.connect<"South" : 3, "North" : 3> - } - %mux18 = aie.shim_mux(%t180) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma18 = aie.switchbox(%t181) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf181_0 = aie.buffer(%t181) {sym_name = "buf181_0" } : memref<7168xi32> - %l181_0 = aie.lock(%t181, 0) - - %m181 = aie.mem(%t181) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l181_0, "Acquire", 0) - aie.dma_bd(%buf181_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l181_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_180 = aie.external_buffer {sym_name = "buffer_out_180" } : memref<7168xi32> - %dma180 = aie.shim_dma(%t180) { - %lock1 = aie.lock(%t180, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_180 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - - %t190 = aie.tile(19, 0) - %t191 = aie.tile(19, 1) - - %sw19 = aie.switchbox(%t190) { - aie.connect<"South" : 3, "North" : 3> - } - %mux19 = aie.shim_mux(%t190) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma19 = aie.switchbox(%t191) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf191_0 = aie.buffer(%t191) {sym_name = "buf191_0" } : memref<7168xi32> - %l191_0 = aie.lock(%t191, 0) - - %m191 = aie.mem(%t191) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l191_0, "Acquire", 0) - aie.dma_bd(%buf191_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l191_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_190 = aie.external_buffer {sym_name = "buffer_out_190" } : memref<7168xi32> - %dma190 = aie.shim_dma(%t190) { - %lock1 = aie.lock(%t190, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_190 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t260 = aie.tile(26, 0) - %t261 = aie.tile(26, 1) - - %sw26 = aie.switchbox(%t260) { - aie.connect<"South" : 3, "North" : 3> - } - %mux26 = aie.shim_mux(%t260) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma26 = aie.switchbox(%t261) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf261_0 = aie.buffer(%t261) {sym_name = "buf261_0" } : memref<7168xi32> - %l261_0 = aie.lock(%t261, 0) - - %m261 = aie.mem(%t261) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l261_0, "Acquire", 0) - aie.dma_bd(%buf261_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l261_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_260 = aie.external_buffer {sym_name = "buffer_out_260" } : memref<7168xi32> - %dma260 = aie.shim_dma(%t260) { - %lock1 = aie.lock(%t260, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_260 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - - %t270 = aie.tile(27, 0) - %t271 = aie.tile(27, 1) - - %sw27 = aie.switchbox(%t270) { - aie.connect<"South" : 3, "North" : 3> - } - %mux27 = aie.shim_mux(%t270) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma27 = aie.switchbox(%t271) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf271_0 = aie.buffer(%t271) {sym_name = "buf271_0" } : memref<7168xi32> - %l271_0 = aie.lock(%t271, 0) - - %m271 = aie.mem(%t271) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l271_0, "Acquire", 0) - aie.dma_bd(%buf271_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l271_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_270 = aie.external_buffer {sym_name = "buffer_out_270" } : memref<7168xi32> - %dma270 = aie.shim_dma(%t270) { - %lock1 = aie.lock(%t270, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_270 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t340 = aie.tile(34, 0) - %t341 = aie.tile(34, 1) - - %sw34 = aie.switchbox(%t340) { - aie.connect<"South" : 3, "North" : 3> - } - %mux34 = aie.shim_mux(%t340) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma34 = aie.switchbox(%t341) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf341_0 = aie.buffer(%t341) {sym_name = "buf341_0" } : memref<7168xi32> - %l341_0 = aie.lock(%t341, 0) - - %m341 = aie.mem(%t341) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l341_0, "Acquire", 0) - aie.dma_bd(%buf341_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l341_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_340 = aie.external_buffer {sym_name = "buffer_out_340" } : memref<7168xi32> - %dma340 = aie.shim_dma(%t340) { - %lock1 = aie.lock(%t340, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_340 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t350 = aie.tile(35, 0) - %t351 = aie.tile(35, 1) - - %sw35 = aie.switchbox(%t350) { - aie.connect<"South" : 3, "North" : 3> - } - %mux35 = aie.shim_mux(%t350) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma35 = aie.switchbox(%t351) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf351_0 = aie.buffer(%t351) {sym_name = "buf351_0" } : memref<7168xi32> - %l351_0 = aie.lock(%t351, 0) - - %m351 = aie.mem(%t351) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l351_0, "Acquire", 0) - aie.dma_bd(%buf351_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l351_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_350 = aie.external_buffer {sym_name = "buffer_out_350" } : memref<7168xi32> - %dma350 = aie.shim_dma(%t350) { - %lock1 = aie.lock(%t350, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_350 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - - %t420 = aie.tile(42, 0) - %t421 = aie.tile(42, 1) - - %sw42 = aie.switchbox(%t420) { - aie.connect<"South" : 3, "North" : 3> - } - - %buf421_0 = aie.buffer(%t421) {sym_name = "buf421_0" } : memref<7168xi32> - %l421 = aie.lock(%t421, 1) - %m421 = aie.mem(%t421) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l421, "Acquire", 0) - aie.dma_bd(%buf421_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l421, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_420 = aie.external_buffer {sym_name = "buffer_out_420" } : memref<7168xi32> - %lock1 = aie.lock(%t420, 1) - %dma420 = aie.shim_dma(%t420) { - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer_out_420 : memref<7168xi32>, 0, 7168) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - %t430 = aie.tile(43, 0) - %t431 = aie.tile(43, 1) - - %sw43 = aie.switchbox(%t430) { - aie.connect<"South" : 3, "North" : 3> - } - %mux43 = aie.shim_mux(%t430) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma43 = aie.switchbox(%t431) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf431_0 = aie.buffer(%t431) {sym_name = "buf431_0" } : memref<7168xi32> - %l431_0 = aie.lock(%t431, 0) - - %m431 = aie.mem(%t431) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l431_0, "Acquire", 0) - aie.dma_bd(%buf431_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l431_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_430 = aie.external_buffer {sym_name = "buffer_out_430" } : memref<7168xi32> - %l430 = aie.lock(%t430, 1) - %dma430 = aie.shim_dma(%t430) { - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%l430, Acquire, 1) - aie.dma_bd(%buffer_out_430 : memref<7168xi32>, 0, 7168) - aie.use_lock(%l430, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - - %t460 = aie.tile(46, 0) - %t461 = aie.tile(46, 1) - - %sw46 = aie.switchbox(%t460) { - aie.connect<"South" : 3, "North" : 3> - } - %mux46 = aie.shim_mux(%t460) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma46 = aie.switchbox(%t461) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf461_0 = aie.buffer(%t461) {sym_name = "buf461_0" } : memref<7168xi32> - %l461_0 = aie.lock(%t461, 0) - - %m461 = aie.mem(%t461) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l461_0, "Acquire", 0) - aie.dma_bd(%buf461_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l461_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - %buffer_out_460 = aie.external_buffer {sym_name = "buffer_out_460" } : memref<7168xi32> - %l460 = aie.lock(%t460, 1) - %dma460 = aie.shim_dma(%t460) { - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%l460, Acquire, 1) - aie.dma_bd(%buffer_out_460 : memref<7168xi32>, 0, 7168) - aie.use_lock(%l460, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - - %t470 = aie.tile(47, 0) - %t471 = aie.tile(47, 1) - - %sw47 = aie.switchbox(%t470) { - aie.connect<"South" : 3, "North" : 3> - } - %mux47 = aie.shim_mux(%t470) { - aie.connect<"DMA" : 0, "North": 3> - } - - %swdma47 = aie.switchbox(%t471) { - aie.connect<"South" : 3, "DMA" : 0> - } - - %buf471_0 = aie.buffer(%t471) {sym_name = "buf471_0" } : memref<7168xi32> - %l471_0 = aie.lock(%t471, 0) - - %m471 = aie.mem(%t471) { - %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l471_0, "Acquire", 0) - aie.dma_bd(%buf471_0 : memref< 7168xi32>, 0, 7168) - aie.use_lock(%l471_0, "Release", 1) - aie.next_bd ^end - ^end: - aie.end - } - - - %buffer_out_470 = aie.external_buffer {sym_name = "buffer_out_470" } : memref<7168xi32> - %l470 = aie.lock(%t470, 1) - %dma470 = aie.shim_dma(%t470) { + % t20 = aie.tile(2, 0) % t21 = aie.tile(2, 1) + + % sw2 = aie.switchbox(% t20){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux2 = aie.shim_mux(% t20){aie.connect < "DMA" : 0, "North" : 3 > } + + % swdma2 = aie.switchbox( + % t21){aie.connect < "South" : 3, "DMA" : 0 > } + + % buf21_0 = aie.buffer(% t21){sym_name = "buf21_0"} + : memref<7168xi32> % l21_0 = aie.lock(% t21, 0) + + % m21 = aie.mem(% t21){ + % srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^ + bd0 : aie.use_lock(% l21_0, "Acquire", 0) + aie.dma_bd(% buf21_0 + : memref<7168xi32>, 0, 7168) + aie.use_lock(% l21_0, "Release", 1) aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_20 = + aie.external_buffer{ + sym_name = "buffer_out_20"} + : memref<7168xi32> % l20 = aie.lock(% t20, 1) % dma20 = + aie.shim_dma(% t20){ + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^ + bd0 : aie.use_lock(% l20, Acquire, 1) + aie.dma_bd(% buffer_out_20 + : memref<7168xi32>, 0, + 7168) + aie.use_lock(% l20, Release, 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t30 = aie.tile(3, 0) % + t31 = aie.tile(3, 1) + + % sw3 = aie.switchbox(% t30){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux3 = aie.shim_mux(% t30){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma3 = + aie.switchbox(% t31){ + aie.connect < "South" : 3, + "DMA" : 0 > + } + + % buf31_0 = + aie.buffer(% t31){ + sym_name = + "buf31_0"} + : memref<7168xi32> % l31_0 = aie.lock(% t31, 0) + + % m31 = + aie.mem(% t31){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l31_0, + "Acquire", 0) + aie.dma_bd( + % buf31_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% l31_0, + "Release", + 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_30 = + aie.external_buffer{ + sym_name = "buffer_out_30"} + : memref<7168xi32> % dma30 = aie.shim_dma(% t30){ + % lock1 = + aie.lock(% t30, 1) + + aie.dma_start(MM2S, 0, + ^bd0, ^end) + + ^ + bd0 : aie + .use_lock(% lock1, Acquire, + 1) aie + .dma_bd(% buffer_out_30 + : memref<7168xi32>, + 0, 7168) aie + .use_lock(% lock1, Release, + 0) aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t60 = aie.tile(6, 0) % + t61 = aie.tile(6, 1) + + % sw6 = aie.switchbox(% t60){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux6 = aie.shim_mux(% t60){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma6 = + aie.switchbox(% t61){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf61_0 = + aie.buffer(% t61){ + sym_name = + "buf61_0"} + : memref<7168xi32> % l61_0 = aie.lock(% t61, 0) + + % m61 = + aie.mem(% t61){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l61_0, + "Acquire", 0) + aie.dma_bd( + % buf61_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% l61_0, + "Release", + 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_60 = + aie.external_buffer{ + sym_name = "buffer_out_60"} + : memref< + 7168xi32> % dma60 = aie + .shim_dma(% t60){ + % lock1 = + aie.lock(% t60, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^ + bd0 : aie + .use_lock(% lock1, Acquire, 1) aie + .dma_bd(% buffer_out_60 + : memref<7168xi32>, 0, + 7168) aie + .use_lock(% lock1, Release, + 0) aie.next_bd ^ + bd0 ^ + end : aie.end + } + + % t70 = + aie.tile(7, 0) % t71 = aie.tile(7, 1) + + % + sw = aie.switchbox(% + t70){ + aie.connect < + "South" : 3, + "North" : 3 > + } % mux = aie.shim_mux(% t70){ + aie.connect < "DMA" : + 0, + "North" : 3 > + } + + % + swdma = + aie.switchbox(% t71){ + aie.connect < "South" : 3, + "DMA" : 0 > + } + + % buf71_0 = + aie.buffer(% t71){ + sym_name = + "buf71_0"} : memref<7168xi32> + + % l71_0 = + aie.lock(% t71, 0) + + % + m71 = aie.mem(% t71){ + % srcDma = + aie.dma_start( + S2MM, 0, + ^bd0, + ^end) ^ + bd0 : aie + .use_lock( + % l71_0, + "Acquir" + "e", + 0) aie + .dma_bd( + % buf71_0 + : memref< + 7168xi32>, + 0, + 7168) + aie + .use_lock( + % l71_0, + "Releas" + "e", + 1) aie + .next_bd ^ + end ^ + end : aie.end + } + + % + buffer_out_70 = + aie.external_buffer{ + sym_name = + "bu" + "ff" + "er" + "_o" + "ut" + "_7" + "0"} + : memref<7168xi32> % dma70 = aie + .shim_dma(% t70){ + % lock1 = + aie.lock(% t70, 1) + + aie.dma_start(MM2S, 0, ^bd0, + ^end) + + ^ + bd0 : + aie.use_lock( + % lock1, Acquire, 1) + aie.dma_bd( + % buffer_out_70 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t100 = + aie.tile(10, 0) % t101 = + aie.tile(10, 1) + + % sw10 = + aie.switchbox(% t100){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux10 = + aie.shim_mux(% t100){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma10 = + aie.switchbox(% t101){ + aie.connect < "South" : + 3, + "DMA" : 0 > + } + + % buf101_0 = + aie.buffer(% t101){ + sym_name = + "buf101_0"} + : memref<7168xi32> + + % l101_0 = + aie.lock(% t101, + 0) + + % + m101 = aie.mem( + % + t101){ + % srcDma = + aie.dma_start( + S2MM, + 0, + ^bd0, + ^end) ^ + bd0 : aie + .use_lock( + % l101_0, + "A" + "c" + "q" + "u" + "i" + "r" + "e", + 0) + aie + .dma_bd( + % buf101_0 + : memref< + 7168xi32>, + 0, + 7168) + aie + .use_lock( + % l101_0, + "R" + "e" + "l" + "e" + "a" + "s" + "e", + 1) + aie + .next_bd ^ + end ^ + end : + aie.end + } + + % + buffer_out_100 = + aie.external_buffer{ + sym_name = + "buffer_out_100"} + : memref<7168xi32> % dma100 = aie + .shim_dma(% t100){ + % lock1 = + aie.lock(% t100, 1) + + aie.dma_start(MM2S, 0, ^bd0, + ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_100 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t110 = + aie.tile(11, 0) % t111 = + aie.tile(11, 1) + + % sw11 = + aie.switchbox(% t110){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux11 = + aie.shim_mux(% t110){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma11 = + aie.switchbox(% t111){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf111_0 = + aie.buffer(% t111){ + sym_name = + "buf111_0"} + : memref<7168xi32> % l111_0 = aie.lock(% t111, 0) + + % m111 = + aie.mem(% t111){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l111_0, + "Acquire", 0) + aie.dma_bd( + % buf111_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l111_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_110 = + aie.external_buffer{ + sym_name = "buffer_out_110"} + : memref<7168xi32> % dma110 = aie + .shim_dma(% t110){ + % lock1 = + aie.lock(% t110, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_110 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t180 = + aie.tile(18, 0) % t181 = + aie.tile(18, 1) + + % sw18 = + aie.switchbox(% t180){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux18 = + aie.shim_mux(% t180){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma18 = + aie.switchbox(% t181){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf181_0 = + aie.buffer(% t181){ + sym_name = + "buf181_0"} + : memref<7168xi32> % l181_0 = aie.lock(% t181, 0) + + % m181 = + aie.mem(% t181){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l181_0, + "Acquire", 0) + aie.dma_bd( + % buf181_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l181_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_180 = + aie.external_buffer{ + sym_name = "buffer_out_180"} + : memref<7168xi32> % dma180 = aie + .shim_dma(% t180){ + % lock1 = + aie.lock(% t180, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_180 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t190 = + aie.tile(19, 0) % t191 = + aie.tile(19, 1) + + % sw19 = + aie.switchbox(% t190){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux19 = + aie.shim_mux(% t190){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma19 = + aie.switchbox(% t191){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf191_0 = + aie.buffer(% t191){ + sym_name = + "buf191_0"} + : memref<7168xi32> % l191_0 = aie.lock(% t191, 0) + + % m191 = + aie.mem(% t191){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l191_0, + "Acquire", 0) + aie.dma_bd( + % buf191_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l191_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_190 = + aie.external_buffer{ + sym_name = "buffer_out_190"} + : memref<7168xi32> % dma190 = aie + .shim_dma(% t190){ + % lock1 = + aie.lock(% t190, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_190 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t260 = + aie.tile(26, 0) % t261 = + aie.tile(26, 1) + + % sw26 = + aie.switchbox(% t260){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux26 = + aie.shim_mux(% t260){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma26 = + aie.switchbox(% t261){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf261_0 = + aie.buffer(% t261){ + sym_name = + "buf261_0"} + : memref<7168xi32> % l261_0 = aie.lock(% t261, 0) + + % m261 = + aie.mem(% t261){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l261_0, + "Acquire", 0) + aie.dma_bd( + % buf261_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l261_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_260 = + aie.external_buffer{ + sym_name = "buffer_out_260"} + : memref<7168xi32> % dma260 = aie + .shim_dma(% t260){ + % lock1 = + aie.lock(% t260, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_260 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t270 = + aie.tile(27, 0) % t271 = + aie.tile(27, 1) + + % sw27 = + aie.switchbox(% t270){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux27 = + aie.shim_mux(% t270){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma27 = + aie.switchbox(% t271){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf271_0 = + aie.buffer(% t271){ + sym_name = + "buf271_0"} + : memref<7168xi32> % l271_0 = aie.lock(% t271, 0) + + % m271 = + aie.mem(% t271){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l271_0, + "Acquire", 0) + aie.dma_bd( + % buf271_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l271_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_270 = + aie.external_buffer{ + sym_name = "buffer_out_270"} + : memref<7168xi32> % dma270 = aie + .shim_dma(% t270){ + % lock1 = + aie.lock(% t270, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_270 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t340 = + aie.tile(34, 0) % t341 = + aie.tile(34, 1) + + % sw34 = + aie.switchbox(% t340){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux34 = + aie.shim_mux(% t340){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma34 = + aie.switchbox(% t341){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf341_0 = + aie.buffer(% t341){ + sym_name = + "buf341_0"} + : memref<7168xi32> % l341_0 = aie.lock(% t341, 0) + + % m341 = + aie.mem(% t341){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l341_0, + "Acquire", 0) + aie.dma_bd( + % buf341_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l341_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_340 = + aie.external_buffer{ + sym_name = "buffer_out_340"} + : memref<7168xi32> % dma340 = aie + .shim_dma(% t340){ + % lock1 = + aie.lock(% t340, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_340 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t350 = + aie.tile(35, 0) % t351 = + aie.tile(35, 1) + + % sw35 = + aie.switchbox(% t350){ + aie.connect < "South" : 3, + "North" : 3 > + } % + mux35 = + aie.shim_mux(% t350){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma35 = + aie.switchbox(% t351){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf351_0 = + aie.buffer(% t351){ + sym_name = + "buf351_0"} + : memref<7168xi32> % l351_0 = aie.lock(% t351, 0) + + % m351 = + aie.mem(% t351){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l351_0, + "Acquire", 0) + aie.dma_bd( + % buf351_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l351_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_350 = + aie.external_buffer{ + sym_name = "buffer_out_350"} + : memref<7168xi32> % dma350 = aie + .shim_dma(% t350){ + % lock1 = + aie.lock(% t350, 1) + + aie.dma_start( + MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, + 1) + aie.dma_bd( + % buffer_out_350 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, + 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % t420 = + aie.tile(42, 0) % t421 = + aie.tile(42, 1) + + % sw42 = + aie.switchbox(% t420){ + aie.connect < "South" : 3, + "North" : 3 > + } + + % buf421_0 = + aie.buffer(% t421){ + sym_name = "buf421_0"} + : memref<7168xi32> % l421 = aie.lock(% t421, 1) % m421 = + aie.mem(% t421){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, ^end) ^ + bd0 : + aie.use_lock(% l421, "Acquire", + 0) + aie.dma_bd( + % buf421_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% l421, + "Release", + 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_420 = + aie.external_buffer{ + sym_name = "buffer_out_420"} + : memref<7168xi32> % lock1 = aie.lock(% t420, 1) % dma420 = + aie.shim_dma(% t420){ + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% lock1, Acquire, 1) + aie.dma_bd(% buffer_out_420 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% lock1, + Release, 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % + t430 = aie.tile(43, 0) % + t431 = aie.tile(43, 1) + + % + sw43 = aie.switchbox(% + t430){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux43 = aie.shim_mux(% t430){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma43 = + aie.switchbox(% t431){ + aie.connect < "South" : + 3, + "DMA" : 0 > + } + + % buf431_0 = + aie.buffer(% t431){ + sym_name = + "buf431_0"} + : memref<7168xi32> % l431_0 = aie.lock(% t431, 0) + + % m431 = + aie.mem(% t431){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l431_0, + "Acquire", 0) + aie.dma_bd( + % buf431_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l431_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_430 = + aie.external_buffer{ + sym_name = "buffer_out_430"} + : memref<7168xi32> % l430 = aie.lock(% t430, 1) % dma430 = + aie.shim_dma(% t430){ + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% l430, Acquire, 1) + aie.dma_bd(% buffer_out_430 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% l430, + Release, 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % + t460 = aie.tile(46, 0) % + t461 = aie.tile(46, 1) + + % + sw46 = aie.switchbox(% + t460){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux46 = aie.shim_mux(% t460){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma46 = + aie.switchbox(% t461){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf461_0 = + aie.buffer(% t461){ + sym_name = + "buf461_0"} + : memref<7168xi32> % l461_0 = aie.lock(% t461, 0) + + % m461 = + aie.mem(% t461){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l461_0, + "Acquire", 0) + aie.dma_bd( + % buf461_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l461_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_460 = + aie.external_buffer{ + sym_name = "buffer_out_460"} + : memref<7168xi32> % l460 = aie.lock(% t460, 1) % dma460 = + aie.shim_dma(% t460){ + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^ + bd0 : + aie.use_lock(% l460, Acquire, 1) + aie.dma_bd(% buffer_out_460 + : memref<7168xi32>, + 0, 7168) + aie.use_lock(% l460, + Release, 0) + aie.next_bd ^ + bd0 ^ end : aie.end + } + + % + t470 = aie.tile(47, 0) % + t471 = aie.tile(47, 1) + + % + sw47 = aie.switchbox(% + t470){ + aie.connect < "South" : 3, + "North" : 3 > + } % mux47 = aie.shim_mux(% t470){ + aie.connect < "DMA" : 0, + "North" : 3 > + } + + % swdma47 = + aie.switchbox(% t471){ + aie.connect < + "South" : 3, + "DMA" : 0 > + } + + % buf471_0 = + aie.buffer(% t471){ + sym_name = + "buf471_0"} + : memref<7168xi32> % l471_0 = aie.lock(% t471, 0) + + % m471 = + aie.mem(% t471){ + % srcDma = + aie.dma_start(S2MM, 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l471_0, + "Acquire", 0) + aie.dma_bd( + % buf471_0 + : memref<7168xi32>, + 0, 7168) + aie.use_lock( + % l471_0, + "Release", 1) + aie.next_bd ^ + end ^ end : aie.end + } + + % buffer_out_470 = + aie.external_buffer{ + sym_name = "buffer_out_470"} + : memref<7168xi32> % l470 = aie.lock(% t470, 1) % dma470 = + aie.shim_dma(% t470) { aie.dma_start(MM2S, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l470, Acquire, 1) - aie.dma_bd(%buffer_out_470 : memref<7168xi32>, 0, 7168) - aie.use_lock(%l470, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end + ^ bd0 : aie.use_lock(% l470, Acquire, 1) + aie.dma_bd(% buffer_out_470 + : memref<7168xi32>, 0, 7168) + aie.use_lock(% l470, Release, 0) aie.next_bd ^ + bd0 ^ end : aie.end } } diff --git a/test/generate-mmap/allocation_error.mlir b/test/generate-mmap/allocation_error.mlir index 1725cfb7a4..312cdc8155 100644 --- a/test/generate-mmap/allocation_error.mlir +++ b/test/generate-mmap/allocation_error.mlir @@ -9,34 +9,39 @@ //===----------------------------------------------------------------------===// // REQUIRES: peano -// RUN: not aiecc.py --alloc-scheme=basic-sequential --no-xchesscc --no-xbridge %s 2>&1 | FileCheck %s --check-prefix=PEANO -// PEANO: ld.lld: error: section '.bss' will not fit in region 'data': overflowed by 4 bytes +// RUN: not aiecc.py --alloc-scheme=basic-sequential --no-xchesscc --no-xbridge +// %s 2>&1 | FileCheck %s --check-prefix=PEANO PEANO: ld.lld: error: section +// '.bss' will not fit in region 'data': overflowed by 4 bytes -// If we use all of the local memory, then linking the AIE executable should fail. -// The fundamental problem here is that we can stuff things in the executable that -// aren't visibla at the MLIR level, so the assign-buffer-addresses pass can't generate -// a good error message. +// If we use all of the local memory, then linking the AIE executable should +// fail. The fundamental problem here is that we can stuff things in the +// executable that aren't visibla at the MLIR level, so the +// assign-buffer-addresses pass can't generate a good error message. module @example0 { - aie.device(xcvc1902) { - memref.global @x : memref<4xi8> = uninitialized - func.func @test (%i: index, %v: i8) -> i8 { - %x = memref.get_global @x : memref<4xi8> - memref.store %v, %x[%i] : memref<4xi8> - %r = memref.load %x[%i] : memref<4xi8> - func.return %r : i8 - } + aie.device(xcvc1902) { + memref.global @x : memref<4xi8> = + uninitialized func.func @test(% i + : index, % v + : i8) + ->i8 { + % x = memref.get_global @x : memref<4xi8> memref.store % v, + % x[% i] : memref<4xi8> % r = + memref.load % x[% i] : memref<4xi8> func.return % r : i8 + } - %t33 = aie.tile(3, 3) + % t33 = aie.tile(3, 3) - // Use all the local memory for buffers, combined with the 1024 byte stack size. - %buf33 = aie.buffer(%t33) : memref<31744xi8> + // Use all the local memory for buffers, combined with the 1024 byte + // stack size. + % buf33 = aie.buffer(% t33) + : memref<31744xi8> - %c33 = aie.core(%t33) { - %idx1 = arith.constant 3 : index - %val1 = arith.constant 7 : i8 - memref.store %val1, %buf33[%idx1] : memref<31744xi8> - func.call @test(%idx1, %val1) : (index, i8) -> i8 - aie.end + % c33 = aie.core(% t33) { + % idx1 = arith.constant 3 : index % val1 = + arith.constant 7 : i8 memref.store % val1, + % buf33[% idx1] : memref<31744xi8> + func.call @test(% idx1, % val1) + : (index, i8)->i8 aie.end + } } - } } diff --git a/test/generate-mmap/allocation_error_chess.mlir b/test/generate-mmap/allocation_error_chess.mlir index bd7139177b..65f90dfdb5 100644 --- a/test/generate-mmap/allocation_error_chess.mlir +++ b/test/generate-mmap/allocation_error_chess.mlir @@ -9,34 +9,39 @@ //===----------------------------------------------------------------------===// // REQUIRES: chess -// RUN: not aiecc.py --alloc-scheme=basic-sequential --xchesscc --xbridge %s 2>&1 | FileCheck %s --check-prefix=CHESS -// CHESS: Error: could not find free space for SpaceSymbol x in memory DMb +// RUN: not aiecc.py --alloc-scheme=basic-sequential --xchesscc --xbridge %s +// 2>&1 | FileCheck %s --check-prefix=CHESS CHESS: Error: could not find free +// space for SpaceSymbol x in memory DMb -// If we use all of the local memory, then linking the AIE executable should fail. -// The fundamental problem here is that we can stuff things in the executable that -// aren't visibla at the MLIR level, so the assign-buffer-addresses pass can't generate -// a good error message. +// If we use all of the local memory, then linking the AIE executable should +// fail. The fundamental problem here is that we can stuff things in the +// executable that aren't visibla at the MLIR level, so the +// assign-buffer-addresses pass can't generate a good error message. module @example0 { - aie.device(xcvc1902) { - memref.global @x : memref<4xi8> = uninitialized - func.func @test (%i: index, %v: i8) -> i8 { - %x = memref.get_global @x : memref<4xi8> - memref.store %v, %x[%i] : memref<4xi8> - %r = memref.load %x[%i] : memref<4xi8> - func.return %r : i8 - } + aie.device(xcvc1902) { + memref.global @x : memref<4xi8> = + uninitialized func.func @test(% i + : index, % v + : i8) + ->i8 { + % x = memref.get_global @x : memref<4xi8> memref.store % v, + % x[% i] : memref<4xi8> % r = + memref.load % x[% i] : memref<4xi8> func.return % r : i8 + } - %t33 = aie.tile(3, 3) + % t33 = aie.tile(3, 3) - // Use all the local memory for buffers, combined with the 1024 byte stack size. - %buf33 = aie.buffer(%t33) : memref<31744xi8> + // Use all the local memory for buffers, combined with the 1024 byte + // stack size. + % buf33 = aie.buffer(% t33) + : memref<31744xi8> - %c33 = aie.core(%t33) { - %idx1 = arith.constant 3 : index - %val1 = arith.constant 7 : i8 - memref.store %val1, %buf33[%idx1] : memref<31744xi8> - func.call @test(%idx1, %val1) : (index, i8) -> i8 - aie.end + % c33 = aie.core(% t33) { + % idx1 = arith.constant 3 : index % val1 = + arith.constant 7 : i8 memref.store % val1, + % buf33[% idx1] : memref<31744xi8> + func.call @test(% idx1, % val1) + : (index, i8)->i8 aie.end + } } - } } diff --git a/test/npu-xrt/add_one_using_dma/run.lit b/test/npu-xrt/add_one_using_dma/run.lit index a3ce61f18b..99c117ab87 100644 --- a/test/npu-xrt/add_one_using_dma/run.lit +++ b/test/npu-xrt/add_one_using_dma/run.lit @@ -3,8 +3,9 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir -// RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem -// RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s -// CHECK: PASS! - +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu +// --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin +// --npu-insts-name=insts.txt %S/aie.mlir RUN: clang %S/test.cpp -o test.exe +// -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options +// -lboost_filesystem RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i +// insts.txt | FileCheck %s CHECK: PASS! diff --git a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir index f647e844c3..b473b2e66b 100644 --- a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir +++ b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir @@ -8,50 +8,53 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf -// RUN: %run_on_vck5000 ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential +// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s +// -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% +// -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf RUN: +// %run_on_vck5000 ./test.elf module @test18_simple_shim_dma_routed { - %t70 = aie.tile(7, 0) - %t72 = aie.tile(7, 2) - - %buffer = aie.external_buffer {sym_name = "input_buffer" } : memref<512 x i32> - %lock1 = aie.lock(%t70, 1) {sym_name = "input_lock" } - - %dma = aie.shim_dma(%t70) { - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } - - aie.flow(%t70, "DMA" : 0, %t72, "DMA" : 0) - - %buf72_0 = aie.buffer(%t72) {sym_name = "buf72_0" } : memref<256xi32> - %buf72_1 = aie.buffer(%t72) {sym_name = "buf72_1" } : memref<256xi32> - - %l72_0 = aie.lock(%t72, 0) - %l72_1 = aie.lock(%t72, 1) - - %m72 = aie.mem(%t72) { - %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l72_0, "Acquire", 0) - aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) - aie.use_lock(%l72_0, "Release", 1) - aie.next_bd ^bd1 - ^bd1: - aie.use_lock(%l72_1, "Acquire", 0) - aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) - aie.use_lock(%l72_1, "Release", 1) - aie.next_bd ^bd0 - ^end: - aie.end + % t70 = aie.tile(7, 0) % t72 = + aie.tile(7, 2) + + % buffer = + aie.external_buffer{sym_name = "input_buffer"} + : memref<512 x i32> % + lock1 = aie.lock(% t70, 1){sym_name = "input_lock"} + + % dma = aie.shim_dma(% t70){ + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^ bd0 : aie.use_lock(% lock1, Acquire, 1) + aie.dma_bd(% buffer + : memref<512 x i32>, 0, 512) + aie.use_lock(% lock1, Release, 0) aie.next_bd ^ + bd0 ^ end : aie.end + } + + aie.flow(% t70, "DMA" : 0, % t72, "DMA" : 0) + + % buf72_0 = + aie.buffer(% t72){sym_name = "buf72_0"} + : memref<256xi32> % buf72_1 = aie.buffer(% t72){sym_name = "buf72_1"} + : memref<256xi32> + + % l72_0 = aie.lock(% t72, 0) % l72_1 = + aie.lock(% t72, 1) + + % m72 = aie.mem(% t72) { + % srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^ + bd0 : aie.use_lock(% l72_0, "Acquire", 0) + aie.dma_bd(% buf72_0 + : memref<256xi32>, 0, 256) + aie.use_lock(% l72_0, "Release", 1) aie.next_bd ^ + bd1 ^ + bd1 : aie.use_lock(% l72_1, "Acquire", 0) + aie.dma_bd(% buf72_1 + : memref<256xi32>, 0, 256) + aie.use_lock(% l72_1, "Release", 1) aie.next_bd ^ + bd0 ^ end : aie.end } } diff --git a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir index 14c84504f5..0ea82afa51 100644 --- a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir +++ b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir @@ -8,74 +8,99 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf -// RUN: %run_on_vck5000 ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential +// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s +// -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% +// -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf RUN: +// %run_on_vck5000 ./test.elf module @test20_shim_dma_broadcast { - %t70 = aie.tile(7, 0) - %t72 = aie.tile(7, 2) - %t73 = aie.tile(7, 3) + % t70 = aie.tile(7, 0) % t72 = + aie.tile(7, 2) % t73 = + aie.tile(7, 3) - %buffer = aie.external_buffer {sym_name = "input_buffer" } : memref<512 x i32> - %lock1 = aie.lock(%t70, 1) {sym_name = "input_lock" } + % buffer = aie.external_buffer{sym_name = "input_buffer"} + : memref<512 x i32> % lock1 = aie.lock(% t70, 1){sym_name = "input_lock"} - %dma = aie.shim_dma(%t70) { - aie.dma_start(MM2S, 0, ^bd0, ^end) + % dma = aie.shim_dma(% t70){ + aie.dma_start(MM2S, 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%lock1, Acquire, 1) - aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) - aie.use_lock(%lock1, Release, 0) - aie.next_bd ^bd0 - ^end: - aie.end - } + ^ bd0 : aie.use_lock(% lock1, Acquire, 1) + aie.dma_bd(% buffer + : memref<512 x i32>, 0, 512) + aie.use_lock(% lock1, Release, 0) aie.next_bd ^ + bd0 ^ end : aie.end + } - aie.flow(%t70, "DMA" : 0, %t72, "DMA" : 0) + aie.flow(% t70, "DMA" : 0, % t72, + "DMA" : 0) - %buf72_0 = aie.buffer(%t72) {sym_name = "buf72_0" } : memref<256xi32> - %buf72_1 = aie.buffer(%t72) {sym_name = "buf72_1" } : memref<256xi32> + % buf72_0 = + aie.buffer(% t72){sym_name = + "buf72_0"} + : memref<256xi32> % buf72_1 = aie.buffer(% t72){sym_name = "buf72_1"} + : memref<256xi32> - %l72_0 = aie.lock(%t72, 0) - %l72_1 = aie.lock(%t72, 1) + % l72_0 = + aie.lock(% t72, 0) % l72_1 = + aie.lock(% t72, 1) - %m72 = aie.mem(%t72) { - %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l72_0, "Acquire", 0) - aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) - aie.use_lock(%l72_0, "Release", 1) - aie.next_bd ^bd1 - ^bd1: - aie.use_lock(%l72_1, "Acquire", 0) - aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) - aie.use_lock(%l72_1, "Release", 1) - aie.next_bd ^bd0 - ^end: - aie.end - } + % m72 = aie.mem(% t72){ + % srcDma = + aie.dma_start("S2MM", 0, ^bd0, + ^end) ^ + bd0 : + aie.use_lock(% l72_0, + "Acquire", + 0) aie + .dma_bd( + % buf72_0 + : memref<256xi32>, + 0, 256) aie + .use_lock(% l72_0, + "Release", + 1) + aie.next_bd ^ + bd1 ^ + bd1 : + aie.use_lock(% l72_1, + "Acquire", + 0) aie + .dma_bd( + % buf72_1 + : memref<256xi32>, + 0, 256) aie + .use_lock(% l72_1, + "Release", + 1) + aie.next_bd ^ + bd0 ^ end : aie.end + } - aie.flow(%t70, "DMA" : 0, %t73, "DMA" : 0) + aie.flow(% t70, "DMA" : 0, + % t73, "DMA" : 0) - %buf73_0 = aie.buffer(%t73) {sym_name = "buf73_0" } : memref<256xi32> - %buf73_1 = aie.buffer(%t73) {sym_name = "buf73_1" } : memref<256xi32> + % buf73_0 = + aie.buffer(% t73){ + sym_name = + "buf73_0"} + : memref<256xi32> % buf73_1 = aie.buffer(% t73){sym_name = "buf73_1"} + : memref<256xi32> - %l73_0 = aie.lock(%t73, 0) - %l73_1 = aie.lock(%t73, 1) + % l73_0 = aie.lock(% t73, 0) % l73_1 = + aie.lock(% t73, 1) - %m73 = aie.mem(%t73) { - %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) - ^bd0: - aie.use_lock(%l73_0, "Acquire", 0) - aie.dma_bd(%buf73_0 : memref<256xi32>, 0, 256) - aie.use_lock(%l73_0, "Release", 1) - aie.next_bd ^bd1 - ^bd1: - aie.use_lock(%l73_1, "Acquire", 0) - aie.dma_bd(%buf73_1 : memref<256xi32>, 0, 256) - aie.use_lock(%l73_1, "Release", 1) - aie.next_bd ^bd0 - ^end: - aie.end + % m73 = aie.mem(% t73) { + % srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^ + bd0 : aie.use_lock(% l73_0, "Acquire", 0) + aie.dma_bd(% buf73_0 + : memref<256xi32>, 0, 256) + aie.use_lock(% l73_0, "Release", 1) aie.next_bd ^ + bd1 ^ + bd1 : aie.use_lock(% l73_1, "Acquire", 0) + aie.dma_bd(% buf73_1 + : memref<256xi32>, 0, 256) + aie.use_lock(% l73_1, "Release", 1) aie.next_bd ^ + bd0 ^ end : aie.end } } From b5eef3ab3c36af607487ae9dc2e3bfe8a576da52 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 16:45:26 -0600 Subject: [PATCH 23/49] Check Message --- .../bank_aware_alloc_error.mlir | 54 +++++++++--------- .../bank_aware_alloc_memtile_error.mlir | 55 ++++++++++--------- .../bank_aware_alloc_memtile_simple.mlir | 39 ++++--------- .../bank_aware_alloc_simple.mlir | 37 +++++++------ 4 files changed, 86 insertions(+), 99 deletions(-) diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index 6106c7e82c..d05b49aadd 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -8,32 +8,36 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s -// 2>&1 | FileCheck %s CHECK: error: Failed to allocate buffer: "b" with size: -// 32768 bytes. CHECK: %1 = aie.buffer(%0) { sym_name = "b" } : -// memref<8192xi32> CHECK: ^ CHECK: note: see current operation: %2 -// = "aie.buffer"(%0) <{sym_name = "b"}> : (index) -> memref<8192xi32> CHECK: -// error: 'aie.tile' op All requested buffers doesn't fit in the available -// memory: Bank aware +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "b" with size: 32768 bytes. +// CHECK: %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> +// CHECK: ^ +// CHECK: note: see current operation: %2 = "aie.buffer"(%0) <{sym_name = "b"}> : (index) -> memref<8192xi32> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware -// CHECK: %0 = aie.tile(3, 3) -// CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row -// = 3 : i32}> : () -> index CHECK: note: Current configuration of buffers in -// bank(s) : MemoryMap: CHECK: (stack) : 0x0-0x3FF -// (1024 bytes) CHECK: bank : 0 0x0-0x1FFF CHECK: bank : 1 -// 0x2000-0x3FFF CHECK: bank : 2 0x4000-0x5FFF CHECK: bank : 3 -// 0x6000-0x7FFF +// CHECK: %0 = aie.tile(3, 3) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row = 3 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (stack) : 0x0-0x3FF (1024 bytes) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: bank : 3 0x6000-0x7FFF module @test { - aie.device(xcvc1902) { - % 0 = aie.tile(3, 3) % b1 = - aie.buffer(% 0){sym_name = "a"} : memref<16xi8> % 1 = - aie.buffer(% 0){sym_name = "b"} : memref<8192xi32> % b2 = - aie.buffer(% 0){sym_name = "c"} : memref<16xi16> % 3 = - aie.tile(4, 4) % 4 = aie.buffer(% 3) - : memref<500xi32> aie.core(% 0){aie.end} aie.core(% 3) { - aie.end - } + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end } -} + aie.core(%3) { + aie.end + } + } +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index 7e66b2d701..694844dded 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -1,5 +1,4 @@ -//===- memtile_error.mlir ---------------------------------------*- MLIR -//-*-===// +//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -9,32 +8,34 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s -// 2>&1 | FileCheck %s CHECK: error: Failed to allocate buffer: "a" with size: -// 528000 bytes. CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : -// memref<132000xi32> CHECK: ^ CHECK: note: see current operation: -// %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<132000xi32> -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the -// available memory: Bank aware +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "a" with size: 528000 bytes. +// CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> +// CHECK: ^ +// CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<132000xi32> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware + +// CHECK: %0 = aie.tile(3, 1) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row = 1 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0xFFFF +// CHECK: bank : 1 0x10000-0x1FFFF +// CHECK: bank : 2 0x20000-0x2FFFF +// CHECK: bank : 3 0x30000-0x3FFFF +// CHECK: bank : 4 0x40000-0x4FFFF +// CHECK: bank : 5 0x50000-0x5FFFF +// CHECK: bank : 6 0x60000-0x6FFFF +// CHECK: bank : 7 0x70000-0x7FFFF -// CHECK: %0 = aie.tile(3, 1) -// CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row -// = 1 : i32}> : () -> index CHECK: note: Current configuration of buffers in -// bank(s) : MemoryMap: CHECK: (no stack allocated) CHECK: bank : -// 0 0x0-0xFFFF CHECK: bank : 1 0x10000-0x1FFFF CHECK: -// bank : 2 0x20000-0x2FFFF CHECK: bank : 3 0x30000-0x3FFFF -// CHECK: bank : 4 0x40000-0x4FFFF -// CHECK: bank : 5 0x50000-0x5FFFF -// CHECK: bank : 6 0x60000-0x6FFFF -// CHECK: bank : 7 0x70000-0x7FFFF module @test { - aie.device(xcve2302) { - % 0 = aie.tile(3, 1) % b1 = - aie.buffer(% 0){sym_name = "a"} : memref<132000xi32> aie - .memtile_dma(% 0) { - aie.end - } + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> + aie.memtile_dma(%0) { + aie.end } -} + } +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir index fa771a6090..c87c249d49 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -1,5 +1,4 @@ -//===- memtile_simple.mlir --------------------------------------*- MLIR -//-*-===// +//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -9,33 +8,15 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 -// | FileCheck %s CHECK: error: Failed to allocate buffer: "a" with size: -// 262144 bytes. CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : -// memref<65536xi32> CHECK: ^ CHECK: note: see current operation: -// %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<65536xi32> -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the -// available memory: Bank aware - -// CHECK: %0 = aie.tile(3, 1) -// CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row -// = 1 : i32}> : () -> index CHECK: note: Current configuration of buffers in -// bank(s) : MemoryMap: CHECK: (no stack allocated) CHECK: bank : -// 0 0x0-0xFFFF CHECK: bank : 1 0x10000-0x1FFFF CHECK: -// bank : 2 0x20000-0x2FFFF CHECK: bank : 3 0x30000-0x3FFFF -// CHECK: bank : 4 0x40000-0x4FFFF -// CHECK: bank : 5 0x50000-0x5FFFF -// CHECK: bank : 6 0x60000-0x6FFFF -// CHECK: bank : 7 0x70000-0x7FFFF +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s +// CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16384xi32> module @test { - aie.device(xcve2302) { - % 0 = - aie.tile(3, 1) % b1 = - aie.buffer(% 0){sym_name = "a"} : memref<65536xi32> aie.memtile_dma( - % 0) { - aie.end - } + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16384xi32> + aie.memtile_dma(%0) { + aie.end } -} + } +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index 7dc499c8c0..6038664753 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -8,24 +8,25 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | -// FileCheck %s CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, -// mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> CHECK: {{.*}} -// aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} -// : memref<512xi32> CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, -// mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> CHECK: {{.*}} -// aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = -// "_anonymous0"} : memref<500xi32> +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | FileCheck %s +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> +// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> module @test { - aie.device(xcvc1902) { - % 0 = aie.tile(3, 3) % b1 = - aie.buffer(% 0){sym_name = "a"} : memref<16xi8> % 1 = - aie.buffer(% 0){sym_name = "b"} : memref<512xi32> % b2 = - aie.buffer(% 0){sym_name = "c"} : memref<16xi16> % 3 = - aie.tile(4, 4) % 4 = aie.buffer(% 3) - : memref<500xi32> aie.core(% 0){aie.end} aie.core(% 3) { - aie.end - } + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end } -} + aie.core(%3) { + aie.end + } + } +} \ No newline at end of file From 8f578fd4dcf3bc292c4a8b4c94922822cc8bbb9c Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 17 Jul 2024 16:51:35 -0600 Subject: [PATCH 24/49] Check Message --- .../fallback_routine_error.mlir | 3 --- .../fallback_routine_simple.mlir | 22 +++++++++---------- 2 files changed, 10 insertions(+), 15 deletions(-) diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index 567b3df2f3..726fdd5a78 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -12,12 +12,10 @@ // CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. // CHECK: %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes // CHECK: ^ -// CHECK: note: see current operation: %6 = "aie.buffer"(%0) <{sym_name = "f"}> : (index) -> memref<256xi16> // CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index // CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: // CHECK: (no stack allocated) // CHECK: bank : 0 0x0-0x1FFF @@ -39,7 +37,6 @@ // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index // CHECK: note: MemoryMap: // CHECK: b : 0x0-0x1FFF (8192 bytes) // CHECK: c : 0x2000-0x3FFF (8192 bytes) diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir index 63a8145443..0a44315d40 100644 --- a/test/assign-buffer-addresses/fallback_routine_simple.mlir +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -10,20 +10,18 @@ // RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s // CHECK: error: Failed to allocate buffer: "a" with size: 16384 bytes. -// CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes +// CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes // CHECK: ^ -// CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<4096xi32> // CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware -// CHECK: (no stack allocated) -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index -// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: bank : 3 0x6000-0x7FFF +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: bank : 3 0x6000-0x7FFF // CHECK: module @test { // CHECK: aie.device(xcvc1902) { @@ -47,7 +45,7 @@ module @test { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes - %b1 = aie.buffer(%tile12) { sym_name = "e" } : memref<16xi16> //32 bytes + %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> //32 bytes %tile13 = aie.tile(1, 3) aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1 bytes } From 6d2ea223b3400a4cbbb3db1dfddc9388e0646d7f Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 18 Jul 2024 10:39:59 -0600 Subject: [PATCH 25/49] Default message --- include/aie/Dialect/AIE/Transforms/AIEPasses.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index 0cf5c44acd..354c440d5c 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -28,7 +28,7 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let options = [ Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", - "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, basic-sequential is selected for the Tile's memory and bank-aware is selected for the rest.">, + "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, bank-aware is selected and if it fails, will fall back to basic-sequential scheme.">, ]; } From 5b9c742b83e6f56e1b3f66c61e91f57f6dee05d0 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Mon, 22 Jul 2024 10:15:48 -0600 Subject: [PATCH 26/49] FileCheck --- .../fallback_routine_error.mlir | 33 ------------------- 1 file changed, 33 deletions(-) diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index 726fdd5a78..880cd98ca2 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -10,44 +10,11 @@ // RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s // CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. -// CHECK: %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes -// CHECK: ^ // CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: -// CHECK: (no stack allocated) -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: a : 0x4000-0x4FFF (4096 bytes) -// CHECK: e : 0x5000-0x5FFF (4096 bytes) -// CHECK: bank : 3 0x6000-0x7FFF -// CHECK: d : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential -// CHECK: (no stack allocated) -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: MemoryMap: -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: a : 0x4000-0x4FFF (4096 bytes) -// CHECK: d : 0x5000-0x5FFF (4096 bytes) -// CHECK: e : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) -// CHECK: f : 0x8000-0x81FF (512 bytes) module @test { aie.device(xcvc1902) { From f1b967aaaacc70836b0d01f7716150a96e5516f8 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Mon, 22 Jul 2024 10:22:50 -0600 Subject: [PATCH 27/49] FileCheck --- .../fallback_routine_error.mlir | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index 880cd98ca2..726fdd5a78 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -10,11 +10,44 @@ // RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s // CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. +// CHECK: %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes +// CHECK: ^ // CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: a : 0x4000-0x4FFF (4096 bytes) +// CHECK: e : 0x5000-0x5FFF (4096 bytes) +// CHECK: bank : 3 0x6000-0x7FFF +// CHECK: d : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential +// CHECK: (no stack allocated) +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: MemoryMap: +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: a : 0x4000-0x4FFF (4096 bytes) +// CHECK: d : 0x5000-0x5FFF (4096 bytes) +// CHECK: e : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: f : 0x8000-0x81FF (512 bytes) module @test { aie.device(xcvc1902) { From 47de60c8bca59931626ae1cfe446a2a3f9876338 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Tue, 23 Jul 2024 14:47:26 -0600 Subject: [PATCH 28/49] CI error --- .../AIEVecToCpp/TranslateAIEVecToCpp.cpp | 162 +++++++++--------- 1 file changed, 79 insertions(+), 83 deletions(-) diff --git a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp index 5c80245fa0..fd71fb79bd 100644 --- a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp +++ b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp @@ -28,6 +28,7 @@ #include "mlir/IR/BuiltinTypes.h" #include "mlir/IR/Operation.h" #include "mlir/Support/IndentedOstream.h" +#include "mlir/Support/MathExtras.h" #include "llvm/ADT/ScopedHashTable.h" #include "llvm/ADT/SmallSet.h" @@ -36,7 +37,6 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FormatVariadic.h" -#include "llvm/Support/MathExtras.h" #include #include @@ -87,7 +87,7 @@ LogicalResult interleaveCommaWithError(const Container &c, raw_ostream &os, namespace { /// Emitter that uses dialect specific emitters to emit C++ code. struct CppEmitter { - explicit CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aie2); + explicit CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aieml); /// Emits attribute or returns failure. LogicalResult emitAttribute(Location loc, Attribute attr); @@ -200,7 +200,7 @@ struct CppEmitter { /// be declared at the beginning of a function. bool shouldDeclareVariablesAtTop() { return declareVariablesAtTop; } - bool aie2() { return aie2_; } + bool aieml() { return aieml_; } private: using ValueMapper = llvm::ScopedHashTable; @@ -230,7 +230,7 @@ struct CppEmitter { llvm::SmallSet includeNames; - bool aie2_; + bool aieml_; }; } // namespace @@ -260,7 +260,7 @@ static bool skippedOp(Operation *op, CppEmitter &emitter, // If the underlying element types are float, then we do not really // need an srs op if source of srsOp has only one use. Value source = srsOp.getSource(); - if (!emitter.aie2() && llvm::isa(eltType) && + if (!emitter.aieml() && llvm::isa(eltType) && source.getDefiningOp()->hasOneUse()) { StringRef srcName = emitter.getOrCreateName(source); emitter.setName(srsOp->getResult(0), srcName); @@ -276,7 +276,7 @@ static bool skippedOp(Operation *op, CppEmitter &emitter, // If the underlying element types are float, then we do not really // need a ups op if the source accumulator has only one use. Value source = upsOp.getSource(); - if (!emitter.aie2() && llvm::isa(eltType) && + if (!emitter.aieml() && llvm::isa(eltType) && source.getDefiningOp()->hasOneUse()) { StringRef srcName = emitter.getOrCreateName(source); emitter.setName(upsOp->getResult(0), srcName); @@ -600,9 +600,9 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPDOp updOp) { } // If the vector size to be loaded is less than or equal to 256, we - // can just do a direct memory copy. If the translation is for AIE2, + // can just do a direct memory copy. If the translation is for AIEML, // this number should be doubled - if (vecSizeInBits <= (emitter.aie2() ? 1024 : 256)) { + if (vecSizeInBits <= (emitter.aieml() ? 1024 : 256)) { // Print the lhs if (failed(emitter.emitAssignPrefix(*updOp))) return failure(); @@ -702,7 +702,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { // If the underlying element types are float, then we do not really need a // ups op. We can simply generate an assignment - if (!emitter.aie2() && llvm::isa(eltType)) { + if (!emitter.aieml() && llvm::isa(eltType)) { os << emitter.getOrCreateName(source); return success(); } @@ -715,9 +715,9 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { os << "l"; } - if (iType && emitter.aie2()) { + if (iType && emitter.aieml()) { os << "ups_to_v" << lanes << "acc" << iType.getWidth(); - } else if (fType && emitter.aie2()) { + } else if (fType && emitter.aieml()) { os << "ups_to_v16accfloat"; } else { os << "ups"; @@ -725,7 +725,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { os << "("; os << emitter.getOrCreateName(source); - if (!(fType && emitter.aie2())) { + if (!(fType && emitter.aieml())) { os << ", "; os << std::to_string(shift); } @@ -734,10 +734,10 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { return success(); } -// Generate the cast intrinsic for AIE2 +// Generate the cast intrinsic for AIE-ML static LogicalResult printOperation(CppEmitter &emitter, aievec::CastOp castOp) { - if (!emitter.aie2()) { + if (!emitter.aieml()) { return failure(); } @@ -784,7 +784,7 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -// Generate the unpack intrinsic for AIE2 +// Generate the unpack intrinsic for AIE-ML static LogicalResult printOperation(CppEmitter &emitter, aievec::UnpackOp unpackOp) { @@ -829,7 +829,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) { // If the underlying element types are float, then we do not really need an // srs op. We can simply generate an assignment if (llvm::isa(eltType)) { - if (emitter.aie2()) { + if (emitter.aieml()) { if (unsigned width = getElementSizeInBits(resType); width == 32) os << "srs"; else if (width == 16) @@ -858,7 +858,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) { else if (srcWidth == 48 && resultWidth == 8) os << "b"; - if (emitter.aie2()) + if (emitter.aieml()) os << "srs_to_v" << std::to_string(lanes) << "int" << std::to_string(resWidth); else @@ -949,8 +949,8 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::ExtOp extOp) { unsigned lanes = getVectorLaneSize(resType); unsigned resWidth = getElementSizeInBits(resType); - // Print the version of ext for AIE2 - if (emitter.aie2()) { + // Print the version of ext for aie-ml + if (emitter.aieml()) { os << "extract_v" << std::to_string(lanes); if (llvm::isa(eltType)) os << "int" << std::to_string(resWidth); @@ -1377,39 +1377,6 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::MulOp mulOp) { return success(); } -// convert operand to 512 bits -static std::string printConversionTo512bit(CppEmitter &emitter, Value v) { - std::string vName = emitter.getOrCreateName(v).str(); - auto vTy = cast(v.getType()); - auto vShape = vTy.getShape(); - int64_t elemBitWidth = vTy.getElementTypeBitWidth(); - int64_t numElems = std::accumulate(vShape.begin(), vShape.end(), 1, - std::multiplies()); - int64_t vBitWidth = numElems * elemBitWidth; - if (vBitWidth >= 512) - return vName; - - int64_t newNumElems = 512 / elemBitWidth; - - std::string vNewName = emitter.getNewName(); - raw_indented_ostream &os = emitter.ostream(); - auto newVecTy = VectorType::get({512 / elemBitWidth}, vTy.getElementType()); - auto newTyName = *( - emitter.genCppTypeName(newVecTy, /*stdintType=*/false, /*isAcc=*/false)); - auto oldTyName = - *(emitter.genCppTypeName(vTy, /*stdintType=*/false, /*isAcc=*/false)); - - os << newTyName << " " << vNewName << " = concat("; - if (newNumElems / numElems == 4) { - os << "concat(" << vName << ", undef_" << oldTyName << "())"; - oldTyName = *(emitter.genCppTypeName( - VectorType::get({256 / elemBitWidth}, vTy.getElementType()))); - } else { - os << vName; - } - os << ", undef_" << oldTyName << "());\n"; - return vNewName; -} // Generate the MulElem op static LogicalResult printOperation(CppEmitter &emitter, @@ -1421,9 +1388,6 @@ static LogicalResult printOperation(CppEmitter &emitter, if (!emitter.hasValueInScope(lhs) || !emitter.hasValueInScope(rhs)) return failure(); - auto lhsName = printConversionTo512bit(emitter, lhs); - auto rhsName = printConversionTo512bit(emitter, rhs); - std::string opname = "mul_elem"; // Create opname based on the source type @@ -1453,15 +1417,16 @@ static LogicalResult printOperation(CppEmitter &emitter, return failure(); os << opname; - os << "(" << lhsName; - if ((lsize == 32) && iType) - os << " ," - << "undef_v16int32()"; - os << " ," << rhsName; - if ((lsize == 32) && iType) - os << " , " - << "broadcast_zero_s32()"; + os << "("; + if (failed(printFMAOrMulElemOperand(emitter, mulElemOp, + iType, lsize, 1))) + return failure(); + os << ", "; + if (failed(printFMAOrMulElemOperand(emitter, mulElemOp, + iType, lsize, 0))) + return failure(); os << ")"; + return success(); } @@ -2023,9 +1988,9 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -// Generate the comparison intrinsics(eq, ne, lt, le, gt, ge) for AIE2 +// Generate the comparison intrinsics(eq, ne, lt, le, gt, ge) for AIE-ML static LogicalResult printOperation(CppEmitter &emitter, aievec::CmpOp cmpOp) { - if (!emitter.aie2()) + if (!emitter.aieml()) return failure(); // The lhs and rhs should have already been emitted @@ -2083,9 +2048,9 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::CmpOp cmpOp) { return success(); } -// Generate the sel intrinsic for AIE2 +// Generate the sel intrinsic for AIE-ML static LogicalResult printOperation(CppEmitter &emitter, aievec::SelOp selOp) { - if (!emitter.aie2()) + if (!emitter.aieml()) return failure(); // The lhs, rhs and sel should have already been emitted @@ -2484,10 +2449,8 @@ static LogicalResult printOperation(CppEmitter &emitter, scf::ForOp forOp) { if (auto [constantLoopBound, tripCount] = getTripCount(forOp); constantLoopBound) { auto [constantStep, step] = getStep(forOp); - int64_t lb = - constantStep && step > 0 ? llvm::divideFloorSigned(tripCount, step) : 1; - int64_t ub = - constantStep && step > 0 ? llvm::divideCeilSigned(tripCount, step) : 0; + int64_t lb = constantStep && step > 0 ? floorDiv(tripCount, step) : 1; + int64_t ub = constantStep && step > 0 ? ceilDiv(tripCount, step) : 0; os << "chess_loop_range("; os << std::to_string(lb); os << ", "; @@ -2745,6 +2708,39 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } +static std::string printConversionTo512bit(CppEmitter &emitter, Value v) { + std::string vName = emitter.getOrCreateName(v).str(); + auto vTy = cast(v.getType()); + auto vShape = vTy.getShape(); + int64_t elemBitWidth = vTy.getElementTypeBitWidth(); + int64_t numElems = std::accumulate(vShape.begin(), vShape.end(), 1, + std::multiplies()); + int64_t vBitWidth = numElems * elemBitWidth; + if (vBitWidth >= 512) + return vName; + + int64_t newNumElems = 512 / elemBitWidth; + + std::string vNewName = emitter.getNewName(); + raw_indented_ostream &os = emitter.ostream(); + auto newVecTy = VectorType::get({512 / elemBitWidth}, vTy.getElementType()); + auto newTyName = *( + emitter.genCppTypeName(newVecTy, /*stdintType=*/false, /*isAcc=*/false)); + auto oldTyName = + *(emitter.genCppTypeName(vTy, /*stdintType=*/false, /*isAcc=*/false)); + + os << newTyName << " " << vNewName << " = concat("; + if (newNumElems / numElems == 4) { + os << "concat(" << vName << ", undef_" << oldTyName << "())"; + oldTyName = *(emitter.genCppTypeName( + VectorType::get({256 / elemBitWidth}, vTy.getElementType()))); + } else { + os << vName; + } + os << ", undef_" << oldTyName << "());\n"; + return vNewName; +} + static LogicalResult printOperation(CppEmitter &emitter, aievec::MatMulOp matmulOp) { auto lhs = matmulOp.getLhs(); @@ -2775,8 +2771,8 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -CppEmitter::CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aie2) - : os(os), declareVariablesAtTop(declareVariablesAtTop), aie2_(aie2) { +CppEmitter::CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aieml) + : os(os), declareVariablesAtTop(declareVariablesAtTop), aieml_(aieml) { valueInScopeCount.push(0); labelInScopeCount.push(0); } @@ -2937,7 +2933,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { } if (auto dense = llvm::dyn_cast(attr)) { - if (aie2() && dense.isSplat()) { + if (aieml() && dense.isSplat()) { if (auto vType = llvm::dyn_cast(dense.getType())) if (auto fType = llvm::dyn_cast(vType.getElementType())) { unsigned width = fType.getWidth(); @@ -2980,7 +2976,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { os << ", 0)"; } } - // TODO: Deal with multiple dense value case for AIE2. + // TODO: Deal with multiple dense value case for AIEML. } else { os << '{'; interleaveComma(dense, os, [&](const APFloat &val) { printFloat(val); }); @@ -3024,7 +3020,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { if (auto iType = llvm::dyn_cast(vType.getElementType())) { unsigned width = iType.getWidth(); if (llvm::all_of(dense, [](const APInt &val) { return val == 0; })) { - if (aie2()) { + if (aieml()) { if (width * getVectorLaneSize(vType) == 1024) { os << "concat(broadcast_zero_s" << width << "(), broadcast_zero_s" << width << "())"; @@ -3041,7 +3037,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { return success(); } - if (aie2() && dense.isSplat()) { + if (aieml() && dense.isSplat()) { std::string splatValue; if (width == 32) splatValue = getSplatValueOfIntDense(dense); @@ -3058,7 +3054,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { os << ")"; os << splatValue; os << ")"; - // TODO: Handle multiple dense value case in AIE2. + // TODO: Handle multiple dense value case in AIEML. } else { os << '{'; interleaveComma(dense, os, [&](const APInt &val) { @@ -3383,9 +3379,9 @@ CppEmitter::genCppTypeName(Type type, bool stdintType, bool isAcc) { auto iElTy = dyn_cast(eltType); if (iElTy) iElTyBitWidth = iElTy.getWidth(); - if (aie2() && (isAcc || iElTyBitWidth == 64)) { + if (aieml() && (isAcc || iElTyBitWidth == 64)) { if (iElTy) { - // AIE2 has `ups_to_v16acc32`, `ups_to_v16acc64`, `ups_to_v32acc32` + // AIE-ML has `ups_to_v16acc32`, `ups_to_v16acc64`, `ups_to_v32acc32` // intrinsics if ((numElems == 16 && iElTyBitWidth == 64) || (numElems == 32 && iElTyBitWidth == 32) || @@ -3396,7 +3392,7 @@ CppEmitter::genCppTypeName(Type type, bool stdintType, bool isAcc) { return {}; } if (isa(eltType)) { - // AIE2 only has a `ups_to_v16accfloat` intrinsic + // AIE-ML only has a `ups_to_v16accfloat` intrinsic ss << "accfloat"; return ss.str(); } @@ -3440,8 +3436,8 @@ LogicalResult CppEmitter::emitTupleType(Location loc, ArrayRef types) { return success(); } -LogicalResult aievec::translateAIEVecToCpp(Operation *op, bool aie2, +LogicalResult aievec::translateAIEVecToCpp(Operation *op, bool aieml, raw_ostream &os) { - CppEmitter emitter(os, false, aie2); + CppEmitter emitter(os, false, aieml); return emitter.emitOperation(*op, /*trailingSemicolon=*/false); } From e042b384cb65dc7455003ec6e5a6706d4901a96d Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Tue, 23 Jul 2024 17:34:28 -0600 Subject: [PATCH 29/49] CI error --- .../fallback_routine_error.mlir | 73 ++++++++++--------- 1 file changed, 37 insertions(+), 36 deletions(-) diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index 726fdd5a78..5de9d32ea9 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -10,44 +10,45 @@ // RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s // CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. -// CHECK: %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes -// CHECK: ^ -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: note: see current operation: %6 = "aie.buffer"(%0) <{sym_name = "f"}> : (index) -> memref<256xi16> +// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: -// CHECK: (no stack allocated) -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: a : 0x4000-0x4FFF (4096 bytes) -// CHECK: e : 0x5000-0x5FFF (4096 bytes) -// CHECK: bank : 3 0x6000-0x7FFF -// CHECK: d : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: a : 0x4000-0x4FFF (4096 bytes) +// CHECK: e : 0x5000-0x5FFF (4096 bytes) +// CHECK: bank : 3 0x6000-0x7FFF +// CHECK: d : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) -// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential -// CHECK: (no stack allocated) +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential +// CHECK: (no stack allocated) -// CHECK: %tile12 = aie.tile(1, 2) -// CHECK: ^ -// CHECK: note: MemoryMap: -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: a : 0x4000-0x4FFF (4096 bytes) -// CHECK: d : 0x5000-0x5FFF (4096 bytes) -// CHECK: e : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) -// CHECK: f : 0x8000-0x81FF (512 bytes) +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index +// CHECK: note: MemoryMap: +// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: a : 0x4000-0x4FFF (4096 bytes) +// CHECK: d : 0x5000-0x5FFF (4096 bytes) +// CHECK: e : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) +// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) +// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) +// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: f : 0x8000-0x81FF (512 bytes) module @test { aie.device(xcvc1902) { @@ -61,4 +62,4 @@ module @test { %tile13 = aie.tile(1, 3) aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1024 bytes } -} +} \ No newline at end of file From 3fcdbdeb58f3308b3166d73b231cf798d203c895 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Tue, 23 Jul 2024 17:40:05 -0600 Subject: [PATCH 30/49] Revert changes --- .../AIEVecToCpp/TranslateAIEVecToCpp.cpp | 164 +++++++++--------- 1 file changed, 84 insertions(+), 80 deletions(-) diff --git a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp index fd71fb79bd..9386f8c215 100644 --- a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp +++ b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp @@ -28,7 +28,6 @@ #include "mlir/IR/BuiltinTypes.h" #include "mlir/IR/Operation.h" #include "mlir/Support/IndentedOstream.h" -#include "mlir/Support/MathExtras.h" #include "llvm/ADT/ScopedHashTable.h" #include "llvm/ADT/SmallSet.h" @@ -37,6 +36,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FormatVariadic.h" +#include "llvm/Support/MathExtras.h" #include #include @@ -87,7 +87,7 @@ LogicalResult interleaveCommaWithError(const Container &c, raw_ostream &os, namespace { /// Emitter that uses dialect specific emitters to emit C++ code. struct CppEmitter { - explicit CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aieml); + explicit CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aie2); /// Emits attribute or returns failure. LogicalResult emitAttribute(Location loc, Attribute attr); @@ -200,7 +200,7 @@ struct CppEmitter { /// be declared at the beginning of a function. bool shouldDeclareVariablesAtTop() { return declareVariablesAtTop; } - bool aieml() { return aieml_; } + bool aie2() { return aie2_; } private: using ValueMapper = llvm::ScopedHashTable; @@ -230,7 +230,7 @@ struct CppEmitter { llvm::SmallSet includeNames; - bool aieml_; + bool aie2_; }; } // namespace @@ -260,7 +260,7 @@ static bool skippedOp(Operation *op, CppEmitter &emitter, // If the underlying element types are float, then we do not really // need an srs op if source of srsOp has only one use. Value source = srsOp.getSource(); - if (!emitter.aieml() && llvm::isa(eltType) && + if (!emitter.aie2() && llvm::isa(eltType) && source.getDefiningOp()->hasOneUse()) { StringRef srcName = emitter.getOrCreateName(source); emitter.setName(srsOp->getResult(0), srcName); @@ -276,7 +276,7 @@ static bool skippedOp(Operation *op, CppEmitter &emitter, // If the underlying element types are float, then we do not really // need a ups op if the source accumulator has only one use. Value source = upsOp.getSource(); - if (!emitter.aieml() && llvm::isa(eltType) && + if (!emitter.aie2() && llvm::isa(eltType) && source.getDefiningOp()->hasOneUse()) { StringRef srcName = emitter.getOrCreateName(source); emitter.setName(upsOp->getResult(0), srcName); @@ -600,9 +600,9 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPDOp updOp) { } // If the vector size to be loaded is less than or equal to 256, we - // can just do a direct memory copy. If the translation is for AIEML, + // can just do a direct memory copy. If the translation is for AIE2, // this number should be doubled - if (vecSizeInBits <= (emitter.aieml() ? 1024 : 256)) { + if (vecSizeInBits <= (emitter.aie2() ? 1024 : 256)) { // Print the lhs if (failed(emitter.emitAssignPrefix(*updOp))) return failure(); @@ -702,7 +702,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { // If the underlying element types are float, then we do not really need a // ups op. We can simply generate an assignment - if (!emitter.aieml() && llvm::isa(eltType)) { + if (!emitter.aie2() && llvm::isa(eltType)) { os << emitter.getOrCreateName(source); return success(); } @@ -715,9 +715,9 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { os << "l"; } - if (iType && emitter.aieml()) { + if (iType && emitter.aie2()) { os << "ups_to_v" << lanes << "acc" << iType.getWidth(); - } else if (fType && emitter.aieml()) { + } else if (fType && emitter.aie2()) { os << "ups_to_v16accfloat"; } else { os << "ups"; @@ -725,7 +725,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { os << "("; os << emitter.getOrCreateName(source); - if (!(fType && emitter.aieml())) { + if (!(fType && emitter.aie2())) { os << ", "; os << std::to_string(shift); } @@ -734,10 +734,10 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::UPSOp upsOp) { return success(); } -// Generate the cast intrinsic for AIE-ML +// Generate the cast intrinsic for AIE2 static LogicalResult printOperation(CppEmitter &emitter, aievec::CastOp castOp) { - if (!emitter.aieml()) { + if (!emitter.aie2()) { return failure(); } @@ -784,7 +784,7 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -// Generate the unpack intrinsic for AIE-ML +// Generate the unpack intrinsic for AIE2 static LogicalResult printOperation(CppEmitter &emitter, aievec::UnpackOp unpackOp) { @@ -829,7 +829,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) { // If the underlying element types are float, then we do not really need an // srs op. We can simply generate an assignment if (llvm::isa(eltType)) { - if (emitter.aieml()) { + if (emitter.aie2()) { if (unsigned width = getElementSizeInBits(resType); width == 32) os << "srs"; else if (width == 16) @@ -858,7 +858,7 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::SRSOp srsOp) { else if (srcWidth == 48 && resultWidth == 8) os << "b"; - if (emitter.aieml()) + if (emitter.aie2()) os << "srs_to_v" << std::to_string(lanes) << "int" << std::to_string(resWidth); else @@ -949,8 +949,8 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::ExtOp extOp) { unsigned lanes = getVectorLaneSize(resType); unsigned resWidth = getElementSizeInBits(resType); - // Print the version of ext for aie-ml - if (emitter.aieml()) { + // Print the version of ext for AIE2 + if (emitter.aie2()) { os << "extract_v" << std::to_string(lanes); if (llvm::isa(eltType)) os << "int" << std::to_string(resWidth); @@ -1377,6 +1377,39 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::MulOp mulOp) { return success(); } +// convert operand to 512 bits +static std::string printConversionTo512bit(CppEmitter &emitter, Value v) { + std::string vName = emitter.getOrCreateName(v).str(); + auto vTy = cast(v.getType()); + auto vShape = vTy.getShape(); + int64_t elemBitWidth = vTy.getElementTypeBitWidth(); + int64_t numElems = std::accumulate(vShape.begin(), vShape.end(), 1, + std::multiplies()); + int64_t vBitWidth = numElems * elemBitWidth; + if (vBitWidth >= 512) + return vName; + + int64_t newNumElems = 512 / elemBitWidth; + + std::string vNewName = emitter.getNewName(); + raw_indented_ostream &os = emitter.ostream(); + auto newVecTy = VectorType::get({512 / elemBitWidth}, vTy.getElementType()); + auto newTyName = *( + emitter.genCppTypeName(newVecTy, /*stdintType=*/false, /*isAcc=*/false)); + auto oldTyName = + *(emitter.genCppTypeName(vTy, /*stdintType=*/false, /*isAcc=*/false)); + + os << newTyName << " " << vNewName << " = concat("; + if (newNumElems / numElems == 4) { + os << "concat(" << vName << ", undef_" << oldTyName << "())"; + oldTyName = *(emitter.genCppTypeName( + VectorType::get({256 / elemBitWidth}, vTy.getElementType()))); + } else { + os << vName; + } + os << ", undef_" << oldTyName << "());\n"; + return vNewName; +} // Generate the MulElem op static LogicalResult printOperation(CppEmitter &emitter, @@ -1388,6 +1421,9 @@ static LogicalResult printOperation(CppEmitter &emitter, if (!emitter.hasValueInScope(lhs) || !emitter.hasValueInScope(rhs)) return failure(); + auto lhsName = printConversionTo512bit(emitter, lhs); + auto rhsName = printConversionTo512bit(emitter, rhs); + std::string opname = "mul_elem"; // Create opname based on the source type @@ -1417,16 +1453,15 @@ static LogicalResult printOperation(CppEmitter &emitter, return failure(); os << opname; - os << "("; - if (failed(printFMAOrMulElemOperand(emitter, mulElemOp, - iType, lsize, 1))) - return failure(); - os << ", "; - if (failed(printFMAOrMulElemOperand(emitter, mulElemOp, - iType, lsize, 0))) - return failure(); + os << "(" << lhsName; + if ((lsize == 32) && iType) + os << " ," + << "undef_v16int32()"; + os << " ," << rhsName; + if ((lsize == 32) && iType) + os << " , " + << "broadcast_zero_s32()"; os << ")"; - return success(); } @@ -1988,9 +2023,9 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -// Generate the comparison intrinsics(eq, ne, lt, le, gt, ge) for AIE-ML +// Generate the comparison intrinsics(eq, ne, lt, le, gt, ge) for AIE2 static LogicalResult printOperation(CppEmitter &emitter, aievec::CmpOp cmpOp) { - if (!emitter.aieml()) + if (!emitter.aie2()) return failure(); // The lhs and rhs should have already been emitted @@ -2048,9 +2083,9 @@ static LogicalResult printOperation(CppEmitter &emitter, aievec::CmpOp cmpOp) { return success(); } -// Generate the sel intrinsic for AIE-ML +// Generate the sel intrinsic for AIE2 static LogicalResult printOperation(CppEmitter &emitter, aievec::SelOp selOp) { - if (!emitter.aieml()) + if (!emitter.aie2()) return failure(); // The lhs, rhs and sel should have already been emitted @@ -2449,8 +2484,10 @@ static LogicalResult printOperation(CppEmitter &emitter, scf::ForOp forOp) { if (auto [constantLoopBound, tripCount] = getTripCount(forOp); constantLoopBound) { auto [constantStep, step] = getStep(forOp); - int64_t lb = constantStep && step > 0 ? floorDiv(tripCount, step) : 1; - int64_t ub = constantStep && step > 0 ? ceilDiv(tripCount, step) : 0; + int64_t lb = + constantStep && step > 0 ? llvm::divideFloorSigned(tripCount, step) : 1; + int64_t ub = + constantStep && step > 0 ? llvm::divideCeilSigned(tripCount, step) : 0; os << "chess_loop_range("; os << std::to_string(lb); os << ", "; @@ -2708,39 +2745,6 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -static std::string printConversionTo512bit(CppEmitter &emitter, Value v) { - std::string vName = emitter.getOrCreateName(v).str(); - auto vTy = cast(v.getType()); - auto vShape = vTy.getShape(); - int64_t elemBitWidth = vTy.getElementTypeBitWidth(); - int64_t numElems = std::accumulate(vShape.begin(), vShape.end(), 1, - std::multiplies()); - int64_t vBitWidth = numElems * elemBitWidth; - if (vBitWidth >= 512) - return vName; - - int64_t newNumElems = 512 / elemBitWidth; - - std::string vNewName = emitter.getNewName(); - raw_indented_ostream &os = emitter.ostream(); - auto newVecTy = VectorType::get({512 / elemBitWidth}, vTy.getElementType()); - auto newTyName = *( - emitter.genCppTypeName(newVecTy, /*stdintType=*/false, /*isAcc=*/false)); - auto oldTyName = - *(emitter.genCppTypeName(vTy, /*stdintType=*/false, /*isAcc=*/false)); - - os << newTyName << " " << vNewName << " = concat("; - if (newNumElems / numElems == 4) { - os << "concat(" << vName << ", undef_" << oldTyName << "())"; - oldTyName = *(emitter.genCppTypeName( - VectorType::get({256 / elemBitWidth}, vTy.getElementType()))); - } else { - os << vName; - } - os << ", undef_" << oldTyName << "());\n"; - return vNewName; -} - static LogicalResult printOperation(CppEmitter &emitter, aievec::MatMulOp matmulOp) { auto lhs = matmulOp.getLhs(); @@ -2771,8 +2775,8 @@ static LogicalResult printOperation(CppEmitter &emitter, return success(); } -CppEmitter::CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aieml) - : os(os), declareVariablesAtTop(declareVariablesAtTop), aieml_(aieml) { +CppEmitter::CppEmitter(raw_ostream &os, bool declareVariablesAtTop, bool aie2) + : os(os), declareVariablesAtTop(declareVariablesAtTop), aie2_(aie2) { valueInScopeCount.push(0); labelInScopeCount.push(0); } @@ -2933,7 +2937,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { } if (auto dense = llvm::dyn_cast(attr)) { - if (aieml() && dense.isSplat()) { + if (aie2() && dense.isSplat()) { if (auto vType = llvm::dyn_cast(dense.getType())) if (auto fType = llvm::dyn_cast(vType.getElementType())) { unsigned width = fType.getWidth(); @@ -2976,7 +2980,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { os << ", 0)"; } } - // TODO: Deal with multiple dense value case for AIEML. + // TODO: Deal with multiple dense value case for AIE2. } else { os << '{'; interleaveComma(dense, os, [&](const APFloat &val) { printFloat(val); }); @@ -3020,7 +3024,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { if (auto iType = llvm::dyn_cast(vType.getElementType())) { unsigned width = iType.getWidth(); if (llvm::all_of(dense, [](const APInt &val) { return val == 0; })) { - if (aieml()) { + if (aie2()) { if (width * getVectorLaneSize(vType) == 1024) { os << "concat(broadcast_zero_s" << width << "(), broadcast_zero_s" << width << "())"; @@ -3037,7 +3041,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { return success(); } - if (aieml() && dense.isSplat()) { + if (aie2() && dense.isSplat()) { std::string splatValue; if (width == 32) splatValue = getSplatValueOfIntDense(dense); @@ -3054,7 +3058,7 @@ LogicalResult CppEmitter::emitAttribute(Location loc, Attribute attr) { os << ")"; os << splatValue; os << ")"; - // TODO: Handle multiple dense value case in AIEML. + // TODO: Handle multiple dense value case in AIE2. } else { os << '{'; interleaveComma(dense, os, [&](const APInt &val) { @@ -3379,9 +3383,9 @@ CppEmitter::genCppTypeName(Type type, bool stdintType, bool isAcc) { auto iElTy = dyn_cast(eltType); if (iElTy) iElTyBitWidth = iElTy.getWidth(); - if (aieml() && (isAcc || iElTyBitWidth == 64)) { + if (aie2() && (isAcc || iElTyBitWidth == 64)) { if (iElTy) { - // AIE-ML has `ups_to_v16acc32`, `ups_to_v16acc64`, `ups_to_v32acc32` + // AIE2 has `ups_to_v16acc32`, `ups_to_v16acc64`, `ups_to_v32acc32` // intrinsics if ((numElems == 16 && iElTyBitWidth == 64) || (numElems == 32 && iElTyBitWidth == 32) || @@ -3392,7 +3396,7 @@ CppEmitter::genCppTypeName(Type type, bool stdintType, bool isAcc) { return {}; } if (isa(eltType)) { - // AIE-ML only has a `ups_to_v16accfloat` intrinsic + // AIE2 only has a `ups_to_v16accfloat` intrinsic ss << "accfloat"; return ss.str(); } @@ -3436,8 +3440,8 @@ LogicalResult CppEmitter::emitTupleType(Location loc, ArrayRef types) { return success(); } -LogicalResult aievec::translateAIEVecToCpp(Operation *op, bool aieml, +LogicalResult aievec::translateAIEVecToCpp(Operation *op, bool aie2, raw_ostream &os) { - CppEmitter emitter(os, false, aieml); + CppEmitter emitter(os, false, aie2); return emitter.emitOperation(*op, /*trailingSemicolon=*/false); -} +} \ No newline at end of file From ca9e514312c6274bcca3144873a89bf4fb52dcea Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Wed, 24 Jul 2024 09:22:13 -0600 Subject: [PATCH 31/49] Message change --- lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp | 2 +- test/assign-buffer-addresses/bank_aware_alloc_error.mlir | 2 +- .../assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir | 2 +- test/assign-buffer-addresses/fallback_routine_error.mlir | 2 +- test/assign-buffer-addresses/fallback_routine_simple.mlir | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 11a46ffd25..0e984fd562 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -192,7 +192,7 @@ void printMemMap(TileOp tile, SmallVector allocatedBuffers, SmallVector preAllocatedBuffers, int numBanks, std::vector &bankLimits, int stacksize) { InFlightDiagnostic error = - tile.emitOpError("All requested buffers doesn't fit in the available " + tile.emitOpError("All requested buffers don't fit in the available " "memory: Bank aware\n"); auto ¬e = error.attachNote() << "Current configuration of buffers in bank(s) : "; diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index d05b49aadd..548686310f 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -13,7 +13,7 @@ // CHECK: %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> // CHECK: ^ // CHECK: note: see current operation: %2 = "aie.buffer"(%0) <{sym_name = "b"}> : (index) -> memref<8192xi32> -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: error: 'aie.tile' op All requested buffers don't fit in the available memory: Bank aware // CHECK: %0 = aie.tile(3, 3) // CHECK: ^ diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index 694844dded..ca8537beff 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -13,7 +13,7 @@ // CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> // CHECK: ^ // CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<132000xi32> -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: error: 'aie.tile' op All requested buffers don't fit in the available memory: Bank aware // CHECK: %0 = aie.tile(3, 1) // CHECK: ^ diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index 5de9d32ea9..e1fd8f75a1 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -11,7 +11,7 @@ // RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s // CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. // CHECK: note: see current operation: %6 = "aie.buffer"(%0) <{sym_name = "f"}> : (index) -> memref<256xi16> -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: error: 'aie.tile' op All requested buffers don't fit in the available memory: Bank aware // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir index 0a44315d40..301b0daf41 100644 --- a/test/assign-buffer-addresses/fallback_routine_simple.mlir +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -12,7 +12,7 @@ // CHECK: error: Failed to allocate buffer: "a" with size: 16384 bytes. // CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes // CHECK: ^ -// CHECK: error: 'aie.tile' op All requested buffers doesn't fit in the available memory: Bank aware +// CHECK: error: 'aie.tile' op All requested buffers don't fit in the available memory: Bank aware // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ From 4384c9b14f5c1bd816f6838f03f90f6a8511f1ee Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 25 Jul 2024 13:18:04 -0600 Subject: [PATCH 32/49] Adjusting bankIndex --- lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 0e984fd562..0639db5e9b 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -251,6 +251,7 @@ bool setBufferAddress(BufferOp buffer, int numBanks, int &bankIndex, setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); allocated = true; bankIndex++; + bankIndex %= numBanks; break; } // Move to the next bank From 978f55eeaa557cfd64badbea68ad7436cfca4b74 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Mon, 16 Sep 2024 16:50:55 -0600 Subject: [PATCH 33/49] Merge latest changes --- python/compiler/aiecc/main.py | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index fd7e175df5..0afccd591f 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -37,7 +37,7 @@ from aie.passmanager import PassManager INPUT_WITH_ADDRESSES_PIPELINE = ( - lambda basic_alloc_scheme=False, ctrl_pkt_overlay=False: ( + lambda scheme="", ctrl_pkt_overlay=False: ( Pipeline() .lower_affine() .add_pass("aie-canonicalize-device") @@ -56,7 +56,7 @@ "aie-generate-column-control-overlay", route_shim_to_tile_ctrl=ctrl_pkt_overlay, ) - .add_pass("aie-assign-buffer-addresses", basic_alloc=basic_alloc_scheme), + .add_pass("aie-assign-buffer-addresses", alloc_scheme=scheme), ) .convert_scf_to_cf() ) @@ -1048,18 +1048,12 @@ async def run_flow(self): ) file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") -<<<<<<< HEAD if opts.alloc_scheme: pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( opts.alloc_scheme ).materialize(module=True) else: pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE().materialize(module=True) -======= - pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( - opts.basic_alloc_scheme, opts.ctrl_pkt_overlay - ).materialize(module=True) ->>>>>>> 932a5df230ed255e9053777f0e07ddde1324531c run_passes( pass_pipeline, self.mlir_module_str, From bd5a81bc8300eef19fde77e31d02a4a609dec247 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Mon, 16 Sep 2024 16:55:53 -0600 Subject: [PATCH 34/49] Formatting main.py --- python/compiler/aiecc/main.py | 40 +++++++++++++++++------------------ 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index 0afccd591f..1b88517434 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -36,30 +36,28 @@ from aie.ir import Context, Location, Module from aie.passmanager import PassManager -INPUT_WITH_ADDRESSES_PIPELINE = ( - lambda scheme="", ctrl_pkt_overlay=False: ( +INPUT_WITH_ADDRESSES_PIPELINE = lambda scheme="", ctrl_pkt_overlay=False: ( + Pipeline() + .lower_affine() + .add_pass("aie-canonicalize-device") + .Nested( + "aie.device", Pipeline() - .lower_affine() - .add_pass("aie-canonicalize-device") - .Nested( - "aie.device", - Pipeline() - .add_pass("aie-assign-lock-ids") - .add_pass("aie-register-objectFifos") - .add_pass("aie-objectFifo-stateful-transform") - .add_pass("aie-assign-bd-ids") - .add_pass("aie-lower-cascade-flows") - .add_pass("aie-lower-broadcast-packet") - .add_pass("aie-lower-multicast") - .add_pass("aie-assign-tile-controller-ids") - .add_pass( - "aie-generate-column-control-overlay", - route_shim_to_tile_ctrl=ctrl_pkt_overlay, - ) - .add_pass("aie-assign-buffer-addresses", alloc_scheme=scheme), + .add_pass("aie-assign-lock-ids") + .add_pass("aie-register-objectFifos") + .add_pass("aie-objectFifo-stateful-transform") + .add_pass("aie-assign-bd-ids") + .add_pass("aie-lower-cascade-flows") + .add_pass("aie-lower-broadcast-packet") + .add_pass("aie-lower-multicast") + .add_pass("aie-assign-tile-controller-ids") + .add_pass( + "aie-generate-column-control-overlay", + route_shim_to_tile_ctrl=ctrl_pkt_overlay, ) - .convert_scf_to_cf() + .add_pass("aie-assign-buffer-addresses", alloc_scheme=scheme), ) + .convert_scf_to_cf() ) LOWER_TO_LLVM_PIPELINE = ( From fc6dca2aaa29900211ecf09b7a9f0bae95400f33 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Mon, 16 Sep 2024 17:11:42 -0600 Subject: [PATCH 35/49] Updated check messages --- .../bank_aware_alloc_memory_exhausted.mlir | 2 +- .../bank_aware_alloc_simple.mlir | 10 ++++++---- .../fallback_routine_error.mlir | 19 +++++-------------- 3 files changed, 12 insertions(+), 19 deletions(-) diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir index d8381a9437..608be4c42c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --verify-diagnostics --aie-assign-buffer-addresses=basic-alloc=0 %s +// RUN: aie-opt --verify-diagnostics --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s module { aie.device(npu1_2col) { diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index 6038664753..4a3e3aec5c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -9,10 +9,12 @@ //===----------------------------------------------------------------------===// // RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> +// CHECK: %a = aie.buffer(%tile_3_3) {address = 3104 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16xi8> +// CHECK: %b = aie.buffer(%tile_3_3) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> +// CHECK: %c = aie.buffer(%tile_3_3) {address = 3072 : i32, mem_bank = 0 : i32, sym_name = "c"} : memref<16xi16> +// CHECK: %_anonymous0 = aie.buffer(%tile_4_4) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> + + module @test { aie.device(xcvc1902) { diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index e1fd8f75a1..bd9d47e1f2 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -15,22 +15,17 @@ // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ -// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index // CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: // CHECK: (no stack allocated) // CHECK: bank : 0 0x0-0x1FFF -// CHECK: b : 0x0-0x1FFF (8192 bytes) +// CHECK: a : 0x0-0x1FFF (8192 bytes) // CHECK: bank : 1 0x2000-0x3FFF -// CHECK: c : 0x2000-0x3FFF (8192 bytes) +// CHECK: b : 0x2000-0x3FFF (8192 bytes) // CHECK: bank : 2 0x4000-0x5FFF -// CHECK: a : 0x4000-0x4FFF (4096 bytes) -// CHECK: e : 0x5000-0x5FFF (4096 bytes) +// CHECK: c : 0x4000-0x5FFF (8192 bytes) // CHECK: bank : 3 0x6000-0x7FFF // CHECK: d : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) +// CHECK: e : 0x7000-0x7FFF (4096 bytes) // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential // CHECK: (no stack allocated) @@ -44,16 +39,12 @@ // CHECK: a : 0x4000-0x4FFF (4096 bytes) // CHECK: d : 0x5000-0x5FFF (4096 bytes) // CHECK: e : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x73FF (1024 bytes) -// CHECK: act_3_4_buff_1 : 0x7400-0x77FF (1024 bytes) -// CHECK: act_3_4_buff_2 : 0x7800-0x7BFF (1024 bytes) -// CHECK: act_3_4_buff_3 : 0x7C00-0x7FFF (1024 bytes) // CHECK: f : 0x8000-0x81FF (512 bytes) module @test { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) - %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<1024xi32> //4096 bytes + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<2048xi32> //8192 bytes %2 = aie.buffer(%tile12) { sym_name = "b" } : memref<2048xi32> //8192 bytes %3 = aie.buffer(%tile12) { sym_name = "c" } : memref<2048xi32> //8192 bytes %4 = aie.buffer(%tile12) { sym_name = "d" } : memref<1024xi32> //4096 bytes From 4c34c280e02c6d64a252818c76af5b785278f86d Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 09:51:11 -0600 Subject: [PATCH 36/49] Update flags --- .../bank_aware_alloc_memory_exhausted.mlir | 29 +++++++++++++++++-- test/npu-xrt/add_blockwrite/run.lit | 2 +- test/npu-xrt/add_maskwrite/run.lit | 2 +- test/npu-xrt/add_one_ctrl_packet/run.lit | 2 +- .../add_one_ctrl_packet_4_cores/run.lit | 2 +- .../add_one_ctrl_packet_col_overlay/run.lit | 2 +- 6 files changed, 31 insertions(+), 8 deletions(-) diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir index 608be4c42c..c574ba652c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir @@ -8,12 +8,35 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --verify-diagnostics --aie-assign-buffer-addresses="alloc-scheme=basic-alloc" %s +// RUN: not aie-opt --aie-assign-bd-ids --aie-assign-buffer-addresses %s + +// CHECK: error: Failed to allocate buffer: "_anonymous0" with size: 24576 bytes. +// CHECK: %C_L1L2_0_0_buff_0 = aie.buffer(%tile_0_2) : memref<64x96xf32> +// CHECK: ^ +// CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "_anonymous0"}> : (index) -> memref<64x96xf32> +// CHECK: error: 'aie.tile' op All requested buffers don't fit in the available memory: Bank aware + +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 0 : i32, row = 2 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x3FFF +// CHECK: bank : 1 0x4000-0x7FFF +// CHECK: bank : 2 0x8000-0xBFFF +// CHECK: bank : 3 0xC000-0xFFFF + +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential +// CHECK: (no stack allocated) + +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 0 : i32, row = 2 : i32}> : () -> index +// CHECK: _anonymous0 : 0x0-0x5FFF (24576 bytes) +// CHECK: _anonymous1 : 0x6000-0xBFFF (24576 bytes) +// CHECK: _anonymous2 : 0xC000-0xD7FF (6144 bytes) +// CHECK: _anonymous3 : 0xD800-0xEFFF (6144 bytes) +// CHECK: _anonymous4 : 0xF000-0xFFFF (4096 bytes) +// CHECK: _anonymous5 : 0x10000-0x10FFF (4096 bytes) module { aie.device(npu1_2col) { - // expected-error@+2 {{allocated buffers exceeded available memory}} - // expected-note@+1 {{}} %tile_0_2 = aie.tile(0, 2) %C_L1L2_0_0_buff_0 = aie.buffer(%tile_0_2) : memref<64x96xf32> %C_L1L2_0_0_buff_1 = aie.buffer(%tile_0_2) : memref<64x96xf32> diff --git a/test/npu-xrt/add_blockwrite/run.lit b/test/npu-xrt/add_blockwrite/run.lit index 35aa0b374d..a3ce61f18b 100644 --- a/test/npu-xrt/add_blockwrite/run.lit +++ b/test/npu-xrt/add_blockwrite/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_maskwrite/run.lit b/test/npu-xrt/add_maskwrite/run.lit index 35aa0b374d..a3ce61f18b 100644 --- a/test/npu-xrt/add_maskwrite/run.lit +++ b/test/npu-xrt/add_maskwrite/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_one_ctrl_packet/run.lit b/test/npu-xrt/add_one_ctrl_packet/run.lit index f08641410e..b7914c9f10 100644 --- a/test/npu-xrt/add_one_ctrl_packet/run.lit +++ b/test/npu-xrt/add_one_ctrl_packet/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit b/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit index f08641410e..b7914c9f10 100644 --- a/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit +++ b/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit b/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit index 1ad5f311fc..a3457c7f17 100644 --- a/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit +++ b/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --generate-ctrl-pkt-overlay --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --generate-ctrl-pkt-overlay --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ -lboost_program_options -lboost_filesystem // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! From 08de1fcae1c128670c7e92d38bf08e2a2e08217a Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 10:07:16 -0600 Subject: [PATCH 37/49] Fall back Error Test case --- .../fallback_routine_error.mlir | 22 ++++++++++++------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index bd9d47e1f2..ba56b2c6ae 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -9,8 +9,8 @@ //===----------------------------------------------------------------------===// // RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s -// CHECK: error: Failed to allocate buffer: "f" with size: 512 bytes. -// CHECK: note: see current operation: %6 = "aie.buffer"(%0) <{sym_name = "f"}> : (index) -> memref<256xi16> +// CHECK: error: Failed to allocate buffer: "act_3_4_buff_2" with size: 2048 bytes. +// CHECK: note: see current operation: %10 = "aie.buffer"(%0) <{sym_name = "act_3_4_buff_2"}> : (index) -> memref<512xi32> // CHECK: error: 'aie.tile' op All requested buffers don't fit in the available memory: Bank aware // CHECK: %tile12 = aie.tile(1, 2) @@ -22,10 +22,12 @@ // CHECK: bank : 1 0x2000-0x3FFF // CHECK: b : 0x2000-0x3FFF (8192 bytes) // CHECK: bank : 2 0x4000-0x5FFF -// CHECK: c : 0x4000-0x5FFF (8192 bytes) +// CHECK: c : 0x4000-0x4FFF (4096 bytes) +// CHECK: d : 0x5000-0x5FFF (4096 bytes) // CHECK: bank : 3 0x6000-0x7FFF -// CHECK: d : 0x6000-0x6FFF (4096 bytes) -// CHECK: e : 0x7000-0x7FFF (4096 bytes) +// CHECK: e : 0x6000-0x6FFF (4096 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x77FF (2048 bytes) +// CHECK: act_3_4_buff_1 : 0x7800-0x7FFF (2048 bytes) // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential // CHECK: (no stack allocated) @@ -39,18 +41,22 @@ // CHECK: a : 0x4000-0x4FFF (4096 bytes) // CHECK: d : 0x5000-0x5FFF (4096 bytes) // CHECK: e : 0x6000-0x6FFF (4096 bytes) -// CHECK: f : 0x8000-0x81FF (512 bytes) +// CHECK: act_3_4_buff_0 : 0x7000-0x77FF (2048 bytes) +// CHECK: act_3_4_buff_1 : 0x7800-0x7FFF (2048 bytes) +// CHECK: act_3_4_buff_2 : 0x8000-0x87FF (2048 bytes) +// CHECK: act_3_4_buff_3 : 0x8800-0x8FFF (2048 bytes) +// CHECK: f : 0x9000-0x91FF (512 bytes) module @test { aie.device(xcvc1902) { %tile12 = aie.tile(1, 2) - %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<2048xi32> //8192 bytes + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<1024xi32> //8192 bytes %2 = aie.buffer(%tile12) { sym_name = "b" } : memref<2048xi32> //8192 bytes %3 = aie.buffer(%tile12) { sym_name = "c" } : memref<2048xi32> //8192 bytes %4 = aie.buffer(%tile12) { sym_name = "d" } : memref<1024xi32> //4096 bytes %5 = aie.buffer(%tile12) { sym_name = "e" } : memref<1024xi32> //4096 bytes %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes %tile13 = aie.tile(1, 3) - aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1024 bytes + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1024 bytes } } \ No newline at end of file From 6bdd30f93c8ba594bf1a38cec8a39387c89bdf0b Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 10:12:39 -0600 Subject: [PATCH 38/49] Reduced CHECK message --- .../fallback_routine_error.mlir | 24 ------------------- 1 file changed, 24 deletions(-) diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index ba56b2c6ae..b04099378e 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -15,19 +15,6 @@ // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ -// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: -// CHECK: (no stack allocated) -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: a : 0x0-0x1FFF (8192 bytes) -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: b : 0x2000-0x3FFF (8192 bytes) -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: c : 0x4000-0x4FFF (4096 bytes) -// CHECK: d : 0x5000-0x5FFF (4096 bytes) -// CHECK: bank : 3 0x6000-0x7FFF -// CHECK: e : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x77FF (2048 bytes) -// CHECK: act_3_4_buff_1 : 0x7800-0x7FFF (2048 bytes) // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential // CHECK: (no stack allocated) @@ -35,17 +22,6 @@ // CHECK: %tile12 = aie.tile(1, 2) // CHECK: ^ // CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index -// CHECK: note: MemoryMap: -// CHECK: b : 0x0-0x1FFF (8192 bytes) -// CHECK: c : 0x2000-0x3FFF (8192 bytes) -// CHECK: a : 0x4000-0x4FFF (4096 bytes) -// CHECK: d : 0x5000-0x5FFF (4096 bytes) -// CHECK: e : 0x6000-0x6FFF (4096 bytes) -// CHECK: act_3_4_buff_0 : 0x7000-0x77FF (2048 bytes) -// CHECK: act_3_4_buff_1 : 0x7800-0x7FFF (2048 bytes) -// CHECK: act_3_4_buff_2 : 0x8000-0x87FF (2048 bytes) -// CHECK: act_3_4_buff_3 : 0x8800-0x8FFF (2048 bytes) -// CHECK: f : 0x9000-0x91FF (512 bytes) module @test { aie.device(xcvc1902) { From 84b94ac4b56a6e27ee711a9b64a243d7ccc718c5 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 10:41:14 -0600 Subject: [PATCH 39/49] Updating names --- test/assign-buffer-addresses/bank_aware_alloc_error.mlir | 2 +- .../bank_aware_alloc_memory_exhausted.mlir | 2 +- .../assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir | 2 +- .../bank_aware_alloc_memtile_simple.mlir | 2 +- test/assign-buffer-addresses/bank_aware_alloc_simple.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_error.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_memtile_error.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir | 2 +- test/assign-buffer-addresses/basic_alloc_simple.mlir | 2 +- test/assign-buffer-addresses/fallback_routine_error.mlir | 1 - 10 files changed, 9 insertions(+), 10 deletions(-) diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index 548686310f..c5e9fba216 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_error.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir index c574ba652c..7200f1a982 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memory_exhausted.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index ca8537beff..6f00903c4e 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -1,4 +1,4 @@ -//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memtile_error.mlir ---------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir index c87c249d49..292291ef9c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -1,4 +1,4 @@ -//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memtile_simple.mlir --------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index 4a3e3aec5c..6724123b4b 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_simple.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/basic_alloc_error.mlir b/test/assign-buffer-addresses/basic_alloc_error.mlir index 03bb66e4cc..7cc1db9a1a 100644 --- a/test/assign-buffer-addresses/basic_alloc_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_error.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- basic_alloc_error.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir index 0828732051..7aaba2b3d6 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir @@ -1,4 +1,4 @@ -//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- basic_alloc_memtile_error.mlir ---------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index b504d6cc43..d140f23521 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -1,4 +1,4 @@ -//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- basic_alloc_memtile_simple.mlir --------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/basic_alloc_simple.mlir b/test/assign-buffer-addresses/basic_alloc_simple.mlir index 73447208f6..f866c76eae 100644 --- a/test/assign-buffer-addresses/basic_alloc_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_simple.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- basic_alloc_simple.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir index b04099378e..a2165600fb 100644 --- a/test/assign-buffer-addresses/fallback_routine_error.mlir +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -1,5 +1,4 @@ //===- fallback_routine_error.mlir ---------------------------------------------*- MLIR -*-===// -// // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception From 52023025dc39f9458da34bc739fd96c99989fa95 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 10:50:42 -0600 Subject: [PATCH 40/49] Unit tests --- .../01_DDR_SHIM_LM_FillRate/aie.mlir | 82 +- .../02_LM_SHIM_DDR_FillRate/aie.mlir | 95 +- test/benchmarks/03_Flood_DDR/aie.mlir | 1823 +++++++---------- .../aie/18_simple_shim_dma_routed/aie.mlir | 91 +- .../aie/20_shim_dma_broadcast/aie.mlir | 139 +- .../08_tile_locks/aie.mlir | 2 +- 6 files changed, 886 insertions(+), 1346 deletions(-) diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir index 3024f8cf47..0ef69a03c2 100644 --- a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir +++ b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir @@ -8,54 +8,56 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential -// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -// -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -// -ltest_lib %S/test.cpp -o test.elf RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %run_on_board ./test.elf module @benchmark01_DDR_SHIM_fill_rate { - % t70 = aie.tile(7, 0) % - t71 = aie.tile(7, 1) - //%t72 = aie.tile(7, 2) + %t70 = aie.tile(7, 0) + %t71 = aie.tile(7, 1) + //%t72 = aie.tile(7, 2) - % buffer = aie.external_buffer{sym_name = "buffer"} - : memref<7168xi32> + %buffer = aie.external_buffer {sym_name = "buffer" } : memref<7168xi32> - // Fixup - % sw = aie.switchbox(% t70){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux = aie.shim_mux(% t70){aie.connect < "DMA" : 0, "North" : 3 > } - - % swdma = - aie.switchbox(% t71){aie.connect < "South" : 3, "DMA" : 0 > } - - % dma = aie.shim_dma(% t70){ - % lock1 = aie.lock(% t70, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) + // Fixup + %sw = aie.switchbox(%t70) { + aie.connect<"South" : 3, "North" : 3> + } + %mux = aie.shim_mux(%t70) { + aie.connect<"DMA" : 0, "North": 3> + } - ^ bd0 : aie.use_lock(% lock1, Acquire, 1) - aie.dma_bd(% buffer - : memref<7168xi32>, 0, 7168) - aie.use_lock(% lock1, Release, 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } + %swdma = aie.switchbox(%t71) { + aie.connect<"South" : 3, "DMA" : 0> + } - % buf71_0 = aie.buffer(% t71){sym_name = "buf71_0"} - : memref<7168xi32> + %dma = aie.shim_dma(%t70) { + %lock1 = aie.lock(%t70, 1) - % l71_0 = aie.lock(% t71, 0) % l71_1 = - aie.lock(% t71, 1) + aie.dma_start(MM2S, 0, ^bd0, ^end) - % m71 = aie.mem(% t71) { - % srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^ - bd0 : aie.use_lock(% l71_0, "Acquire", 0) - aie.dma_bd(% buf71_0 - : memref<7168xi32>, 0, 7168) - aie.use_lock(% l71_0, "Release", 1) aie.next_bd ^ - end ^ end : aie.end + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end } + + %buf71_0 = aie.buffer(%t71) {sym_name = "buf71_0" } : memref<7168xi32> + + %l71_0 = aie.lock(%t71, 0) + %l71_1 = aie.lock(%t71, 1) + + %m71 = aie.mem(%t71) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l71_0, "Acquire", 0) + aie.dma_bd(%buf71_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l71_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } } diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir index 68e480da19..f3e9d7e051 100644 --- a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir +++ b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir @@ -8,62 +8,55 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential -// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -// -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -// -ltest_lib %S/test.cpp -o test.elf RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %run_on_board ./test.elf module @benchmark_02_LM2DDR { - % t70 = - aie.tile(7, 0) % t71 = - aie.tile(7, 1) - - % lock_a_ping = - aie.lock(% t71, 3) // a_ping - - % buf71_0 = - aie.buffer(% t71){sym_name = "buf71_0"} : memref<7168xi32> - - // Declare the buffers - % buffer_out = aie.external_buffer{sym_name = "buffer"} - : memref<7168xi32> - - % m71 = aie.mem(% t71){ - % srcDma = - aie.dma_start(MM2S, 1, ^bd0, ^end) ^ - bd0 : aie.use_lock(% lock_a_ping, "Acquire", 0) - aie.dma_bd(% buf71_0 - : memref<7168xi32>, 0, 7168) - aie.use_lock(% lock_a_ping, "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % - dma = aie.shim_dma(% t70){ - % lock1 = aie.lock(% t70, 2) + %t70 = aie.tile(7, 0) + %t71 = aie.tile(7, 1) + + %lock_a_ping = aie.lock(%t71, 3) // a_ping + + %buf71_0 = aie.buffer(%t71) {sym_name = "buf71_0" } : memref<7168xi32> + + //Declare the buffers + %buffer_out = aie.external_buffer {sym_name = "buffer" } : memref<7168xi32> + + %m71 = aie.mem(%t71) { + %srcDma = aie.dma_start(MM2S, 1, ^bd0, ^end) + ^bd0: + aie.use_lock(%lock_a_ping, "Acquire", 0) + aie.dma_bd(%buf71_0 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock_a_ping, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } - aie.dma_start(S2MM, 0, ^bd0, ^end) + %dma = aie.shim_dma(%t70) { + %lock1 = aie.lock(%t70, 2) - ^ bd0 : aie.use_lock(% lock1, Acquire, 1) - aie.dma_bd(% buffer_out - : memref<7168xi32>, 0, 7168) - aie.use_lock(% lock1, Release, 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } + aie.dma_start(S2MM, 0, ^bd0, ^end) - // Shim DMA connection to kernel - % sw2 = aie.switchbox(% t71){ - aie.connect < "DMA" : 1, - "South" : 2 > - } + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } - % sw1 = aie.switchbox( - % t70){ - aie.connect < "North" : 2, - "South" : 2 > - } % mux1 = aie.shim_mux(% t70) { + // Shim DMA connection to kernel + %sw2 = aie.switchbox(%t71){ + aie.connect<"DMA" : 1, "South" : 2> + } + + %sw1 = aie.switchbox(%t70) { + aie.connect<"North" : 2, "South" : 2> + } + %mux1 = aie.shim_mux (%t70) { aie.connect<"North" : 2, "DMA" : 0> } -} + +} \ No newline at end of file diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir index 25e1ab71f1..10e36b027c 100644 --- a/test/benchmarks/03_Flood_DDR/aie.mlir +++ b/test/benchmarks/03_Flood_DDR/aie.mlir @@ -8,1135 +8,708 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential -// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -// -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -// -ltest_lib %S/test.cpp -o test.elf RUN: %run_on_board ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %run_on_board ./test.elf module @benchmark03_Flood_DDR { - % t20 = aie.tile(2, 0) % t21 = aie.tile(2, 1) - - % sw2 = aie.switchbox(% t20){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux2 = aie.shim_mux(% t20){aie.connect < "DMA" : 0, "North" : 3 > } - - % swdma2 = aie.switchbox( - % t21){aie.connect < "South" : 3, "DMA" : 0 > } - - % buf21_0 = aie.buffer(% t21){sym_name = "buf21_0"} - : memref<7168xi32> % l21_0 = aie.lock(% t21, 0) - - % m21 = aie.mem(% t21){ - % srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) ^ - bd0 : aie.use_lock(% l21_0, "Acquire", 0) - aie.dma_bd(% buf21_0 - : memref<7168xi32>, 0, 7168) - aie.use_lock(% l21_0, "Release", 1) aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_20 = - aie.external_buffer{ - sym_name = "buffer_out_20"} - : memref<7168xi32> % l20 = aie.lock(% t20, 1) % dma20 = - aie.shim_dma(% t20){ - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^ - bd0 : aie.use_lock(% l20, Acquire, 1) - aie.dma_bd(% buffer_out_20 - : memref<7168xi32>, 0, - 7168) - aie.use_lock(% l20, Release, 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t30 = aie.tile(3, 0) % - t31 = aie.tile(3, 1) - - % sw3 = aie.switchbox(% t30){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux3 = aie.shim_mux(% t30){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma3 = - aie.switchbox(% t31){ - aie.connect < "South" : 3, - "DMA" : 0 > - } - - % buf31_0 = - aie.buffer(% t31){ - sym_name = - "buf31_0"} - : memref<7168xi32> % l31_0 = aie.lock(% t31, 0) - - % m31 = - aie.mem(% t31){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l31_0, - "Acquire", 0) - aie.dma_bd( - % buf31_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% l31_0, - "Release", - 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_30 = - aie.external_buffer{ - sym_name = "buffer_out_30"} - : memref<7168xi32> % dma30 = aie.shim_dma(% t30){ - % lock1 = - aie.lock(% t30, 1) - - aie.dma_start(MM2S, 0, - ^bd0, ^end) - - ^ - bd0 : aie - .use_lock(% lock1, Acquire, - 1) aie - .dma_bd(% buffer_out_30 - : memref<7168xi32>, - 0, 7168) aie - .use_lock(% lock1, Release, - 0) aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t60 = aie.tile(6, 0) % - t61 = aie.tile(6, 1) - - % sw6 = aie.switchbox(% t60){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux6 = aie.shim_mux(% t60){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma6 = - aie.switchbox(% t61){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf61_0 = - aie.buffer(% t61){ - sym_name = - "buf61_0"} - : memref<7168xi32> % l61_0 = aie.lock(% t61, 0) - - % m61 = - aie.mem(% t61){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l61_0, - "Acquire", 0) - aie.dma_bd( - % buf61_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% l61_0, - "Release", - 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_60 = - aie.external_buffer{ - sym_name = "buffer_out_60"} - : memref< - 7168xi32> % dma60 = aie - .shim_dma(% t60){ - % lock1 = - aie.lock(% t60, 1) - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^ - bd0 : aie - .use_lock(% lock1, Acquire, 1) aie - .dma_bd(% buffer_out_60 - : memref<7168xi32>, 0, - 7168) aie - .use_lock(% lock1, Release, - 0) aie.next_bd ^ - bd0 ^ - end : aie.end - } - - % t70 = - aie.tile(7, 0) % t71 = aie.tile(7, 1) - - % - sw = aie.switchbox(% - t70){ - aie.connect < - "South" : 3, - "North" : 3 > - } % mux = aie.shim_mux(% t70){ - aie.connect < "DMA" : - 0, - "North" : 3 > - } - - % - swdma = - aie.switchbox(% t71){ - aie.connect < "South" : 3, - "DMA" : 0 > - } - - % buf71_0 = - aie.buffer(% t71){ - sym_name = - "buf71_0"} : memref<7168xi32> - - % l71_0 = - aie.lock(% t71, 0) - - % - m71 = aie.mem(% t71){ - % srcDma = - aie.dma_start( - S2MM, 0, - ^bd0, - ^end) ^ - bd0 : aie - .use_lock( - % l71_0, - "Acquir" - "e", - 0) aie - .dma_bd( - % buf71_0 - : memref< - 7168xi32>, - 0, - 7168) - aie - .use_lock( - % l71_0, - "Releas" - "e", - 1) aie - .next_bd ^ - end ^ - end : aie.end - } - - % - buffer_out_70 = - aie.external_buffer{ - sym_name = - "bu" - "ff" - "er" - "_o" - "ut" - "_7" - "0"} - : memref<7168xi32> % dma70 = aie - .shim_dma(% t70){ - % lock1 = - aie.lock(% t70, 1) - - aie.dma_start(MM2S, 0, ^bd0, - ^end) - - ^ - bd0 : - aie.use_lock( - % lock1, Acquire, 1) - aie.dma_bd( - % buffer_out_70 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t100 = - aie.tile(10, 0) % t101 = - aie.tile(10, 1) - - % sw10 = - aie.switchbox(% t100){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux10 = - aie.shim_mux(% t100){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma10 = - aie.switchbox(% t101){ - aie.connect < "South" : - 3, - "DMA" : 0 > - } - - % buf101_0 = - aie.buffer(% t101){ - sym_name = - "buf101_0"} - : memref<7168xi32> - - % l101_0 = - aie.lock(% t101, - 0) - - % - m101 = aie.mem( - % - t101){ - % srcDma = - aie.dma_start( - S2MM, - 0, - ^bd0, - ^end) ^ - bd0 : aie - .use_lock( - % l101_0, - "A" - "c" - "q" - "u" - "i" - "r" - "e", - 0) - aie - .dma_bd( - % buf101_0 - : memref< - 7168xi32>, - 0, - 7168) - aie - .use_lock( - % l101_0, - "R" - "e" - "l" - "e" - "a" - "s" - "e", - 1) - aie - .next_bd ^ - end ^ - end : - aie.end - } - - % - buffer_out_100 = - aie.external_buffer{ - sym_name = - "buffer_out_100"} - : memref<7168xi32> % dma100 = aie - .shim_dma(% t100){ - % lock1 = - aie.lock(% t100, 1) - - aie.dma_start(MM2S, 0, ^bd0, - ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_100 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t110 = - aie.tile(11, 0) % t111 = - aie.tile(11, 1) - - % sw11 = - aie.switchbox(% t110){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux11 = - aie.shim_mux(% t110){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma11 = - aie.switchbox(% t111){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf111_0 = - aie.buffer(% t111){ - sym_name = - "buf111_0"} - : memref<7168xi32> % l111_0 = aie.lock(% t111, 0) - - % m111 = - aie.mem(% t111){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l111_0, - "Acquire", 0) - aie.dma_bd( - % buf111_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l111_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_110 = - aie.external_buffer{ - sym_name = "buffer_out_110"} - : memref<7168xi32> % dma110 = aie - .shim_dma(% t110){ - % lock1 = - aie.lock(% t110, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_110 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t180 = - aie.tile(18, 0) % t181 = - aie.tile(18, 1) - - % sw18 = - aie.switchbox(% t180){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux18 = - aie.shim_mux(% t180){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma18 = - aie.switchbox(% t181){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf181_0 = - aie.buffer(% t181){ - sym_name = - "buf181_0"} - : memref<7168xi32> % l181_0 = aie.lock(% t181, 0) - - % m181 = - aie.mem(% t181){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l181_0, - "Acquire", 0) - aie.dma_bd( - % buf181_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l181_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_180 = - aie.external_buffer{ - sym_name = "buffer_out_180"} - : memref<7168xi32> % dma180 = aie - .shim_dma(% t180){ - % lock1 = - aie.lock(% t180, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_180 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t190 = - aie.tile(19, 0) % t191 = - aie.tile(19, 1) - - % sw19 = - aie.switchbox(% t190){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux19 = - aie.shim_mux(% t190){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma19 = - aie.switchbox(% t191){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf191_0 = - aie.buffer(% t191){ - sym_name = - "buf191_0"} - : memref<7168xi32> % l191_0 = aie.lock(% t191, 0) - - % m191 = - aie.mem(% t191){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l191_0, - "Acquire", 0) - aie.dma_bd( - % buf191_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l191_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_190 = - aie.external_buffer{ - sym_name = "buffer_out_190"} - : memref<7168xi32> % dma190 = aie - .shim_dma(% t190){ - % lock1 = - aie.lock(% t190, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_190 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t260 = - aie.tile(26, 0) % t261 = - aie.tile(26, 1) - - % sw26 = - aie.switchbox(% t260){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux26 = - aie.shim_mux(% t260){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma26 = - aie.switchbox(% t261){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf261_0 = - aie.buffer(% t261){ - sym_name = - "buf261_0"} - : memref<7168xi32> % l261_0 = aie.lock(% t261, 0) - - % m261 = - aie.mem(% t261){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l261_0, - "Acquire", 0) - aie.dma_bd( - % buf261_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l261_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_260 = - aie.external_buffer{ - sym_name = "buffer_out_260"} - : memref<7168xi32> % dma260 = aie - .shim_dma(% t260){ - % lock1 = - aie.lock(% t260, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_260 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t270 = - aie.tile(27, 0) % t271 = - aie.tile(27, 1) - - % sw27 = - aie.switchbox(% t270){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux27 = - aie.shim_mux(% t270){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma27 = - aie.switchbox(% t271){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf271_0 = - aie.buffer(% t271){ - sym_name = - "buf271_0"} - : memref<7168xi32> % l271_0 = aie.lock(% t271, 0) - - % m271 = - aie.mem(% t271){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l271_0, - "Acquire", 0) - aie.dma_bd( - % buf271_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l271_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_270 = - aie.external_buffer{ - sym_name = "buffer_out_270"} - : memref<7168xi32> % dma270 = aie - .shim_dma(% t270){ - % lock1 = - aie.lock(% t270, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_270 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t340 = - aie.tile(34, 0) % t341 = - aie.tile(34, 1) - - % sw34 = - aie.switchbox(% t340){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux34 = - aie.shim_mux(% t340){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma34 = - aie.switchbox(% t341){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf341_0 = - aie.buffer(% t341){ - sym_name = - "buf341_0"} - : memref<7168xi32> % l341_0 = aie.lock(% t341, 0) - - % m341 = - aie.mem(% t341){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l341_0, - "Acquire", 0) - aie.dma_bd( - % buf341_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l341_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_340 = - aie.external_buffer{ - sym_name = "buffer_out_340"} - : memref<7168xi32> % dma340 = aie - .shim_dma(% t340){ - % lock1 = - aie.lock(% t340, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_340 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t350 = - aie.tile(35, 0) % t351 = - aie.tile(35, 1) - - % sw35 = - aie.switchbox(% t350){ - aie.connect < "South" : 3, - "North" : 3 > - } % - mux35 = - aie.shim_mux(% t350){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma35 = - aie.switchbox(% t351){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf351_0 = - aie.buffer(% t351){ - sym_name = - "buf351_0"} - : memref<7168xi32> % l351_0 = aie.lock(% t351, 0) - - % m351 = - aie.mem(% t351){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l351_0, - "Acquire", 0) - aie.dma_bd( - % buf351_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l351_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_350 = - aie.external_buffer{ - sym_name = "buffer_out_350"} - : memref<7168xi32> % dma350 = aie - .shim_dma(% t350){ - % lock1 = - aie.lock(% t350, 1) - - aie.dma_start( - MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, - 1) - aie.dma_bd( - % buffer_out_350 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, - 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % t420 = - aie.tile(42, 0) % t421 = - aie.tile(42, 1) - - % sw42 = - aie.switchbox(% t420){ - aie.connect < "South" : 3, - "North" : 3 > - } - - % buf421_0 = - aie.buffer(% t421){ - sym_name = "buf421_0"} - : memref<7168xi32> % l421 = aie.lock(% t421, 1) % m421 = - aie.mem(% t421){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, ^end) ^ - bd0 : - aie.use_lock(% l421, "Acquire", - 0) - aie.dma_bd( - % buf421_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% l421, - "Release", - 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_420 = - aie.external_buffer{ - sym_name = "buffer_out_420"} - : memref<7168xi32> % lock1 = aie.lock(% t420, 1) % dma420 = - aie.shim_dma(% t420){ - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% lock1, Acquire, 1) - aie.dma_bd(% buffer_out_420 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% lock1, - Release, 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % - t430 = aie.tile(43, 0) % - t431 = aie.tile(43, 1) - - % - sw43 = aie.switchbox(% - t430){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux43 = aie.shim_mux(% t430){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma43 = - aie.switchbox(% t431){ - aie.connect < "South" : - 3, - "DMA" : 0 > - } - - % buf431_0 = - aie.buffer(% t431){ - sym_name = - "buf431_0"} - : memref<7168xi32> % l431_0 = aie.lock(% t431, 0) - - % m431 = - aie.mem(% t431){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l431_0, - "Acquire", 0) - aie.dma_bd( - % buf431_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l431_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_430 = - aie.external_buffer{ - sym_name = "buffer_out_430"} - : memref<7168xi32> % l430 = aie.lock(% t430, 1) % dma430 = - aie.shim_dma(% t430){ - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% l430, Acquire, 1) - aie.dma_bd(% buffer_out_430 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% l430, - Release, 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % - t460 = aie.tile(46, 0) % - t461 = aie.tile(46, 1) - - % - sw46 = aie.switchbox(% - t460){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux46 = aie.shim_mux(% t460){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma46 = - aie.switchbox(% t461){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf461_0 = - aie.buffer(% t461){ - sym_name = - "buf461_0"} - : memref<7168xi32> % l461_0 = aie.lock(% t461, 0) - - % m461 = - aie.mem(% t461){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l461_0, - "Acquire", 0) - aie.dma_bd( - % buf461_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l461_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_460 = - aie.external_buffer{ - sym_name = "buffer_out_460"} - : memref<7168xi32> % l460 = aie.lock(% t460, 1) % dma460 = - aie.shim_dma(% t460){ - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^ - bd0 : - aie.use_lock(% l460, Acquire, 1) - aie.dma_bd(% buffer_out_460 - : memref<7168xi32>, - 0, 7168) - aie.use_lock(% l460, - Release, 0) - aie.next_bd ^ - bd0 ^ end : aie.end - } - - % - t470 = aie.tile(47, 0) % - t471 = aie.tile(47, 1) - - % - sw47 = aie.switchbox(% - t470){ - aie.connect < "South" : 3, - "North" : 3 > - } % mux47 = aie.shim_mux(% t470){ - aie.connect < "DMA" : 0, - "North" : 3 > - } - - % swdma47 = - aie.switchbox(% t471){ - aie.connect < - "South" : 3, - "DMA" : 0 > - } - - % buf471_0 = - aie.buffer(% t471){ - sym_name = - "buf471_0"} - : memref<7168xi32> % l471_0 = aie.lock(% t471, 0) - - % m471 = - aie.mem(% t471){ - % srcDma = - aie.dma_start(S2MM, 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l471_0, - "Acquire", 0) - aie.dma_bd( - % buf471_0 - : memref<7168xi32>, - 0, 7168) - aie.use_lock( - % l471_0, - "Release", 1) - aie.next_bd ^ - end ^ end : aie.end - } - - % buffer_out_470 = - aie.external_buffer{ - sym_name = "buffer_out_470"} - : memref<7168xi32> % l470 = aie.lock(% t470, 1) % dma470 = - aie.shim_dma(% t470) { + + %t20 = aie.tile(2, 0) + %t21 = aie.tile(2, 1) + + %sw2 = aie.switchbox(%t20) { + aie.connect<"South" : 3, "North" : 3> + } + %mux2 = aie.shim_mux(%t20) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma2 = aie.switchbox(%t21) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf21_0 = aie.buffer(%t21) {sym_name = "buf21_0" } : memref<7168xi32> + %l21_0 = aie.lock(%t21, 0) + + %m21 = aie.mem(%t21) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l21_0, "Acquire", 0) + aie.dma_bd(%buf21_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l21_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_20 = aie.external_buffer {sym_name = "buffer_out_20" } : memref<7168xi32> + %l20 = aie.lock(%t20, 1) + %dma20 = aie.shim_dma(%t20) { + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%l20, Acquire, 1) + aie.dma_bd(%buffer_out_20 : memref<7168xi32>, 0, 7168) + aie.use_lock(%l20, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t30 = aie.tile(3, 0) + %t31 = aie.tile(3, 1) + + %sw3 = aie.switchbox(%t30) { + aie.connect<"South" : 3, "North" : 3> + } + %mux3 = aie.shim_mux(%t30) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma3 = aie.switchbox(%t31) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf31_0 = aie.buffer(%t31) {sym_name = "buf31_0" } : memref<7168xi32> + %l31_0 = aie.lock(%t31, 0) + + %m31 = aie.mem(%t31) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l31_0, "Acquire", 0) + aie.dma_bd(%buf31_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l31_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_30 = aie.external_buffer {sym_name = "buffer_out_30" } : memref<7168xi32> + %dma30 = aie.shim_dma(%t30) { + %lock1 = aie.lock(%t30, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_30 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t60 = aie.tile(6, 0) + %t61 = aie.tile(6, 1) + + %sw6 = aie.switchbox(%t60) { + aie.connect<"South" : 3, "North" : 3> + } + %mux6 = aie.shim_mux(%t60) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma6 = aie.switchbox(%t61) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf61_0 = aie.buffer(%t61) {sym_name = "buf61_0" } : memref<7168xi32> + %l61_0 = aie.lock(%t61, 0) + + %m61 = aie.mem(%t61) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l61_0, "Acquire", 0) + aie.dma_bd(%buf61_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l61_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_60 = aie.external_buffer {sym_name = "buffer_out_60" } : memref<7168xi32> + %dma60 = aie.shim_dma(%t60) { + %lock1 = aie.lock(%t60, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_60 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t70 = aie.tile(7, 0) + %t71 = aie.tile(7, 1) + + + %sw = aie.switchbox(%t70) { + aie.connect<"South" : 3, "North" : 3> + } + %mux = aie.shim_mux(%t70) { + aie.connect<"DMA" : 0, "North": 3> + } + + + %swdma = aie.switchbox(%t71) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf71_0 = aie.buffer(%t71) {sym_name = "buf71_0" } : memref<7168xi32> + + %l71_0 = aie.lock(%t71, 0) + + %m71 = aie.mem(%t71) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l71_0, "Acquire", 0) + aie.dma_bd(%buf71_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l71_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_70 = aie.external_buffer {sym_name = "buffer_out_70" } : memref<7168xi32> + %dma70 = aie.shim_dma(%t70) { + %lock1 = aie.lock(%t70, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_70 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t100 = aie.tile(10, 0) + %t101 = aie.tile(10, 1) + + + %sw10 = aie.switchbox(%t100) { + aie.connect<"South" : 3, "North" : 3> + } + %mux10 = aie.shim_mux(%t100) { + aie.connect<"DMA" : 0, "North": 3> + } + + + %swdma10 = aie.switchbox(%t101) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf101_0 = aie.buffer(%t101) {sym_name = "buf101_0" } : memref<7168xi32> + + %l101_0 = aie.lock(%t101, 0) + + %m101 = aie.mem(%t101) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l101_0, "Acquire", 0) + aie.dma_bd(%buf101_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l101_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_100 = aie.external_buffer {sym_name = "buffer_out_100" } : memref<7168xi32> + %dma100 = aie.shim_dma(%t100) { + %lock1 = aie.lock(%t100, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_100 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t110 = aie.tile(11, 0) + %t111 = aie.tile(11, 1) + + %sw11 = aie.switchbox(%t110) { + aie.connect<"South" : 3, "North" : 3> + } + %mux11 = aie.shim_mux(%t110) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma11 = aie.switchbox(%t111) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf111_0 = aie.buffer(%t111) {sym_name = "buf111_0" } : memref<7168xi32> + %l111_0 = aie.lock(%t111, 0) + + %m111 = aie.mem(%t111) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l111_0, "Acquire", 0) + aie.dma_bd(%buf111_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l111_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_110 = aie.external_buffer {sym_name = "buffer_out_110" } : memref<7168xi32> + %dma110 = aie.shim_dma(%t110) { + %lock1 = aie.lock(%t110, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_110 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t180 = aie.tile(18, 0) + %t181 = aie.tile(18, 1) + + %sw18 = aie.switchbox(%t180) { + aie.connect<"South" : 3, "North" : 3> + } + %mux18 = aie.shim_mux(%t180) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma18 = aie.switchbox(%t181) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf181_0 = aie.buffer(%t181) {sym_name = "buf181_0" } : memref<7168xi32> + %l181_0 = aie.lock(%t181, 0) + + %m181 = aie.mem(%t181) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l181_0, "Acquire", 0) + aie.dma_bd(%buf181_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l181_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_180 = aie.external_buffer {sym_name = "buffer_out_180" } : memref<7168xi32> + %dma180 = aie.shim_dma(%t180) { + %lock1 = aie.lock(%t180, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_180 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + + %t190 = aie.tile(19, 0) + %t191 = aie.tile(19, 1) + + %sw19 = aie.switchbox(%t190) { + aie.connect<"South" : 3, "North" : 3> + } + %mux19 = aie.shim_mux(%t190) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma19 = aie.switchbox(%t191) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf191_0 = aie.buffer(%t191) {sym_name = "buf191_0" } : memref<7168xi32> + %l191_0 = aie.lock(%t191, 0) + + %m191 = aie.mem(%t191) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l191_0, "Acquire", 0) + aie.dma_bd(%buf191_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l191_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_190 = aie.external_buffer {sym_name = "buffer_out_190" } : memref<7168xi32> + %dma190 = aie.shim_dma(%t190) { + %lock1 = aie.lock(%t190, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_190 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t260 = aie.tile(26, 0) + %t261 = aie.tile(26, 1) + + %sw26 = aie.switchbox(%t260) { + aie.connect<"South" : 3, "North" : 3> + } + %mux26 = aie.shim_mux(%t260) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma26 = aie.switchbox(%t261) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf261_0 = aie.buffer(%t261) {sym_name = "buf261_0" } : memref<7168xi32> + %l261_0 = aie.lock(%t261, 0) + + %m261 = aie.mem(%t261) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l261_0, "Acquire", 0) + aie.dma_bd(%buf261_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l261_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_260 = aie.external_buffer {sym_name = "buffer_out_260" } : memref<7168xi32> + %dma260 = aie.shim_dma(%t260) { + %lock1 = aie.lock(%t260, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_260 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + + %t270 = aie.tile(27, 0) + %t271 = aie.tile(27, 1) + + %sw27 = aie.switchbox(%t270) { + aie.connect<"South" : 3, "North" : 3> + } + %mux27 = aie.shim_mux(%t270) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma27 = aie.switchbox(%t271) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf271_0 = aie.buffer(%t271) {sym_name = "buf271_0" } : memref<7168xi32> + %l271_0 = aie.lock(%t271, 0) + + %m271 = aie.mem(%t271) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l271_0, "Acquire", 0) + aie.dma_bd(%buf271_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l271_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_270 = aie.external_buffer {sym_name = "buffer_out_270" } : memref<7168xi32> + %dma270 = aie.shim_dma(%t270) { + %lock1 = aie.lock(%t270, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_270 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t340 = aie.tile(34, 0) + %t341 = aie.tile(34, 1) + + %sw34 = aie.switchbox(%t340) { + aie.connect<"South" : 3, "North" : 3> + } + %mux34 = aie.shim_mux(%t340) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma34 = aie.switchbox(%t341) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf341_0 = aie.buffer(%t341) {sym_name = "buf341_0" } : memref<7168xi32> + %l341_0 = aie.lock(%t341, 0) + + %m341 = aie.mem(%t341) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l341_0, "Acquire", 0) + aie.dma_bd(%buf341_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l341_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_340 = aie.external_buffer {sym_name = "buffer_out_340" } : memref<7168xi32> + %dma340 = aie.shim_dma(%t340) { + %lock1 = aie.lock(%t340, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_340 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t350 = aie.tile(35, 0) + %t351 = aie.tile(35, 1) + + %sw35 = aie.switchbox(%t350) { + aie.connect<"South" : 3, "North" : 3> + } + %mux35 = aie.shim_mux(%t350) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma35 = aie.switchbox(%t351) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf351_0 = aie.buffer(%t351) {sym_name = "buf351_0" } : memref<7168xi32> + %l351_0 = aie.lock(%t351, 0) + + %m351 = aie.mem(%t351) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l351_0, "Acquire", 0) + aie.dma_bd(%buf351_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l351_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_350 = aie.external_buffer {sym_name = "buffer_out_350" } : memref<7168xi32> + %dma350 = aie.shim_dma(%t350) { + %lock1 = aie.lock(%t350, 1) + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_350 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + + %t420 = aie.tile(42, 0) + %t421 = aie.tile(42, 1) + + %sw42 = aie.switchbox(%t420) { + aie.connect<"South" : 3, "North" : 3> + } + + %buf421_0 = aie.buffer(%t421) {sym_name = "buf421_0" } : memref<7168xi32> + %l421 = aie.lock(%t421, 1) + %m421 = aie.mem(%t421) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l421, "Acquire", 0) + aie.dma_bd(%buf421_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l421, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_420 = aie.external_buffer {sym_name = "buffer_out_420" } : memref<7168xi32> + %lock1 = aie.lock(%t420, 1) + %dma420 = aie.shim_dma(%t420) { + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer_out_420 : memref<7168xi32>, 0, 7168) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + %t430 = aie.tile(43, 0) + %t431 = aie.tile(43, 1) + + %sw43 = aie.switchbox(%t430) { + aie.connect<"South" : 3, "North" : 3> + } + %mux43 = aie.shim_mux(%t430) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma43 = aie.switchbox(%t431) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf431_0 = aie.buffer(%t431) {sym_name = "buf431_0" } : memref<7168xi32> + %l431_0 = aie.lock(%t431, 0) + + %m431 = aie.mem(%t431) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l431_0, "Acquire", 0) + aie.dma_bd(%buf431_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l431_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_430 = aie.external_buffer {sym_name = "buffer_out_430" } : memref<7168xi32> + %l430 = aie.lock(%t430, 1) + %dma430 = aie.shim_dma(%t430) { + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%l430, Acquire, 1) + aie.dma_bd(%buffer_out_430 : memref<7168xi32>, 0, 7168) + aie.use_lock(%l430, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + + %t460 = aie.tile(46, 0) + %t461 = aie.tile(46, 1) + + %sw46 = aie.switchbox(%t460) { + aie.connect<"South" : 3, "North" : 3> + } + %mux46 = aie.shim_mux(%t460) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma46 = aie.switchbox(%t461) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf461_0 = aie.buffer(%t461) {sym_name = "buf461_0" } : memref<7168xi32> + %l461_0 = aie.lock(%t461, 0) + + %m461 = aie.mem(%t461) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l461_0, "Acquire", 0) + aie.dma_bd(%buf461_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l461_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + %buffer_out_460 = aie.external_buffer {sym_name = "buffer_out_460" } : memref<7168xi32> + %l460 = aie.lock(%t460, 1) + %dma460 = aie.shim_dma(%t460) { + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%l460, Acquire, 1) + aie.dma_bd(%buffer_out_460 : memref<7168xi32>, 0, 7168) + aie.use_lock(%l460, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + + %t470 = aie.tile(47, 0) + %t471 = aie.tile(47, 1) + + %sw47 = aie.switchbox(%t470) { + aie.connect<"South" : 3, "North" : 3> + } + %mux47 = aie.shim_mux(%t470) { + aie.connect<"DMA" : 0, "North": 3> + } + + %swdma47 = aie.switchbox(%t471) { + aie.connect<"South" : 3, "DMA" : 0> + } + + %buf471_0 = aie.buffer(%t471) {sym_name = "buf471_0" } : memref<7168xi32> + %l471_0 = aie.lock(%t471, 0) + + %m471 = aie.mem(%t471) { + %srcDma = aie.dma_start(S2MM, 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l471_0, "Acquire", 0) + aie.dma_bd(%buf471_0 : memref< 7168xi32>, 0, 7168) + aie.use_lock(%l471_0, "Release", 1) + aie.next_bd ^end + ^end: + aie.end + } + + + %buffer_out_470 = aie.external_buffer {sym_name = "buffer_out_470" } : memref<7168xi32> + %l470 = aie.lock(%t470, 1) + %dma470 = aie.shim_dma(%t470) { aie.dma_start(MM2S, 0, ^bd0, ^end) - ^ bd0 : aie.use_lock(% l470, Acquire, 1) - aie.dma_bd(% buffer_out_470 - : memref<7168xi32>, 0, 7168) - aie.use_lock(% l470, Release, 0) aie.next_bd ^ - bd0 ^ end : aie.end + ^bd0: + aie.use_lock(%l470, Acquire, 1) + aie.dma_bd(%buffer_out_470 : memref<7168xi32>, 0, 7168) + aie.use_lock(%l470, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end } -} +} \ No newline at end of file diff --git a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir index b473b2e66b..2acd5ca60a 100644 --- a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir +++ b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir @@ -8,53 +8,50 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential -// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -// -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -// -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf RUN: -// %run_on_vck5000 ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %run_on_vck5000 ./test.elf module @test18_simple_shim_dma_routed { - % t70 = aie.tile(7, 0) % t72 = - aie.tile(7, 2) - - % buffer = - aie.external_buffer{sym_name = "input_buffer"} - : memref<512 x i32> % - lock1 = aie.lock(% t70, 1){sym_name = "input_lock"} - - % dma = aie.shim_dma(% t70){ - - aie.dma_start(MM2S, 0, ^bd0, ^end) - - ^ bd0 : aie.use_lock(% lock1, Acquire, 1) - aie.dma_bd(% buffer - : memref<512 x i32>, 0, 512) - aie.use_lock(% lock1, Release, 0) aie.next_bd ^ - bd0 ^ end : aie.end - } - - aie.flow(% t70, "DMA" : 0, % t72, "DMA" : 0) - - % buf72_0 = - aie.buffer(% t72){sym_name = "buf72_0"} - : memref<256xi32> % buf72_1 = aie.buffer(% t72){sym_name = "buf72_1"} - : memref<256xi32> - - % l72_0 = aie.lock(% t72, 0) % l72_1 = - aie.lock(% t72, 1) - - % m72 = aie.mem(% t72) { - % srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^ - bd0 : aie.use_lock(% l72_0, "Acquire", 0) - aie.dma_bd(% buf72_0 - : memref<256xi32>, 0, 256) - aie.use_lock(% l72_0, "Release", 1) aie.next_bd ^ - bd1 ^ - bd1 : aie.use_lock(% l72_1, "Acquire", 0) - aie.dma_bd(% buf72_1 - : memref<256xi32>, 0, 256) - aie.use_lock(% l72_1, "Release", 1) aie.next_bd ^ - bd0 ^ end : aie.end + %t70 = aie.tile(7, 0) + %t72 = aie.tile(7, 2) + + %buffer = aie.external_buffer {sym_name = "input_buffer" } : memref<512 x i32> + %lock1 = aie.lock(%t70, 1) {sym_name = "input_lock" } + + %dma = aie.shim_dma(%t70) { + + aie.dma_start(MM2S, 0, ^bd0, ^end) + + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } + + aie.flow(%t70, "DMA" : 0, %t72, "DMA" : 0) + + %buf72_0 = aie.buffer(%t72) {sym_name = "buf72_0" } : memref<256xi32> + %buf72_1 = aie.buffer(%t72) {sym_name = "buf72_1" } : memref<256xi32> + + %l72_0 = aie.lock(%t72, 0) + %l72_1 = aie.lock(%t72, 1) + + %m72 = aie.mem(%t72) { + %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l72_0, "Acquire", 0) + aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) + aie.use_lock(%l72_0, "Release", 1) + aie.next_bd ^bd1 + ^bd1: + aie.use_lock(%l72_1, "Acquire", 0) + aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) + aie.use_lock(%l72_1, "Release", 1) + aie.next_bd ^bd0 + ^end: + aie.end } -} +} \ No newline at end of file diff --git a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir index 0ea82afa51..4bf98e63a9 100644 --- a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir +++ b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir @@ -8,99 +8,74 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential -// --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -// -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -// -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf RUN: -// %run_on_vck5000 ./test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include %extraAieCcFlags% -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %run_on_vck5000 ./test.elf module @test20_shim_dma_broadcast { - % t70 = aie.tile(7, 0) % t72 = - aie.tile(7, 2) % t73 = - aie.tile(7, 3) + %t70 = aie.tile(7, 0) + %t72 = aie.tile(7, 2) + %t73 = aie.tile(7, 3) - % buffer = aie.external_buffer{sym_name = "input_buffer"} - : memref<512 x i32> % lock1 = aie.lock(% t70, 1){sym_name = "input_lock"} + %buffer = aie.external_buffer {sym_name = "input_buffer" } : memref<512 x i32> + %lock1 = aie.lock(%t70, 1) {sym_name = "input_lock" } - % dma = aie.shim_dma(% t70){ - aie.dma_start(MM2S, 0, ^bd0, ^end) + %dma = aie.shim_dma(%t70) { + aie.dma_start(MM2S, 0, ^bd0, ^end) - ^ bd0 : aie.use_lock(% lock1, Acquire, 1) - aie.dma_bd(% buffer - : memref<512 x i32>, 0, 512) - aie.use_lock(% lock1, Release, 0) aie.next_bd ^ - bd0 ^ end : aie.end - } + ^bd0: + aie.use_lock(%lock1, Acquire, 1) + aie.dma_bd(%buffer : memref<512 x i32>, 0, 512) + aie.use_lock(%lock1, Release, 0) + aie.next_bd ^bd0 + ^end: + aie.end + } - aie.flow(% t70, "DMA" : 0, % t72, - "DMA" : 0) + aie.flow(%t70, "DMA" : 0, %t72, "DMA" : 0) - % buf72_0 = - aie.buffer(% t72){sym_name = - "buf72_0"} - : memref<256xi32> % buf72_1 = aie.buffer(% t72){sym_name = "buf72_1"} - : memref<256xi32> + %buf72_0 = aie.buffer(%t72) {sym_name = "buf72_0" } : memref<256xi32> + %buf72_1 = aie.buffer(%t72) {sym_name = "buf72_1" } : memref<256xi32> - % l72_0 = - aie.lock(% t72, 0) % l72_1 = - aie.lock(% t72, 1) + %l72_0 = aie.lock(%t72, 0) + %l72_1 = aie.lock(%t72, 1) - % m72 = aie.mem(% t72){ - % srcDma = - aie.dma_start("S2MM", 0, ^bd0, - ^end) ^ - bd0 : - aie.use_lock(% l72_0, - "Acquire", - 0) aie - .dma_bd( - % buf72_0 - : memref<256xi32>, - 0, 256) aie - .use_lock(% l72_0, - "Release", - 1) - aie.next_bd ^ - bd1 ^ - bd1 : - aie.use_lock(% l72_1, - "Acquire", - 0) aie - .dma_bd( - % buf72_1 - : memref<256xi32>, - 0, 256) aie - .use_lock(% l72_1, - "Release", - 1) - aie.next_bd ^ - bd0 ^ end : aie.end - } + %m72 = aie.mem(%t72) { + %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l72_0, "Acquire", 0) + aie.dma_bd(%buf72_0 : memref<256xi32>, 0, 256) + aie.use_lock(%l72_0, "Release", 1) + aie.next_bd ^bd1 + ^bd1: + aie.use_lock(%l72_1, "Acquire", 0) + aie.dma_bd(%buf72_1 : memref<256xi32>, 0, 256) + aie.use_lock(%l72_1, "Release", 1) + aie.next_bd ^bd0 + ^end: + aie.end + } - aie.flow(% t70, "DMA" : 0, - % t73, "DMA" : 0) + aie.flow(%t70, "DMA" : 0, %t73, "DMA" : 0) - % buf73_0 = - aie.buffer(% t73){ - sym_name = - "buf73_0"} - : memref<256xi32> % buf73_1 = aie.buffer(% t73){sym_name = "buf73_1"} - : memref<256xi32> + %buf73_0 = aie.buffer(%t73) {sym_name = "buf73_0" } : memref<256xi32> + %buf73_1 = aie.buffer(%t73) {sym_name = "buf73_1" } : memref<256xi32> - % l73_0 = aie.lock(% t73, 0) % l73_1 = - aie.lock(% t73, 1) + %l73_0 = aie.lock(%t73, 0) + %l73_1 = aie.lock(%t73, 1) - % m73 = aie.mem(% t73) { - % srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) ^ - bd0 : aie.use_lock(% l73_0, "Acquire", 0) - aie.dma_bd(% buf73_0 - : memref<256xi32>, 0, 256) - aie.use_lock(% l73_0, "Release", 1) aie.next_bd ^ - bd1 ^ - bd1 : aie.use_lock(% l73_1, "Acquire", 0) - aie.dma_bd(% buf73_1 - : memref<256xi32>, 0, 256) - aie.use_lock(% l73_1, "Release", 1) aie.next_bd ^ - bd0 ^ end : aie.end + %m73 = aie.mem(%t73) { + %srcDma = aie.dma_start("S2MM", 0, ^bd0, ^end) + ^bd0: + aie.use_lock(%l73_0, "Acquire", 0) + aie.dma_bd(%buf73_0 : memref<256xi32>, 0, 256) + aie.use_lock(%l73_0, "Release", 1) + aie.next_bd ^bd1 + ^bd1: + aie.use_lock(%l73_1, "Acquire", 0) + aie.dma_bd(%buf73_1 : memref<256xi32>, 0, 256) + aie.use_lock(%l73_1, "Release", 1) + aie.next_bd ^bd0 + ^end: + aie.end } -} +} \ No newline at end of file diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index c28f87e766..7222f3e372 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -83,4 +83,4 @@ module @test_chess_08_tile_locks { ^end: aie.end } -} +} \ No newline at end of file From 9989149258e9dda33196483ac1626198766ac0e1 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 11:09:20 -0600 Subject: [PATCH 41/49] Error check messgae is not found, so added alloc-scheme to see if it helps --- test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index 7222f3e372..4abdfff0b4 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license, !hsa -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: aie.mlir.prj/aiesim.sh | FileCheck %s From ad7a10b66fcab647235275d184ed2c026e08b65c Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 11:11:32 -0600 Subject: [PATCH 42/49] Error with check message, so added alloc-scheme flag --- .../unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index df46768688..857b0b72d8 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license, !hsa -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s From 55c72209328a6eeec3d3b884ae3af5b66a5ab339 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 12:49:53 -0600 Subject: [PATCH 43/49] Revert "Error with check message, so added alloc-scheme flag" This reverts commit ad7a10b66fcab647235275d184ed2c026e08b65c. --- .../unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index 857b0b72d8..df46768688 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license, !hsa -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s From 34a3e0fcbd3e2acf4ac3de49501292e7ae250946 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 12:50:07 -0600 Subject: [PATCH 44/49] Revert "Error check messgae is not found, so added alloc-scheme to see if it helps" This reverts commit 9989149258e9dda33196483ac1626198766ac0e1. --- test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index 4abdfff0b4..7222f3e372 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license, !hsa -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: aie.mlir.prj/aiesim.sh | FileCheck %s From fc49e0b6b3887d91bb08a0f915e616cd88367c2f Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 14:05:19 -0600 Subject: [PATCH 45/49] Removing CHECK messages with address to check if that is the reason for failure of tests --- test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir | 4 ---- .../chess_compiler_tests_aie2/08_tile_locks/aie.mlir | 6 +----- 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index 7222f3e372..44d6c48500 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -18,18 +18,14 @@ // CHECK: after core start // CHECK: DMA [7, 3] // CHECK: BD 0 valid (Next BD: 1) -// CHECK: Transferring 2 32 bit words to/from byte address 006000 // CHECK: Acquires lock 0 with value 0 Releases lock 0 with value 1 currently Acquired 1 // CHECK: BD 1 valid (Last BD) // CHECK: * Current BD for mm2s channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 006010 // CHECK: Acquires lock 1 with value 0 Releases lock 1 with value 1 currently Acquired 1 // CHECK: BD 2 valid (Next BD: 3) -// CHECK: Transferring 2 32 bit words to/from byte address 006020 // CHECK: Acquires lock 2 with value 0 Releases lock 2 with value 1 currently Acquired 1 // CHECK: BD 3 valid (Last BD) // CHECK: * Current BD for s2mm channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 006030 // CHECK: Acquires lock 3 with value 0 Releases lock 3 with value 1 currently Acquired 1 // CHECK: Lock 0: Acquired 1 // CHECK: Lock 1: Acquired 1 diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index df46768688..f16eb7f2ed 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -10,7 +10,7 @@ //===----------------------------------------------------------------------===// // REQUIRES: valid_xchess_license, !hsa -// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py --aiesim --xchesscc --xbridge %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s -I%host_runtime_lib%/test_lib/include -L%host_runtime_lib%/test_lib/lib -ltest_lib %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf // RUN: sh -c 'aie.mlir.prj/aiesim.sh; exit 0' | FileCheck %s @@ -22,21 +22,17 @@ // CHECK: DMA [7, 3] AIE2 mm2s0 IDLE // CHECK: DMA [7, 3] AIE2 mm2s1 IDLE // CHECK: BD 0 valid (Next BD: 1) -// CHECK: Transferring 2 32 bit words to/from byte address 00C000 // CHECK: Acquires lock 0 with value -1 // CHECK: Releases lock 1 with value 1 // CHECK: BD 1 valid (Last BD) // CHECK: * Current BD for mm2s channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 00C010 // CHECK: Acquires lock 0 with value -1 // CHECK: Releases lock 1 with value 1 // CHECK: BD 2 valid (Next BD: 3) -// CHECK: Transferring 2 32 bit words to/from byte address 00C020 // CHECK: Acquires lock 2 with value -1 // CHECK: Releases lock 3 with value 1 // CHECK: BD 3 valid (Last BD) // CHECK: * Current BD for s2mm channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 00C030 // CHECK: Acquires lock 2 with value -1 // CHECK: Releases lock 3 with value 1 // CHECK: Core [7, 3] AIE2 locks are: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 From 04dcd7f41ea4946b5dfaee33ce27e4616caff8bf Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 14:43:58 -0600 Subject: [PATCH 46/49] Messages --- include/aie/Dialect/AIE/Transforms/AIEPasses.td | 2 +- lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index ef645a4c22..adec825d33 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -28,7 +28,7 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let options = [ Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", - "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, bank-aware is selected and if it fails, will fall back to basic-sequential scheme.">, + "Select allocation scheme:basic-sequential or bank-aware. Default is bank-aware, falling back to basic-sequential if it fails">, ]; } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index c49175f602..339940d39b 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -463,6 +463,7 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { + tile.emitWarning("Memory allocation scheme is either missing or unrecognized. By default, bank-aware is selected."); if (auto res = simpleBankAwareAllocation(tile); res.failed()) { if (auto res2 = basicAllocation(tile); res2.failed()) return signalPassFailure(); From e155c24153277ab838ce3afde9a63b539fa99ab7 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 14:44:33 -0600 Subject: [PATCH 47/49] Revert "Messages" This reverts commit 04dcd7f41ea4946b5dfaee33ce27e4616caff8bf. --- include/aie/Dialect/AIE/Transforms/AIEPasses.td | 2 +- lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index adec825d33..ef645a4c22 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -28,7 +28,7 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let options = [ Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", - "Select allocation scheme:basic-sequential or bank-aware. Default is bank-aware, falling back to basic-sequential if it fails">, + "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, bank-aware is selected and if it fails, will fall back to basic-sequential scheme.">, ]; } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 339940d39b..c49175f602 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -463,7 +463,6 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { - tile.emitWarning("Memory allocation scheme is either missing or unrecognized. By default, bank-aware is selected."); if (auto res = simpleBankAwareAllocation(tile); res.failed()) { if (auto res2 = basicAllocation(tile); res2.failed()) return signalPassFailure(); From 33c659a73c4d0149639a55935d598e3214f0e8ff Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 14:48:45 -0600 Subject: [PATCH 48/49] Messages --- include/aie/Dialect/AIE/Transforms/AIEPasses.td | 2 +- lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index ef645a4c22..b608bb47dd 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -28,7 +28,7 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let options = [ Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", - "Choose allocation scheme; possibilities: basic-sequential, bank-aware. By default, bank-aware is selected and if it fails, will fall back to basic-sequential scheme.">, + "Select allocation scheme: basic-sequential or bank-aware. Default is bank-aware, falling back to basic-sequential if it fails.">, ]; } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index c49175f602..bdc167c58f 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -463,6 +463,8 @@ struct AIEAssignBufferAddressesPass } } else { for (auto tile : device.getOps()) { + tile.emitWarning("Memory allocation scheme is either missing or " + "unrecognized. By default, bank-aware is selected."); if (auto res = simpleBankAwareAllocation(tile); res.failed()) { if (auto res2 = basicAllocation(tile); res2.failed()) return signalPassFailure(); From 5420b862b03aa5c33da48ea6d3f0790df612d703 Mon Sep 17 00:00:00 2001 From: Pranathi Vasireddy Date: Thu, 19 Sep 2024 16:32:24 -0600 Subject: [PATCH 49/49] Using sequential allocation --- programming_examples/ml/bottleneck/Makefile | 2 +- programming_examples/ml/resnet/layers_conv2_x/Makefile | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/programming_examples/ml/bottleneck/Makefile b/programming_examples/ml/bottleneck/Makefile index b6b8caa8cc..1af113732f 100755 --- a/programming_examples/ml/bottleneck/Makefile +++ b/programming_examples/ml/bottleneck/Makefile @@ -32,7 +32,7 @@ build/conv2dk1_skip.o: conv2dk1_skip.cc xchesscc -d ${CHESSCC2_FLAGS} -DINT8_ACT -c $< -o $@ build/final.xclbin: build/${mlirFileName}.mlir build/conv2dk1.o build/conv2dk3.o build/conv2dk1_skip.o - cd build && aiecc.py -v --aie-generate-cdo --aie-generate-npu --no-compile-host \ + cd build && aiecc.py -v --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential \ --xclbin-name=${@F} --npu-insts-name=insts.txt ${