diff --git a/include/aie-c/TargetModel.h b/include/aie-c/TargetModel.h index 3248618795f..60a91bedf45 100644 --- a/include/aie-c/TargetModel.h +++ b/include/aie-c/TargetModel.h @@ -137,6 +137,9 @@ aieTargetModelGetNumMemTileRows(AieTargetModel targetModel); MLIR_CAPI_EXPORTED uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel); +MLIR_CAPI_EXPORTED uint32_t +aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, int row); + /// Returns true if this is an NPU target model. MLIR_CAPI_EXPORTED bool aieTargetModelIsNPU(AieTargetModel targetModel); diff --git a/include/aie/Dialect/AIE/IR/AIETargetModel.h b/include/aie/Dialect/AIE/IR/AIETargetModel.h index c685376f2f3..493d1849459 100644 --- a/include/aie/Dialect/AIE/IR/AIETargetModel.h +++ b/include/aie/Dialect/AIE/IR/AIETargetModel.h @@ -181,6 +181,8 @@ class AIETargetModel { virtual uint32_t getNumMemTileRows() const = 0; /// Return the size (in bytes) of a MemTile. virtual uint32_t getMemTileSize() const = 0; + /// Return the number of memory banks of a given tile. + virtual uint32_t getNumBanks(int col, int row) const = 0; /// Return the number of destinations of connections inside a switchbox. These /// are the targets of connect operations in the switchbox. virtual uint32_t getNumDestSwitchboxConnections(int col, int row, @@ -268,6 +270,7 @@ class AIE1TargetModel : public AIETargetModel { } uint32_t getNumMemTileRows() const override { return 0; } uint32_t getMemTileSize() const override { return 0; } + uint32_t getNumBanks(int col, int row) const override { return 4; } uint32_t getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const override; @@ -342,6 +345,10 @@ class AIE2TargetModel : public AIETargetModel { uint32_t getMemTileSize() const override { return 0x00080000; } + uint32_t getNumBanks(int col, int row) const override { + return isMemTile(col, row) ? 8 : 4; + } + uint32_t getNumDestSwitchboxConnections(int col, int row, WireBundle bundle) const override; uint32_t getNumSourceSwitchboxConnections(int col, int row, diff --git a/include/aie/Dialect/AIE/Transforms/AIEPasses.td b/include/aie/Dialect/AIE/Transforms/AIEPasses.td index 8453c4cd0c4..82a01c163f7 100644 --- a/include/aie/Dialect/AIE/Transforms/AIEPasses.td +++ b/include/aie/Dialect/AIE/Transforms/AIEPasses.td @@ -27,8 +27,8 @@ def AIEAssignBufferAddresses : Pass<"aie-assign-buffer-addresses", "DeviceOp"> { let constructor = "xilinx::AIE::createAIEAssignBufferAddressesPass()"; let options = [ - Option<"clBasicAlloc", "basic-alloc", "bool", /*default=*/"false", - "Flag to enable the basic sequential allocation scheme (not bank-aware)."> + Option<"clAllocScheme", "alloc-scheme", "std::string", /*default=*/"", + "Select allocation scheme: basic-sequential or bank-aware. Default is bank-aware, falling back to basic-sequential if it fails.">, ]; } diff --git a/lib/CAPI/TargetModel.cpp b/lib/CAPI/TargetModel.cpp index b609c9abc2a..2eb51059173 100644 --- a/lib/CAPI/TargetModel.cpp +++ b/lib/CAPI/TargetModel.cpp @@ -149,6 +149,11 @@ uint32_t aieTargetModelGetMemTileSize(AieTargetModel targetModel) { return unwrap(targetModel).getMemTileSize(); } +uint32_t aieTargetModelGetNumBanks(AieTargetModel targetModel, int col, + int row) { + return unwrap(targetModel).getNumBanks(col, row); +} + bool aieTargetModelIsNPU(AieTargetModel targetModel) { return unwrap(targetModel).isNPU(); } diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index d76d738e426..752cb58b6b5 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -53,7 +53,7 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int address, return success(); } -LogicalResult basicAllocation(TileOp &tile) { +LogicalResult basicAllocation(TileOp tile) { auto device = tile->getParentOfType(); if (!device) return failure(); @@ -113,14 +113,6 @@ typedef struct BankLimits { int64_t endAddr; } BankLimits; -// TODO: add to target model -int getNumBanks(TileOp tile) { - if (tile.isMemTile()) - return 1; - else - return 4; -} - // Function that given a number of banks and their size, computes // the start and end addresses for each bank and fills in the entry // in the bankLimits vector. @@ -195,34 +187,86 @@ bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, return false; } +// Prints the memory map across banks +void printMemMap(TileOp tile, SmallVector allocatedBuffers, + SmallVector preAllocatedBuffers, int numBanks, + std::vector &bankLimits, int stacksize) { + InFlightDiagnostic error = tile.emitOpError( + "Not all requested buffers fit in the available memory.\n"); + auto ¬e = error.attachNote() + << "Current configuration of buffers in bank(s) : "; + note << "MemoryMap:\n"; + auto printbuffer = [&](StringRef name, int address, int size) { + note << "\t" + << "\t" << name << " \t" + << ": 0x" << llvm::utohexstr(address) << "-0x" + << llvm::utohexstr(address + size - 1) << " \t(" << size + << " bytes)\n"; + }; + for (int i = 0; i < numBanks; i++) { + if (i == 0) { + if (stacksize > 0) + printbuffer("(stack)", 0, stacksize); + else + note << "(no stack allocated)\n"; + } + note << "\t" + << "bank : " << i << "\t" + << "0x" << llvm::utohexstr(bankLimits[i].startAddr) << "-0x" + << llvm::utohexstr(bankLimits[i].endAddr - 1) << "\n"; + for (auto buffer : preAllocatedBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + for (auto buffer : allocatedBuffers) { + auto addr = buffer.getAddress().value(); + auto mem_bank = buffer.getMemBank().value(); + if (mem_bank == i) + printbuffer(buffer.name(), addr, buffer.getAllocationSize()); + } + } +} + // Function that given a buffer will iterate over all the memory banks // starting from the given index to try and find a bank with enough // space. If it does, it will set the buffer's address and mem_bank // attributes and update the nextAddrInBanks vector. -// If it does not find one with enough space, it will allocate the -// buffer in the last checked bank (this will be picked up during -// overflow error checking). Finally, the function returns the index -// of the next bank to search (which should be given to subsequent -// calls of this function to ensure a round-robin allocation scheme -// over the available banks). +// If it does not find one with enough space, it will throw an error. +// Returns true if the buffer was successfully allocated, false otherwise. +// If no bank has enough space to accommodate the buffer, an error is emitted. + int setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, std::vector &nextAddrInBanks, std::vector &bankLimits) { assert(startBankIndex < numBanks && "Unexpected input value for startBankIndex"); int bankIndex = startBankIndex; + bool allocated = false; for (int i = 0; i < numBanks; i++) { int64_t startAddr = nextAddrInBanks[bankIndex]; int64_t endAddr = startAddr + buffer.getAllocationSize(); - if (endAddr <= bankLimits[bankIndex].endAddr || i == numBanks - 1) { + if (endAddr <= bankLimits[bankIndex].endAddr) { buffer.setMemBank(bankIndex); setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); - bankIndex = (bankIndex + 1) % numBanks; + allocated = true; + bankIndex++; + bankIndex %= numBanks; break; } - bankIndex = (bankIndex + 1) % numBanks; + // Move to the next bank + bankIndex++; + bankIndex %= numBanks; + } + // If no bank has enough space, throws error + if (!allocated) { + buffer.emitError("Failed to allocate buffer: ") + << buffer.name() << " with size: " << buffer.getAllocationSize() + << " bytes."; + return false; } - return bankIndex; + return true; } LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, @@ -275,6 +319,14 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, return success(); } +// Function to deallocate attributes of buffers in case of a failure +void deAllocationBuffers(SmallVector &buffers) { + for (auto buffer : buffers) { + buffer->removeAttr("address"); + buffer->removeAttr("mem_bank"); + } +} + LogicalResult simpleBankAwareAllocation(TileOp tile) { auto device = tile->getParentOfType(); if (!device) @@ -295,7 +347,7 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { else maxDataMemorySize = targetModel.getLocalMemorySize(); - int numBanks = getNumBanks(tile); + int numBanks = targetModel.getNumBanks(tile.getCol(), tile.getRow()); int bankSize = maxDataMemorySize / numBanks; // Address range owned by the MemTile is 0x80000. @@ -312,6 +364,7 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { fillBankLimits(numBanks, bankSize, bankLimits); SmallVector buffersToAlloc; + SmallVector preAllocatedBuffers; SmallVector allBuffers; // Collect all the buffers for this tile. device.walk([&](BufferOp buffer) { @@ -331,6 +384,8 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { nextAddrInBanks, bankLimits); if (!has_addr && !has_bank) buffersToAlloc.push_back(buffer); + else + preAllocatedBuffers.push_back(buffer); } } @@ -341,10 +396,24 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { }); // Set addresses for remaining buffers. + SmallVector allocatedBuffers; int bankIndex = 0; - for (auto buffer : buffersToAlloc) - bankIndex = setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, - bankLimits); + for (auto buffer : buffersToAlloc) { + // If the buffer doesn't fit in any of the bank space then + // it prints the current memory map of the banks, + // deallocates all the buffers, and + // returns a failure. + if (!setBufferAddress(buffer, numBanks, bankIndex, nextAddrInBanks, + bankLimits)) { + + printMemMap(tile, allocatedBuffers, preAllocatedBuffers, numBanks, + bankLimits, stacksize); + deAllocationBuffers(allocatedBuffers); + return failure(); + } else { + allocatedBuffers.push_back(buffer); + } + } // Sort by smallest address before printing memory map. std::sort(allBuffers.begin(), allBuffers.end(), [](BufferOp a, BufferOp b) { @@ -380,16 +449,25 @@ struct AIEAssignBufferAddressesPass }); // Select allocation scheme - if (clBasicAlloc) { + if (clAllocScheme == "basic-sequential") { for (auto tile : device.getOps()) { if (auto res = basicAllocation(tile); res.failed()) return signalPassFailure(); } - } else { + } else if (clAllocScheme == "bank-aware") { for (auto tile : device.getOps()) { if (auto res = simpleBankAwareAllocation(tile); res.failed()) return signalPassFailure(); } + } else { + for (auto tile : device.getOps()) { + tile.emitWarning("Memory allocation scheme is either not provided or " + "unrecognized. Defaulting to bank-aware allocation."); + if (auto res = simpleBankAwareAllocation(tile); res.failed()) { + if (auto res2 = basicAllocation(tile); res2.failed()) + return signalPassFailure(); + } + } } } }; diff --git a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp index 1a731a5b7ea..5cb98dd22ec 100644 --- a/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp +++ b/lib/Targets/AIEVecToCpp/TranslateAIEVecToCpp.cpp @@ -3470,4 +3470,4 @@ LogicalResult aievec::translateAIEVecToCpp(Operation *op, bool aie2, raw_ostream &os) { CppEmitter emitter(os, false, aie2); return emitter.emitOperation(*op, /*trailingSemicolon=*/false); -} +} \ No newline at end of file diff --git a/programming_examples/ml/bottleneck/Makefile b/programming_examples/ml/bottleneck/Makefile index 3c997a3f660..1d0fe565715 100755 --- a/programming_examples/ml/bottleneck/Makefile +++ b/programming_examples/ml/bottleneck/Makefile @@ -37,7 +37,7 @@ build/conv2dk1_skip.o: conv2dk1_skip.cc build/final.xclbin: build/${mlirFileName}.mlir build/conv2dk1.o build/conv2dk3.o build/conv2dk1_skip.o mkdir -p ${@D} cd ${@D} && aiecc.py -v --aie-generate-cdo --aie-generate-npu --no-compile-host \ - --basic-alloc-scheme \ + --alloc-scheme=basic-sequential \ --no-xchesscc --no-xbridge \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) diff --git a/programming_examples/ml/resnet/layers_conv2_x/Makefile b/programming_examples/ml/resnet/layers_conv2_x/Makefile index 2f4c6194b62..400005faddd 100755 --- a/programming_examples/ml/resnet/layers_conv2_x/Makefile +++ b/programming_examples/ml/resnet/layers_conv2_x/Makefile @@ -44,9 +44,10 @@ build/conv2dk1_skip.o: conv2dk1_skip.cc build/final.xclbin: build/${mlirFileName}.mlir build/conv2dk1_i8.o build/conv2dk1_skip_init.o build/conv2dk3.o build/conv2dk1_skip.o build/conv2dk1_ui8.o mkdir -p ${@D} - cd ${@D} && aiecc.py --basic-alloc-scheme --aie-generate-cdo --aie-generate-npu --no-compile-host \ + cd ${@D} && aiecc.py --alloc-scheme=basic-sequential --aie-generate-cdo --aie-generate-npu --no-compile-host \ --no-xchesscc --no-xbridge \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) + clean: rm -rf build log diff --git a/programming_examples/vision/color_detect/Makefile b/programming_examples/vision/color_detect/Makefile index d4ced3a74af..55f5dd586e4 100755 --- a/programming_examples/vision/color_detect/Makefile +++ b/programming_examples/vision/color_detect/Makefile @@ -41,7 +41,7 @@ build/aie2_lineBased_8b_${COLORDETECT_WIDTH}.mlir: ${srcdir}/aie2_colorDetect.py build/final_${COLORDETECT_WIDTH}.xclbin: build/aie2_lineBased_8b_${COLORDETECT_WIDTH}.mlir build/rgba2hue.cc.o build/threshold.cc.o build/combined_bitwiseOR_gray2rgba_bitwiseAND.a mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential \ --no-xchesscc --no-xbridge \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) diff --git a/programming_examples/vision/color_threshold/Makefile b/programming_examples/vision/color_threshold/Makefile index 56841203df3..b998ed762ac 100644 --- a/programming_examples/vision/color_threshold/Makefile +++ b/programming_examples/vision/color_threshold/Makefile @@ -34,7 +34,7 @@ build/aie2_${COLORTHRESHOLD_WIDTH}.mlir: ${srcdir}/aie2_colorThreshold.py build/final_${COLORTHRESHOLD_WIDTH}.xclbin: build/aie2_${COLORTHRESHOLD_WIDTH}.mlir build/threshold.cc.o mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential \ --no-xchesscc --no-xbridge \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) diff --git a/programming_examples/vision/edge_detect/Makefile b/programming_examples/vision/edge_detect/Makefile index 37106a9c072..8921dfc79da 100755 --- a/programming_examples/vision/edge_detect/Makefile +++ b/programming_examples/vision/edge_detect/Makefile @@ -41,7 +41,7 @@ build/aie2_lineBased_8b_${EDGEDETECT_WIDTH}.mlir: ${srcdir}/aie2_edgeDetect.py build/final_${EDGEDETECT_WIDTH}.xclbin: build/aie2_lineBased_8b_${EDGEDETECT_WIDTH}.mlir build/rgba2gray.cc.o build/gray2rgba.cc.o build/filter2d.cc.o build/threshold.cc.o build/addWeighted.cc.o build/combined_gray2rgba_addWeighted.a mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential \ --no-xchesscc --no-xbridge \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) diff --git a/programming_examples/vision/vision_passthrough/Makefile b/programming_examples/vision/vision_passthrough/Makefile index 874a89e8f92..93fd48ef38e 100644 --- a/programming_examples/vision/vision_passthrough/Makefile +++ b/programming_examples/vision/vision_passthrough/Makefile @@ -34,7 +34,7 @@ build/passThrough.cc.o: passThrough.cc build/final_${PASSTHROUGH_WIDTH}.xclbin: build/aie2_lineBased_8b_${PASSTHROUGH_WIDTH}.mlir build/passThrough.cc.o mkdir -p ${@D} - cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme \ + cd ${@D} && aiecc.py --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential \ --no-xchesscc --no-xbridge \ --xclbin-name=${@F} --npu-insts-name=insts.txt $(<:%=../%) diff --git a/python/compiler/aiecc/cl_arguments.py b/python/compiler/aiecc/cl_arguments.py index ff6a44e06ec..f8ac91e5ed2 100644 --- a/python/compiler/aiecc/cl_arguments.py +++ b/python/compiler/aiecc/cl_arguments.py @@ -145,11 +145,10 @@ def parse_args(args=None): help="Disable linking of AIE code", ) parser.add_argument( - "--basic-alloc-scheme", - dest="basic_alloc_scheme", - default=False, - action="store_true", - help="Use basic memory allocation scheme for AIE buffer address assignment", + "--alloc-scheme", + dest="alloc_scheme", + default=None, + help="Allocation scheme for AIE buffers: basic-sequential, bank-aware (default).", ) parser.add_argument( "--generate-ctrl-pkt-overlay", diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index 6845481b4f1..6deb4f49fdd 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -35,7 +35,7 @@ from aie.passmanager import PassManager INPUT_WITH_ADDRESSES_PIPELINE = ( - lambda basic_alloc_scheme=False, dynamic_objFifos=False, ctrl_pkt_overlay=False: ( + lambda scheme="", dynamic_objFifos=False, ctrl_pkt_overlay=False: ( Pipeline() .lower_affine() .add_pass("aie-canonicalize-device") @@ -56,7 +56,7 @@ "aie-generate-column-control-overlay", route_shim_to_tile_ctrl=ctrl_pkt_overlay, ) - .add_pass("aie-assign-buffer-addresses", basic_alloc=basic_alloc_scheme), + .add_pass("aie-assign-buffer-addresses", alloc_scheme=scheme), ) .convert_scf_to_cf() ) @@ -1061,9 +1061,14 @@ async def run_flow(self): ) file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") - pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( - opts.basic_alloc_scheme, opts.dynamic_objFifos, opts.ctrl_pkt_overlay - ).materialize(module=True) + + if opts.alloc_scheme: + pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( + opts.alloc_scheme, opts.dynamic_objFifos, opts.ctrl_pkt_overlay + ).materialize(module=True) + else: + pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE().materialize(module=True) + run_passes( pass_pipeline, self.mlir_module_str, diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index 77b7996d76d..a22dbde1c21 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_error.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,18 +8,22 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s -// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory -// CHECK: Error in bank(s) : 3 -// CHECK: MemoryMap: -// CHECK: bank : 0 0x0-0x1FFF -// CHECK: (stack) : 0x0-0x3FF (1024 bytes) -// CHECK: c : 0x400-0x41F (32 bytes) -// CHECK: bank : 1 0x2000-0x3FFF -// CHECK: a : 0x2000-0x200F (16 bytes) -// CHECK: bank : 2 0x4000-0x5FFF -// CHECK: bank : 3 0x6000-0x7FFF -// CHECK: b : 0x6000-0xDFFF (32768 bytes) +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "b" with size: 32768 bytes. +// CHECK: %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> +// CHECK: ^ +// CHECK: note: see current operation: %2 = "aie.buffer"(%0) <{sym_name = "b"}> : (index) -> memref<8192xi32> +// CHECK: error: 'aie.tile' op Not all requested buffers fit in the available memory. + +// CHECK: %0 = aie.tile(3, 3) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row = 3 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (stack) : 0x0-0x3FF (1024 bytes) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: bank : 3 0x6000-0x7FFF module @test { aie.device(xcvc1902) { @@ -36,4 +40,4 @@ module @test { aie.end } } -} +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir index d8381a9437b..44968d6d676 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memory_exhausted.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,12 +8,35 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --verify-diagnostics --aie-assign-buffer-addresses=basic-alloc=0 %s +// RUN: not aie-opt --aie-assign-bd-ids --aie-assign-buffer-addresses %s + +// CHECK: error: Failed to allocate buffer: "_anonymous0" with size: 24576 bytes. +// CHECK: %C_L1L2_0_0_buff_0 = aie.buffer(%tile_0_2) : memref<64x96xf32> +// CHECK: ^ +// CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "_anonymous0"}> : (index) -> memref<64x96xf32> +// CHECK: error: 'aie.tile' op Not all requested buffers fit in the available memory. + +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 0 : i32, row = 2 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x3FFF +// CHECK: bank : 1 0x4000-0x7FFF +// CHECK: bank : 2 0x8000-0xBFFF +// CHECK: bank : 3 0xC000-0xFFFF + +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory: Sequential +// CHECK: (no stack allocated) + +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 0 : i32, row = 2 : i32}> : () -> index +// CHECK: _anonymous0 : 0x0-0x5FFF (24576 bytes) +// CHECK: _anonymous1 : 0x6000-0xBFFF (24576 bytes) +// CHECK: _anonymous2 : 0xC000-0xD7FF (6144 bytes) +// CHECK: _anonymous3 : 0xD800-0xEFFF (6144 bytes) +// CHECK: _anonymous4 : 0xF000-0xFFFF (4096 bytes) +// CHECK: _anonymous5 : 0x10000-0x10FFF (4096 bytes) module { aie.device(npu1_2col) { - // expected-error@+2 {{allocated buffers exceeded available memory}} - // expected-note@+1 {{}} %tile_0_2 = aie.tile(0, 2) %C_L1L2_0_0_buff_0 = aie.buffer(%tile_0_2) : memref<64x96xf32> %C_L1L2_0_0_buff_1 = aie.buffer(%tile_0_2) : memref<64x96xf32> diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index 7c639528d4c..929d1d43aea 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -1,4 +1,4 @@ -//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memtile_error.mlir ---------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,12 +8,26 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s -// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory -// CHECK: Error in bank(s) : 0 -// CHECK: MemoryMap: -// CHECK: bank : 0 0x0-0x7FFFF -// CHECK: a : 0x0-0x80E7F (528000 bytes) +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "a" with size: 528000 bytes. +// CHECK: %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> +// CHECK: ^ +// CHECK: note: see current operation: %1 = "aie.buffer"(%0) <{sym_name = "a"}> : (index) -> memref<132000xi32> +// CHECK: error: 'aie.tile' op Not all requested buffers fit in the available memory. + +// CHECK: %0 = aie.tile(3, 1) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 3 : i32, row = 1 : i32}> : () -> index +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0xFFFF +// CHECK: bank : 1 0x10000-0x1FFFF +// CHECK: bank : 2 0x20000-0x2FFFF +// CHECK: bank : 3 0x30000-0x3FFFF +// CHECK: bank : 4 0x40000-0x4FFFF +// CHECK: bank : 5 0x50000-0x5FFFF +// CHECK: bank : 6 0x60000-0x6FFFF +// CHECK: bank : 7 0x70000-0x7FFFF module @test { @@ -24,4 +38,4 @@ module @test { aie.end } } -} +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir index aee7b03b918..292291ef9ce 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -1,4 +1,4 @@ -//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memtile_simple.mlir --------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,15 +8,15 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<65536xi32> +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s 2>&1 | FileCheck %s +// CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16384xi32> module @test { aie.device(xcve2302) { %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16384xi32> aie.memtile_dma(%0) { aie.end } } -} +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index 84812a14c80..6724123b4b9 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_simple.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,11 +8,13 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses %s | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 16384 : i32, mem_bank = 2 : i32, sym_name = "a"} : memref<16xi8> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 8192 : i32, mem_bank = 1 : i32, sym_name = "c"} : memref<16xi16> -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=bank-aware" %s | FileCheck %s +// CHECK: %a = aie.buffer(%tile_3_3) {address = 3104 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16xi8> +// CHECK: %b = aie.buffer(%tile_3_3) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "b"} : memref<512xi32> +// CHECK: %c = aie.buffer(%tile_3_3) {address = 3072 : i32, mem_bank = 0 : i32, sym_name = "c"} : memref<16xi16> +// CHECK: %_anonymous0 = aie.buffer(%tile_4_4) {address = 1024 : i32, mem_bank = 0 : i32, sym_name = "_anonymous0"} : memref<500xi32> + + module @test { aie.device(xcvc1902) { @@ -29,4 +31,4 @@ module @test { aie.end } } -} +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/basic_alloc_error.mlir b/test/assign-buffer-addresses/basic_alloc_error.mlir index 9c2d85f4f35..7cc1db9a1aa 100644 --- a/test/assign-buffer-addresses/basic_alloc_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_error.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- basic_alloc_error.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory // CHECK: (stack) : 0x0-0x3FF (1024 bytes) // CHECK: b : 0x400-0x83FF (32768 bytes) diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir index b179f8e8420..7aaba2b3d65 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir @@ -1,4 +1,4 @@ -//===- memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- basic_alloc_memtile_error.mlir ---------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: not aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s +// RUN: not aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory module @test { diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index ef468d1e635..d140f23521d 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -1,4 +1,4 @@ -//===- memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- basic_alloc_memtile_simple.mlir --------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,9 +8,16 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="basic-alloc" %s 2>&1 | FileCheck %s -// CHECK: {{.*}} aie.buffer({{.*}}) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> - +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s 2>&1 | FileCheck %s +// CHECK: module @test { +// CHECK: aie.device(xcve2302) { +// CHECK: %tile_3_1 = aie.tile(3, 1) +// CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, sym_name = "a"} : memref<65536xi32> +// CHECK: %memtile_dma_3_1 = aie.memtile_dma(%tile_3_1) { +// CHECK: aie.end +// CHECK: } +// CHECK: } +// CHECK: } module @test { aie.device(xcve2302) { %0 = aie.tile(3, 1) diff --git a/test/assign-buffer-addresses/basic_alloc_simple.mlir b/test/assign-buffer-addresses/basic_alloc_simple.mlir index 51254e4f419..f866c76eae4 100644 --- a/test/assign-buffer-addresses/basic_alloc_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_simple.mlir @@ -1,4 +1,4 @@ -//===- simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- basic_alloc_simple.mlir ---------------------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: aie-opt --aie-assign-buffer-addresses="basic-alloc" %s | FileCheck %s +// RUN: aie-opt --aie-assign-buffer-addresses="alloc-scheme=basic-sequential" %s | FileCheck %s // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3104 : i32, sym_name = "a"} : memref<16xi8> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "b"} : memref<512xi32> // CHECK: {{.*}} aie.buffer({{.*}}) {address = 3072 : i32, sym_name = "c"} : memref<16xi16> diff --git a/test/assign-buffer-addresses/fallback_routine_error.mlir b/test/assign-buffer-addresses/fallback_routine_error.mlir new file mode 100644 index 00000000000..3aae18e27f2 --- /dev/null +++ b/test/assign-buffer-addresses/fallback_routine_error.mlir @@ -0,0 +1,37 @@ +//===- fallback_routine_error.mlir ---------------------------------------------*- MLIR -*-===// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: not aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "act_3_4_buff_2" with size: 2048 bytes. +// CHECK: note: see current operation: %10 = "aie.buffer"(%0) <{sym_name = "act_3_4_buff_2"}> : (index) -> memref<512xi32> +// CHECK: error: 'aie.tile' op Not all requested buffers fit in the available memory. + +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ + +// CHECK: error: 'aie.tile' op allocated buffers exceeded available memory +// CHECK: (no stack allocated) + +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: see current operation: %0 = "aie.tile"() <{col = 1 : i32, row = 2 : i32}> : () -> index + +module @test { + aie.device(xcvc1902) { + %tile12 = aie.tile(1, 2) + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<1024xi32> //8192 bytes + %2 = aie.buffer(%tile12) { sym_name = "b" } : memref<2048xi32> //8192 bytes + %3 = aie.buffer(%tile12) { sym_name = "c" } : memref<2048xi32> //8192 bytes + %4 = aie.buffer(%tile12) { sym_name = "d" } : memref<1024xi32> //4096 bytes + %5 = aie.buffer(%tile12) { sym_name = "e" } : memref<1024xi32> //4096 bytes + %6 = aie.buffer(%tile12) { sym_name = "f" } : memref<256xi16> //32 bytes + %tile13 = aie.tile(1, 3) + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1024 bytes + } +} \ No newline at end of file diff --git a/test/assign-buffer-addresses/fallback_routine_simple.mlir b/test/assign-buffer-addresses/fallback_routine_simple.mlir new file mode 100644 index 00000000000..511605ea43b --- /dev/null +++ b/test/assign-buffer-addresses/fallback_routine_simple.mlir @@ -0,0 +1,52 @@ +//===- fallback_routine_simple.mlir ---------------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-objectFifo-stateful-transform --aie-assign-buffer-addresses %s 2>&1 | FileCheck %s +// CHECK: error: Failed to allocate buffer: "a" with size: 16384 bytes. +// CHECK: %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes +// CHECK: ^ +// CHECK: error: 'aie.tile' op Not all requested buffers fit in the available memory. + +// CHECK: %tile12 = aie.tile(1, 2) +// CHECK: ^ +// CHECK: note: Current configuration of buffers in bank(s) : MemoryMap: +// CHECK: (no stack allocated) +// CHECK: bank : 0 0x0-0x1FFF +// CHECK: bank : 1 0x2000-0x3FFF +// CHECK: bank : 2 0x4000-0x5FFF +// CHECK: bank : 3 0x6000-0x7FFF + +// CHECK: module @test { +// CHECK: aie.device(xcvc1902) { +// CHECK: memref.global "public" @act_3_4 : memref<8xi32> +// CHECK: %tile_1_2 = aie.tile(1, 2) +// CHECK: %a = aie.buffer(%tile_1_2) {address = 0 : i32, sym_name = "a"} : memref<4096xi32> +// CHECK: %b = aie.buffer(%tile_1_2) {address = 16384 : i32, sym_name = "b"} : memref<16xi16> +// CHECK: %tile_1_3 = aie.tile(1, 3) +// CHECK: %act_3_4_buff_0 = aie.buffer(%tile_1_2) {address = 16416 : i32, sym_name = "act_3_4_buff_0"} : memref<8xi32> +// CHECK: %act_3_4_buff_1 = aie.buffer(%tile_1_2) {address = 16448 : i32, sym_name = "act_3_4_buff_1"} : memref<8xi32> +// CHECK: %act_3_4_buff_2 = aie.buffer(%tile_1_2) {address = 16480 : i32, sym_name = "act_3_4_buff_2"} : memref<8xi32> +// CHECK: %act_3_4_buff_3 = aie.buffer(%tile_1_2) {address = 16512 : i32, sym_name = "act_3_4_buff_3"} : memref<8xi32> +// CHECK: %act_3_4_lock_0 = aie.lock(%tile_1_2, 0) {init = 0 : i32, sym_name = "act_3_4_lock_0"} +// CHECK: %act_3_4_lock_1 = aie.lock(%tile_1_2, 1) {init = 0 : i32, sym_name = "act_3_4_lock_1"} +// CHECK: %act_3_4_lock_2 = aie.lock(%tile_1_2, 2) {init = 0 : i32, sym_name = "act_3_4_lock_2"} +// CHECK: %act_3_4_lock_3 = aie.lock(%tile_1_2, 3) {init = 0 : i32, sym_name = "act_3_4_lock_3"} +// CHECK: } +// CHECK: } + +module @test { + aie.device(xcvc1902) { + %tile12 = aie.tile(1, 2) + %1 = aie.buffer(%tile12) { sym_name = "a" } : memref<4096xi32> //16384 bytes + %b1 = aie.buffer(%tile12) { sym_name = "b" } : memref<16xi16> //32 bytes + %tile13 = aie.tile(1, 3) + aie.objectfifo @act_3_4(%tile12, {%tile13}, 4 : i32) : !aie.objectfifo> //4x1 bytes + } +} diff --git a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir old mode 100755 new mode 100644 index dfc08007da9..0c9a497ae91 --- a/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir +++ b/test/benchmarks/01_DDR_SHIM_LM_FillRate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark01_DDR_SHIM_fill_rate { @@ -61,4 +61,3 @@ module @benchmark01_DDR_SHIM_fill_rate { aie.end } } - diff --git a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir old mode 100755 new mode 100644 index 378fa63059c..7fe61b1da36 --- a/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir +++ b/test/benchmarks/02_LM_SHIM_DDR_FillRate/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark_02_LM2DDR { @@ -59,4 +59,4 @@ module @benchmark_02_LM2DDR { aie.connect<"North" : 2, "DMA" : 0> } -} +} \ No newline at end of file diff --git a/test/benchmarks/03_Flood_DDR/aie.mlir b/test/benchmarks/03_Flood_DDR/aie.mlir old mode 100755 new mode 100644 index 63f0722bb46..c5d97484700 --- a/test/benchmarks/03_Flood_DDR/aie.mlir +++ b/test/benchmarks/03_Flood_DDR/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %S/test.cpp -o test.elf // RUN: %run_on_board ./test.elf module @benchmark03_Flood_DDR { @@ -712,4 +712,4 @@ module @benchmark03_Flood_DDR { ^end: aie.end } -} +} \ No newline at end of file diff --git a/test/generate-mmap/allocation_error.mlir b/test/generate-mmap/allocation_error.mlir index c682562e15b..9650cf7e69d 100644 --- a/test/generate-mmap/allocation_error.mlir +++ b/test/generate-mmap/allocation_error.mlir @@ -9,34 +9,38 @@ //===----------------------------------------------------------------------===// // REQUIRES: peano, aietools_aie -// RUN: not aiecc.py --basic-alloc-scheme --no-xchesscc --no-xbridge %s 2>&1 | FileCheck %s --check-prefix=PEANO +// RUN: not aiecc.py --alloc-scheme=basic-sequential --no-xchesscc --no-xbridge %s 2>&1 | FileCheck %s --check-prefix=PEANO // PEANO: ld.lld: error: section '.bss' will not fit in region 'data': overflowed by 4 bytes -// If we use all of the local memory, then linking the AIE executable should fail. -// The fundamental problem here is that we can stuff things in the executable that -// aren't visibla at the MLIR level, so the assign-buffer-addresses pass can't generate -// a good error message. +// If we use all of the local memory, then linking the AIE executable should +// fail. The fundamental problem here is that we can stuff things in the +// executable that aren't visibla at the MLIR level, so the +// assign-buffer-addresses pass can't generate a good error message. module @example0 { - aie.device(xcvc1902) { - memref.global @x : memref<4xi8> = uninitialized - func.func @test (%i: index, %v: i8) -> i8 { - %x = memref.get_global @x : memref<4xi8> - memref.store %v, %x[%i] : memref<4xi8> - %r = memref.load %x[%i] : memref<4xi8> - func.return %r : i8 - } + aie.device(xcvc1902) { + memref.global @x : memref<4xi8> = + uninitialized func.func @test(% i + : index, % v + : i8) + ->i8 { + % x = memref.get_global @x : memref<4xi8> memref.store % v, + % x[% i] : memref<4xi8> % r = + memref.load % x[% i] : memref<4xi8> func.return % r : i8 + } - %t33 = aie.tile(3, 3) + % t33 = aie.tile(3, 3) - // Use all the local memory for buffers, combined with the 1024 byte stack size. - %buf33 = aie.buffer(%t33) : memref<31744xi8> + // Use all the local memory for buffers, combined with the 1024 byte + // stack size. + % buf33 = aie.buffer(% t33) + : memref<31744xi8> - %c33 = aie.core(%t33) { - %idx1 = arith.constant 3 : index - %val1 = arith.constant 7 : i8 - memref.store %val1, %buf33[%idx1] : memref<31744xi8> - func.call @test(%idx1, %val1) : (index, i8) -> i8 - aie.end + % c33 = aie.core(% t33) { + % idx1 = arith.constant 3 : index % val1 = + arith.constant 7 : i8 memref.store % val1, + % buf33[% idx1] : memref<31744xi8> + func.call @test(% idx1, % val1) + : (index, i8)->i8 aie.end + } } - } } diff --git a/test/generate-mmap/allocation_error_chess.mlir b/test/generate-mmap/allocation_error_chess.mlir index 90362ea4b9e..1c5b17404ab 100644 --- a/test/generate-mmap/allocation_error_chess.mlir +++ b/test/generate-mmap/allocation_error_chess.mlir @@ -9,34 +9,38 @@ //===----------------------------------------------------------------------===// // REQUIRES: chess, aietools_aie -// RUN: not aiecc.py --basic-alloc-scheme --xchesscc --xbridge %s 2>&1 | FileCheck %s --check-prefix=CHESS +// RUN: not aiecc.py --alloc-scheme=basic-sequential --xchesscc --xbridge %s 2>&1 | FileCheck %s --check-prefix=CHESS // CHESS: Error: could not find free space for SpaceSymbol x in memory DMb -// If we use all of the local memory, then linking the AIE executable should fail. -// The fundamental problem here is that we can stuff things in the executable that -// aren't visibla at the MLIR level, so the assign-buffer-addresses pass can't generate -// a good error message. +// If we use all of the local memory, then linking the AIE executable should +// fail. The fundamental problem here is that we can stuff things in the +// executable that aren't visibla at the MLIR level, so the +// assign-buffer-addresses pass can't generate a good error message. module @example0 { - aie.device(xcvc1902) { - memref.global @x : memref<4xi8> = uninitialized - func.func @test (%i: index, %v: i8) -> i8 { - %x = memref.get_global @x : memref<4xi8> - memref.store %v, %x[%i] : memref<4xi8> - %r = memref.load %x[%i] : memref<4xi8> - func.return %r : i8 - } + aie.device(xcvc1902) { + memref.global @x : memref<4xi8> = + uninitialized func.func @test(% i + : index, % v + : i8) + ->i8 { + % x = memref.get_global @x : memref<4xi8> memref.store % v, + % x[% i] : memref<4xi8> % r = + memref.load % x[% i] : memref<4xi8> func.return % r : i8 + } - %t33 = aie.tile(3, 3) + % t33 = aie.tile(3, 3) - // Use all the local memory for buffers, combined with the 1024 byte stack size. - %buf33 = aie.buffer(%t33) : memref<31744xi8> + // Use all the local memory for buffers, combined with the 1024 byte + // stack size. + % buf33 = aie.buffer(% t33) + : memref<31744xi8> - %c33 = aie.core(%t33) { - %idx1 = arith.constant 3 : index - %val1 = arith.constant 7 : i8 - memref.store %val1, %buf33[%idx1] : memref<31744xi8> - func.call @test(%idx1, %val1) : (index, i8) -> i8 - aie.end + % c33 = aie.core(% t33) { + % idx1 = arith.constant 3 : index % val1 = + arith.constant 7 : i8 memref.store % val1, + % buf33[% idx1] : memref<31744xi8> + func.call @test(% idx1, % val1) + : (index, i8)->i8 aie.end + } } - } } diff --git a/test/npu-xrt/add_blockwrite/run.lit b/test/npu-xrt/add_blockwrite/run.lit index 0d76390b3b8..52b72f70448 100644 --- a/test/npu-xrt/add_blockwrite/run.lit +++ b/test/npu-xrt/add_blockwrite/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_maskwrite/run.lit b/test/npu-xrt/add_maskwrite/run.lit index 0d76390b3b8..52b72f70448 100644 --- a/test/npu-xrt/add_maskwrite/run.lit +++ b/test/npu-xrt/add_maskwrite/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_one_ctrl_packet/run.lit b/test/npu-xrt/add_one_ctrl_packet/run.lit index 2c08faa9579..81d333bfd40 100644 --- a/test/npu-xrt/add_one_ctrl_packet/run.lit +++ b/test/npu-xrt/add_one_ctrl_packet/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit b/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit index acc723cb04c..c015674ff2f 100644 --- a/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit +++ b/test/npu-xrt/add_one_ctrl_packet_4_cores/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall -lrt -lstdc++ %xrt_flags %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/add_one_ctrl_packet_col_overlay/aie.mlir b/test/npu-xrt/add_one_ctrl_packet_col_overlay/aie.mlir index 26e509c78fe..0bb576a7f40 100644 --- a/test/npu-xrt/add_one_ctrl_packet_col_overlay/aie.mlir +++ b/test/npu-xrt/add_one_ctrl_packet_col_overlay/aie.mlir @@ -374,4 +374,4 @@ module { aiex.npu.dma_wait {symbol = @out3} } } -} +} \ No newline at end of file diff --git a/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit b/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit index 36cb1172a4c..b073de91b0a 100644 --- a/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit +++ b/test/npu-xrt/add_one_ctrl_packet_col_overlay/run.lit @@ -3,8 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --generate-ctrl-pkt-overlay --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --generate-ctrl-pkt-overlay --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! - diff --git a/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp b/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp index ccfef64dc2c..ea176b2e0c3 100644 --- a/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp +++ b/test/npu-xrt/add_one_ctrl_packet_col_overlay/test.cpp @@ -211,4 +211,4 @@ int main(int argc, const char *argv[]) { std::cout << "\nfailed.\n\n"; return 1; } -} +} \ No newline at end of file diff --git a/test/npu-xrt/add_one_using_dma/run.lit b/test/npu-xrt/add_one_using_dma/run.lit index 0d76390b3b8..52b72f70448 100644 --- a/test/npu-xrt/add_one_using_dma/run.lit +++ b/test/npu-xrt/add_one_using_dma/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/vec_vec_add_memtile_init/run.lit b/test/npu-xrt/vec_vec_add_memtile_init/run.lit index 2c08faa9579..81d333bfd40 100644 --- a/test/npu-xrt/vec_vec_add_memtile_init/run.lit +++ b/test/npu-xrt/vec_vec_add_memtile_init/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/npu-xrt/vec_vec_add_tile_init/run.lit b/test/npu-xrt/vec_vec_add_tile_init/run.lit index 2c08faa9579..81d333bfd40 100644 --- a/test/npu-xrt/vec_vec_add_tile_init/run.lit +++ b/test/npu-xrt/vec_vec_add_tile_init/run.lit @@ -3,7 +3,7 @@ // // REQUIRES: ryzen_ai // -// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --basic-alloc-scheme --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir +// RUN: %python aiecc.py --no-aiesim --aie-generate-cdo --aie-generate-npu --no-compile-host --alloc-scheme=basic-sequential --xclbin-name=aie.xclbin --npu-insts-name=insts.txt %S/aie.mlir // RUN: clang %S/test.cpp -o test.exe -std=c++11 -Wall %xrt_flags -lrt -lstdc++ %test_utils_flags // RUN: %run_on_npu ./test.exe -x aie.xclbin -k MLIR_AIE -i insts.txt | FileCheck %s // CHECK: PASS! diff --git a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir index f997375df54..8b8395bb233 100644 --- a/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir +++ b/test/unit_tests/aie/18_simple_shim_dma_routed/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %extraAieCcFlags% %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %extraAieCcFlags% %S/test.cpp -o test.elf // RUN: %run_on_vck5000 ./test.elf module @test18_simple_shim_dma_routed { @@ -54,4 +54,4 @@ module @test18_simple_shim_dma_routed { ^end: aie.end } -} +} \ No newline at end of file diff --git a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir index bbccafaaa77..d7f845f0a6c 100644 --- a/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir +++ b/test/unit_tests/aie/20_shim_dma_broadcast/aie.mlir @@ -8,7 +8,7 @@ // //===----------------------------------------------------------------------===// -// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --basic-alloc-scheme --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %extraAieCcFlags% %S/test.cpp -o test.elf +// RUN: %PYTHON aiecc.py %VitisSysrootFlag% --alloc-scheme=basic-sequential --host-target=%aieHostTargetTriplet% %link_against_hsa% %s %test_lib_flags %extraAieCcFlags% %S/test.cpp -o test.elf // RUN: %run_on_vck5000 ./test.elf module @test20_shim_dma_broadcast { @@ -78,4 +78,4 @@ module @test20_shim_dma_broadcast { ^end: aie.end } -} +} \ No newline at end of file diff --git a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir index df4821ce2a3..64d35f3b0b6 100644 --- a/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests/08_tile_locks/aie.mlir @@ -18,18 +18,18 @@ // CHECK: after core start // CHECK: DMA [7, 3] // CHECK: BD 0 valid (Next BD: 1) -// CHECK: Transferring 2 32 bit words to/from byte address 006000 +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: Acquires lock 0 with value 0 Releases lock 0 with value 1 currently Acquired 1 // CHECK: BD 1 valid (Last BD) // CHECK: * Current BD for mm2s channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 006010 +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: Acquires lock 1 with value 0 Releases lock 1 with value 1 currently Acquired 1 // CHECK: BD 2 valid (Next BD: 3) -// CHECK: Transferring 2 32 bit words to/from byte address 006020 +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: Acquires lock 2 with value 0 Releases lock 2 with value 1 currently Acquired 1 // CHECK: BD 3 valid (Last BD) // CHECK: * Current BD for s2mm channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 006030 +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: Acquires lock 3 with value 0 Releases lock 3 with value 1 currently Acquired 1 // CHECK: Lock 0: Acquired 1 // CHECK: Lock 1: Acquired 1 diff --git a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir index 51ca1c910b3..34499fb1ea6 100644 --- a/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir +++ b/test/unit_tests/chess_compiler_tests_aie2/08_tile_locks/aie.mlir @@ -21,21 +21,21 @@ // CHECK: DMA [7, 3] AIE2 mm2s0 IDLE // CHECK: DMA [7, 3] AIE2 mm2s1 IDLE // CHECK: BD 0 valid (Next BD: 1) -// CHECK: Transferring 2 32 bit words to/from byte address 00C000 +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: Acquires lock 0 with value -1 // CHECK: Releases lock 1 with value 1 // CHECK: BD 1 valid (Last BD) +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: * Current BD for mm2s channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 00C010 // CHECK: Acquires lock 0 with value -1 // CHECK: Releases lock 1 with value 1 // CHECK: BD 2 valid (Next BD: 3) -// CHECK: Transferring 2 32 bit words to/from byte address 00C020 +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: Acquires lock 2 with value -1 // CHECK: Releases lock 3 with value 1 // CHECK: BD 3 valid (Last BD) +// CHECK: Transferring 2 32 bit words to/from byte address // CHECK: * Current BD for s2mm channel 0 -// CHECK: Transferring 2 32 bit words to/from byte address 00C030 // CHECK: Acquires lock 2 with value -1 // CHECK: Releases lock 3 with value 1 // CHECK: Core [7, 3] AIE2 locks are: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0