diff --git a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp index 752cb58b6b..61f50ccf30 100644 --- a/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp +++ b/lib/Dialect/AIE/Transforms/AIEAssignBuffers.cpp @@ -26,7 +26,7 @@ using namespace xilinx::AIE; //===----------------------------------------------------------------------===// LogicalResult checkAndPrintOverflow(TileOp tile, int address, int maxDataMemorySize, int stacksize, - SmallVector buffers) { + SmallVector &buffers) { if (address > maxDataMemorySize) { InFlightDiagnostic error = tile.emitOpError("allocated buffers exceeded available memory\n"); @@ -65,17 +65,30 @@ LogicalResult basicAllocation(TileOp tile) { else maxDataMemorySize = targetModel.getLocalMemorySize(); - SmallVector buffers; - // Collect all the buffers for this tile. + SmallVector buffers; + SmallVector allocated_buffers; + // Collect all the buffers for this tile. If the buffer has an address, add + // it to allocated_buffers. Otherwise, add it to buffers. device.walk([&](BufferOp buffer) { - if (buffer.getTileOp() == tile) - buffers.push_back(buffer); + if (buffer.getTileOp() == tile) { + if (buffer.getAddress()) + allocated_buffers.push_back(buffer); + else + buffers.push_back(buffer); + } }); - // Sort by allocation size. + + // Sort buffers by allocation size. std::sort(buffers.begin(), buffers.end(), [](BufferOp a, BufferOp b) { return a.getAllocationSize() > b.getAllocationSize(); }); + // Sort allocated_buffers by address + std::sort(allocated_buffers.begin(), allocated_buffers.end(), + [](BufferOp a, BufferOp b) { + return a.getAddress().value() < b.getAddress().value(); + }); + // Address range owned by the MemTile is 0x80000. // Address range owned by the tile is 0x8000 in // AIE1 and 0x10000 in AIE2, but we need room at @@ -87,9 +100,18 @@ LogicalResult basicAllocation(TileOp tile) { address += stacksize; } + // As the next address to allocate is assigned, skip over any buffers + // from the allocated_buffers list. + auto current_alloc = allocated_buffers.begin(); for (auto buffer : buffers) { - if (buffer.getAddress()) - buffer->emitWarning("Overriding existing address"); + assert(!buffer.getAddress()); + while (current_alloc != allocated_buffers.end() && + address + buffer.getAllocationSize() > + current_alloc->getAddress().value()) { + address = current_alloc->getAddress().value() + + current_alloc->getAllocationSize(); + current_alloc++; + } buffer.setAddress(address); address += buffer.getAllocationSize(); } @@ -142,25 +164,29 @@ void setAndUpdateAddressInBank(BufferOp buffer, int64_t start_addr, // returns true and if not, the function emits a warning that the address // will be overwritten and returns false (which will cause the buffer to be // added to the list of buffers without addresses, to be completed later on). -bool checkAndAddBufferWithAddress(BufferOp buffer, int numBanks, - std::vector &nextAddrInBanks, - std::vector &bankLimits) { - if (auto addrAttr = buffer->getAttrOfType("address")) { - int addr = addrAttr.getInt(); - for (int i = 0; i < numBanks; i++) { - if (bankLimits[i].startAddr <= addr && addr < bankLimits[i].endAddr) { - if (addr >= nextAddrInBanks[i]) { - nextAddrInBanks[i] = addr + buffer.getAllocationSize(); - buffer.setMemBank(i); - } else { - buffer->emitWarning("Overriding existing address"); - return false; - } - } - } - return true; +FailureOr +checkAndAddBufferWithAddress(BufferOp buffer, int numBanks, + std::vector &nextAddrInBanks, + std::vector &bankLimits) { + auto addrAttr = buffer->getAttrOfType("address"); + if (!addrAttr) + return false; + + int addr = addrAttr.getInt(); + for (int i = 0; i < numBanks; i++) { + // if the address is not within the bank, continue + if (addr < bankLimits[i].startAddr || addr >= bankLimits[i].endAddr) + continue; + + // if the allocator already allocated this address, fail + if (addr < nextAddrInBanks[i]) + return buffer->emitOpError("would override allocated address"); + + // the allocator can accomadate this existing allocation + nextAddrInBanks[i] = addr + buffer.getAllocationSize(); + buffer.setMemBank(i); } - return false; + return true; } // Function that checks whether the given buffer already has a set mem_bank @@ -169,27 +195,26 @@ bool checkAndAddBufferWithAddress(BufferOp buffer, int numBanks, // function emits a warning that the mem_bank will be overwritten and returns // false (which will cause the buffer to be added to the list of buffers // without addresses, to be completed later on). -bool checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, - std::vector &nextAddrInBanks, - std::vector &bankLimits) { - if (auto memBankAttr = buffer->getAttrOfType("mem_bank")) { - int mem_bank = memBankAttr.getInt(); - int64_t startAddr = nextAddrInBanks[mem_bank]; - int64_t endAddr = startAddr + buffer.getAllocationSize(); - if (endAddr <= bankLimits[mem_bank].endAddr) { - setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); - } else { - buffer->emitWarning("Overriding existing mem_bank"); - return false; - } - return true; - } - return false; +FailureOr +checkAndAddBufferWithMemBank(BufferOp buffer, int numBanks, + std::vector &nextAddrInBanks, + std::vector &bankLimits) { + auto memBankAttr = buffer->getAttrOfType("mem_bank"); + if (!memBankAttr) + return false; + + int mem_bank = memBankAttr.getInt(); + int64_t startAddr = nextAddrInBanks[mem_bank]; + int64_t endAddr = startAddr + buffer.getAllocationSize(); + if (endAddr > bankLimits[mem_bank].endAddr) + return buffer->emitOpError("would override existing mem_bank"); + setAndUpdateAddressInBank(buffer, startAddr, endAddr, nextAddrInBanks); + return true; } // Prints the memory map across banks -void printMemMap(TileOp tile, SmallVector allocatedBuffers, - SmallVector preAllocatedBuffers, int numBanks, +void printMemMap(TileOp tile, SmallVector &allocatedBuffers, + SmallVector &preAllocatedBuffers, int numBanks, std::vector &bankLimits, int stacksize) { InFlightDiagnostic error = tile.emitOpError( "Not all requested buffers fit in the available memory.\n"); @@ -270,7 +295,7 @@ int setBufferAddress(BufferOp buffer, int numBanks, int startBankIndex, } LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, - SmallVector allBuffers, + SmallVector &allBuffers, std::vector &nextAddrInBanks, std::vector &bankLimits) { bool foundOverflow = false; @@ -320,7 +345,7 @@ LogicalResult checkAndPrintOverflow(TileOp tile, int numBanks, int stacksize, } // Function to deallocate attributes of buffers in case of a failure -void deAllocationBuffers(SmallVector &buffers) { +void deAllocationBuffers(SmallVector &buffers) { for (auto buffer : buffers) { buffer->removeAttr("address"); buffer->removeAttr("mem_bank"); @@ -363,9 +388,9 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { } fillBankLimits(numBanks, bankSize, bankLimits); - SmallVector buffersToAlloc; - SmallVector preAllocatedBuffers; - SmallVector allBuffers; + SmallVector preAllocatedBuffers; + SmallVector buffersToAlloc; + SmallVector allBuffers; // Collect all the buffers for this tile. device.walk([&](BufferOp buffer) { if (buffer.getTileOp() == tile) @@ -378,11 +403,13 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { // the above. for (auto buffer : allBuffers) { if (buffer.getTileOp() == tile) { - bool has_addr = checkAndAddBufferWithAddress(buffer, numBanks, + auto has_addr = checkAndAddBufferWithAddress(buffer, numBanks, nextAddrInBanks, bankLimits); - bool has_bank = checkAndAddBufferWithMemBank(buffer, numBanks, + auto has_bank = checkAndAddBufferWithMemBank(buffer, numBanks, nextAddrInBanks, bankLimits); - if (!has_addr && !has_bank) + if (failed(has_addr) || failed(has_bank)) + return failure(); + if (!has_addr.value() && !has_bank.value()) buffersToAlloc.push_back(buffer); else preAllocatedBuffers.push_back(buffer); @@ -396,7 +423,7 @@ LogicalResult simpleBankAwareAllocation(TileOp tile) { }); // Set addresses for remaining buffers. - SmallVector allocatedBuffers; + SmallVector allocatedBuffers; int bankIndex = 0; for (auto buffer : buffersToAlloc) { // If the buffer doesn't fit in any of the bank space then diff --git a/python/compiler/aiecc/cl_arguments.py b/python/compiler/aiecc/cl_arguments.py index f8ac91e5ed..c03caa10fe 100644 --- a/python/compiler/aiecc/cl_arguments.py +++ b/python/compiler/aiecc/cl_arguments.py @@ -147,7 +147,7 @@ def parse_args(args=None): parser.add_argument( "--alloc-scheme", dest="alloc_scheme", - default=None, + default="bank-aware", help="Allocation scheme for AIE buffers: basic-sequential, bank-aware (default).", ) parser.add_argument( diff --git a/python/compiler/aiecc/main.py b/python/compiler/aiecc/main.py index 6deb4f49fd..9218a59549 100644 --- a/python/compiler/aiecc/main.py +++ b/python/compiler/aiecc/main.py @@ -34,32 +34,30 @@ from aie.ir import Context, Location, Module from aie.passmanager import PassManager -INPUT_WITH_ADDRESSES_PIPELINE = ( - lambda scheme="", dynamic_objFifos=False, ctrl_pkt_overlay=False: ( +INPUT_WITH_ADDRESSES_PIPELINE = lambda scheme, dynamic_objFifos, ctrl_pkt_overlay: ( + Pipeline() + .lower_affine() + .add_pass("aie-canonicalize-device") + .Nested( + "aie.device", Pipeline() - .lower_affine() - .add_pass("aie-canonicalize-device") - .Nested( - "aie.device", - Pipeline() - .add_pass("aie-assign-lock-ids") - .add_pass("aie-register-objectFifos") - .add_pass( - "aie-objectFifo-stateful-transform", dynamic_objFifos=dynamic_objFifos - ) - .add_pass("aie-assign-bd-ids") - .add_pass("aie-lower-cascade-flows") - .add_pass("aie-lower-broadcast-packet") - .add_pass("aie-lower-multicast") - .add_pass("aie-assign-tile-controller-ids") - .add_pass( - "aie-generate-column-control-overlay", - route_shim_to_tile_ctrl=ctrl_pkt_overlay, - ) - .add_pass("aie-assign-buffer-addresses", alloc_scheme=scheme), + .add_pass("aie-assign-lock-ids") + .add_pass("aie-register-objectFifos") + .add_pass( + "aie-objectFifo-stateful-transform", dynamic_objFifos=dynamic_objFifos ) - .convert_scf_to_cf() + .add_pass("aie-assign-bd-ids") + .add_pass("aie-lower-cascade-flows") + .add_pass("aie-lower-broadcast-packet") + .add_pass("aie-lower-multicast") + .add_pass("aie-assign-tile-controller-ids") + .add_pass( + "aie-generate-column-control-overlay", + route_shim_to_tile_ctrl=ctrl_pkt_overlay, + ) + .add_pass("aie-assign-buffer-addresses", alloc_scheme=scheme), ) + .convert_scf_to_cf() ) LOWER_TO_LLVM_PIPELINE = ( @@ -334,7 +332,12 @@ def run_passes(pass_pipeline, mlir_module_str, outputfile=None, verbose=False): print("Running:", pass_pipeline) with Context() as ctx, Location.unknown(): module = Module.parse(mlir_module_str) - PassManager.parse(pass_pipeline).run(module.operation) + pm = PassManager.parse(pass_pipeline) + try: + pm.run(module.operation) + except Exception as e: + print("Error running pass pipeline: ", pass_pipeline, e) + raise e mlir_module_str = str(module) if outputfile: with open(outputfile, "w") as g: @@ -1062,12 +1065,9 @@ async def run_flow(self): file_with_addresses = self.prepend_tmp("input_with_addresses.mlir") - if opts.alloc_scheme: - pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( - opts.alloc_scheme, opts.dynamic_objFifos, opts.ctrl_pkt_overlay - ).materialize(module=True) - else: - pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE().materialize(module=True) + pass_pipeline = INPUT_WITH_ADDRESSES_PIPELINE( + opts.alloc_scheme, opts.dynamic_objFifos, opts.ctrl_pkt_overlay + ).materialize(module=True) run_passes( pass_pipeline, diff --git a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir index a22dbde1c2..e68749cd94 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_error.mlir @@ -1,4 +1,4 @@ -//===- bank_aware_alloc_error.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_error.mlir -----------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -26,18 +26,18 @@ // CHECK: bank : 3 0x6000-0x7FFF module @test { - aie.device(xcvc1902) { - %0 = aie.tile(3, 3) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> - %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> - %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) - %4 = aie.buffer(%3) : memref<500xi32> - aie.core(%0) { - aie.end + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end + } + aie.core(%3) { + aie.end + } } - aie.core(%3) { - aie.end - } - } -} \ No newline at end of file +} diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir index 44968d6d67..7615817140 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memory_exhausted.mlir @@ -1,4 +1,4 @@ -//===- bank_aware_alloc_memory_exhausted.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memory_exhausted.mlir ------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir index 929d1d43ae..9ec227545c 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_error.mlir @@ -1,4 +1,4 @@ -//===- bank_aware_alloc_memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memtile_error.mlir ---------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -29,13 +29,12 @@ // CHECK: bank : 6 0x60000-0x6FFFF // CHECK: bank : 7 0x70000-0x7FFFF - module @test { - aie.device(xcve2302) { - %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> - aie.memtile_dma(%0) { - aie.end + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> + aie.memtile_dma(%0) { + aie.end + } } - } -} \ No newline at end of file +} diff --git a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir index 292291ef9c..58374c6463 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_memtile_simple.mlir @@ -1,4 +1,4 @@ -//===- bank_aware_alloc_memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_memtile_simple.mlir --------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -12,11 +12,11 @@ // CHECK: %a = aie.buffer(%tile_3_1) {address = 0 : i32, mem_bank = 0 : i32, sym_name = "a"} : memref<16384xi32> module @test { - aie.device(xcve2302) { - %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16384xi32> - aie.memtile_dma(%0) { - aie.end + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16384xi32> + aie.memtile_dma(%0) { + aie.end + } } - } -} \ No newline at end of file +} diff --git a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir index 6724123b4b..ffad62922e 100644 --- a/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir +++ b/test/assign-buffer-addresses/bank_aware_alloc_simple.mlir @@ -1,4 +1,4 @@ -//===- bank_aware_alloc_simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- bank_aware_alloc_simple.mlir ----------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -17,18 +17,18 @@ module @test { - aie.device(xcvc1902) { - %0 = aie.tile(3, 3) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> - %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> - %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) - %4 = aie.buffer(%3) : memref<500xi32> - aie.core(%0) { - aie.end + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end + } + aie.core(%3) { + aie.end + } } - aie.core(%3) { - aie.end - } - } -} \ No newline at end of file +} diff --git a/test/assign-buffer-addresses/bank_aware_prealloc_error.mlir b/test/assign-buffer-addresses/bank_aware_prealloc_error.mlir new file mode 100644 index 0000000000..381c513781 --- /dev/null +++ b/test/assign-buffer-addresses/bank_aware_prealloc_error.mlir @@ -0,0 +1,35 @@ +//===- bank_aware_prealloc_error.mlir --------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --split-input-file --verify-diagnostics --aie-assign-buffer-addresses='alloc-scheme=bank-aware' %s + +module @test0 { + aie.device(npu1) { + %tile44 = aie.tile(4, 4) + %buf0 = aie.buffer(%tile44) : memref<200xi32> + %buf1 = aie.buffer(%tile44) : memref<100xi32> + %buf2 = aie.buffer(%tile44) { sym_name = "b", address = 4096 : i32 } : memref<1024xi32> + // expected-error@+1 {{'aie.buffer' op would override existing mem_bank}} + %buf3 = aie.buffer(%tile44) { sym_name = "c", address = 12288 : i32 } : memref<1024xi32> + %buf4 = aie.buffer(%tile44) { sym_name = "d", address = 20000 : i32 } : memref<1024xi32> + %buf5 = aie.buffer(%tile44) : memref<800xi32> + } +} + +// ----- + +module @test1 { + aie.device(npu1) { + %tile44 = aie.tile(4, 4) + %buf0 = aie.buffer(%tile44) { sym_name = "a", address = 0 : i32 } : memref<1024xi32> + // expected-error@+1 {{'aie.buffer' op would override allocated address}} + %buf2 = aie.buffer(%tile44) { sym_name = "b", address = 1024 : i32 } : memref<1024xi32> + } +} diff --git a/test/assign-buffer-addresses/basic_alloc_error.mlir b/test/assign-buffer-addresses/basic_alloc_error.mlir index 7cc1db9a1a..978eb2a54f 100644 --- a/test/assign-buffer-addresses/basic_alloc_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_error.mlir @@ -1,4 +1,4 @@ -//===- basic_alloc_error.mlir ---------------------------------------------*- MLIR -*-===// +//===- basic_alloc_error.mlir ----------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -16,18 +16,18 @@ // CHECK: a : 0x8420-0x842F (16 bytes) module @test { - aie.device(xcvc1902) { - %0 = aie.tile(3, 3) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> - %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> - %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) - %4 = aie.buffer(%3) : memref<500xi32> - aie.core(%0) { - aie.end + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<8192xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end + } + aie.core(%3) { + aie.end + } } - aie.core(%3) { - aie.end - } - } } diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir index 7aaba2b3d6..0b1ba4b627 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_error.mlir @@ -1,4 +1,4 @@ -//===- basic_alloc_memtile_error.mlir ---------------------------------------*- MLIR -*-===// +//===- basic_alloc_memtile_error.mlir --------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -12,11 +12,11 @@ // CHECK: error: 'aie.tile' op allocated buffers exceeded available memory module @test { - aie.device(xcve2302) { - %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> - aie.memtile_dma(%0) { - aie.end + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<132000xi32> + aie.memtile_dma(%0) { + aie.end + } } - } } diff --git a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir index d140f23521..886e3596fb 100644 --- a/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_memtile_simple.mlir @@ -1,4 +1,4 @@ -//===- basic_alloc_memtile_simple.mlir --------------------------------------*- MLIR -*-===// +//===- basic_alloc_memtile_simple.mlir -------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -19,11 +19,11 @@ // CHECK: } // CHECK: } module @test { - aie.device(xcve2302) { - %0 = aie.tile(3, 1) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> - aie.memtile_dma(%0) { - aie.end + aie.device(xcve2302) { + %0 = aie.tile(3, 1) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<65536xi32> + aie.memtile_dma(%0) { + aie.end + } } - } } diff --git a/test/assign-buffer-addresses/basic_alloc_simple.mlir b/test/assign-buffer-addresses/basic_alloc_simple.mlir index f866c76eae..e7b81c47c2 100644 --- a/test/assign-buffer-addresses/basic_alloc_simple.mlir +++ b/test/assign-buffer-addresses/basic_alloc_simple.mlir @@ -1,4 +1,4 @@ -//===- basic_alloc_simple.mlir ---------------------------------------------*- MLIR -*-===// +//===- basic_alloc_simple.mlir ---------------------------------*- MLIR -*-===// // // This file is licensed under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -15,18 +15,18 @@ // CHECK: {{.*}} aie.buffer({{.*}}) {address = 1024 : i32, sym_name = "_anonymous0"} : memref<500xi32> module @test { - aie.device(xcvc1902) { - %0 = aie.tile(3, 3) - %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> - %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> - %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> - %3 = aie.tile(4, 4) - %4 = aie.buffer(%3) : memref<500xi32> - aie.core(%0) { - aie.end + aie.device(xcvc1902) { + %0 = aie.tile(3, 3) + %b1 = aie.buffer(%0) { sym_name = "a" } : memref<16xi8> + %1 = aie.buffer(%0) { sym_name = "b" } : memref<512xi32> + %b2 = aie.buffer(%0) { sym_name = "c" } : memref<16xi16> + %3 = aie.tile(4, 4) + %4 = aie.buffer(%3) : memref<500xi32> + aie.core(%0) { + aie.end + } + aie.core(%3) { + aie.end + } } - aie.core(%3) { - aie.end - } - } } diff --git a/test/assign-buffer-addresses/basic_prealloc.mlir b/test/assign-buffer-addresses/basic_prealloc.mlir new file mode 100644 index 0000000000..c8b2be2e11 --- /dev/null +++ b/test/assign-buffer-addresses/basic_prealloc.mlir @@ -0,0 +1,28 @@ +//===- basic_prealloc.mlir -------------------------------------*- MLIR -*-===// +// +// This file is licensed under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +// Copyright (C) 2024, Advanced Micro Devices, Inc. +// +//===----------------------------------------------------------------------===// + +// RUN: aie-opt --aie-assign-buffer-addresses='alloc-scheme=basic-sequential' %s | FileCheck %s + +// CHECK: aie.buffer(%{{.*}}) {address = 4096 : i32, sym_name = "b"} : memref<1024xi32> +// CHECK: aie.buffer(%{{.*}}) {address = 12288 : i32, sym_name = "c"} : memref<1024xi32> +// CHECK: aie.buffer(%{{.*}}) {address = 20000 : i32, sym_name = "d"} : memref<1024xi32> + +module @test { + aie.device(npu1) { + %tile22 = aie.tile(2, 2) + + %buf0 = aie.buffer(%tile22) : memref<200xi32> + %buf1 = aie.buffer(%tile22) : memref<100xi32> + %buf2 = aie.buffer(%tile22) { sym_name = "b", address = 4096 : i32 } : memref<1024xi32> + %buf3 = aie.buffer(%tile22) { sym_name = "c", address = 12288 : i32 } : memref<1024xi32> + %buf4 = aie.buffer(%tile22) { sym_name = "d", address = 20000 : i32 } : memref<1024xi32> + %buf5 = aie.buffer(%tile22) : memref<800xi32> + } +} diff --git a/test/unit_tests/aie2/00_itsalive/aie.mlir b/test/unit_tests/aie2/00_itsalive/aie.mlir index a11c2f3594..5c7600260f 100644 --- a/test/unit_tests/aie2/00_itsalive/aie.mlir +++ b/test/unit_tests/aie2/00_itsalive/aie.mlir @@ -15,7 +15,7 @@ module @test00_itsalive { aie.device(xcve2802) { %tile12 = aie.tile(1, 3) - %buf12_0 = aie.buffer(%tile12) { sym_name = "a", address = 0 : i32 } : memref<256xi32> + %buf12_0 = aie.buffer(%tile12) : memref<256xi32> %core12 = aie.core(%tile12) { %val1 = arith.constant 1 : i32