diff --git a/llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp b/llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp
index 37865902ad13..0b3279e9de96 100644
--- a/llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/AIE/AIE2PreLegalizerCombiner.cpp
@@ -69,6 +69,8 @@ class AIE2PreLegalizerCombinerImpl : public Combiner {
 
   bool tryToCombineVectorShiftsByZero(MachineInstr &MI) const;
 
+  bool tryToCombineSetExtract(MachineInstr &MI) const;
+
   bool tryToCombineIntrinsic(MachineInstr &MI) const;
 
 private:
@@ -136,6 +138,25 @@ bool AIE2PreLegalizerCombinerImpl::tryToCombineVectorShiftsByZero(
   return true;
 }
 
+bool AIE2PreLegalizerCombinerImpl::tryToCombineSetExtract(
+    MachineInstr &MI) const {
+  const Register DstReg = MI.getOperand(0).getReg();
+  MachineInstr *ExtOp = MRI.getUniqueVRegDef(MI.getOperand(2).getReg());
+
+  assert(ExtOp && "Expected SSA.");
+  if (ExtOp->getOpcode() != AIE2::G_INTRINSIC ||
+      cast<GIntrinsic>(*ExtOp).getIntrinsicID() !=
+          Intrinsic::aie2_extract_I128_I512)
+    return false;
+
+  MachineIRBuilder MIRBuilder(MI);
+  MIRBuilder.buildCopy(DstReg, ExtOp->getOperand(2).getReg());
+  ExtOp->eraseFromParent();
+  MI.eraseFromParent();
+
+  return true;
+}
+
 bool AIE2PreLegalizerCombinerImpl::tryToCombineIntrinsic(
     MachineInstr &MI) const {
 
@@ -143,6 +164,9 @@ bool AIE2PreLegalizerCombinerImpl::tryToCombineIntrinsic(
   case Intrinsic::aie2_vshift_I512_I512: {
     return CombineVecShiftByZero && tryToCombineVectorShiftsByZero(MI);
   }
+  case Intrinsic::aie2_set_I512_I128: {
+    return tryToCombineSetExtract(MI);
+  }
   default:
     break;
   }