PCB_Design

Versal™ Adaptive SoC Architecture Tutorials See Vivado™ Development Environment on amd.com

PCB Design Tutorials

External Memory Interface Planning

This page shows an overview of the external memory pre-planning tool that allows system architects to quickly determine which Versal devices are suitable for their memory interace needs.

Timing Models for Hyperlynx DDRx Wizard

This page shows an overview of the Mentor Graphics Hyperlynx DDRx Wizard, a tool that allows signal integrity engineers to quickly simulate memory interfaces at the PCB level.

Obtain and Verify Memory Pinouts

This page guides the schematic designer to obtain and verify memory pinouts for AMD Versal™ devices.

Schematic Checker Tool

This page shows an overview of the schematic checker tool, which is a subset of the Versal Schematic Review Checklist.

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