HW_Debug

Versal™ Adaptive SoC Architecture Tutorials See Vivado™ Development Environment on amd.com

Versal Architecture-Specific Tutorials

Hardware Debugging Tutorials

Tutorial	Description
Basic PL Hardware Debugging Using ChipScope AXIS-ILA and AXIS-VIO	This tutorial introduces the basic hardware debugging techniques using ChipScope. Covers the adding the Integraded Logic Analyzer (AXIS-ILA) to an IP Integrator (IPI) design, an RTL Module, and after synthesis using post-synthesis insertion.
Versal IBERT GTY Tutorial	Versal IBERT GTY is used to interact with GTY lanes contained in a design. It is used to debug and verify issues in high speed serial I/O links. In contrast to previous architectures, Versal IBERT GTY does not require additional IP and can be used with any design that utilizes the GTY transceivers. However, in some cases it may be required to generate an IBERT capable design with minimal user interaction: this tutorial will demonstrate that flow.

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