We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
I got that compilation error while trying to build chaidnn using SDSoC v2018.3
Creating Vivado project and starting FPGA synthesis.
What could be the reason of that error ?
WARNING: [VPL 60-1142] Unabled to read data from '/home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/vivado/output/generated_reports.log', generated reports will not be copied. ERROR: [VPL 60-341] Hardware accelerator integration failed. Aborting build_system. The following log file is available for debugging '/home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/vivado/vivado.log'. Contact your local Xilinx representative and provide the log file for further assistance. ERROR: [VPL 60-806] Failed to finish platform linker ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx_SDx/SDx/2018.3/bin/vpl --iprepo /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/iprepo/repo --iprepo /opt/Xilinx_SDx/SDx/2018.3/data/ip/xilinx --platform /opt/Xilinx_SDx/SDx/2018.3/platforms/zcu102/zcu102.xpfm --temp_dir /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0 --output_dir /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/vpl --input_file /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels PoolTop:XiDeconvTop:XiConvolutionTop:adapter --webtalk_flag SDSoC --remote_ip_cache /home/aiembed/Desktop/Karim/sdsoc/ip_cache --xp "param:compiler.skipTimingCheckAndFrequencyScaling=1" --xp "vivado_prop:run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1" --xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.synth_1.{STEPS.SYNTH_DESIGN.TCL.PRE}={/src/conv/scripts/mcps.tcl}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.TCL.PRE}={/src/conv/scripts/mcps.tcl}" --xp "param:compiler.deleteDefaultReportConfigs=false" ' sds++ log file saved as /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/reports/sds.log ERROR: [SdsCompiler 83-5004] Build failed sds++ completed at Mon Oct 28 16:49:59 CET 2019
The text was updated successfully, but these errors were encountered:
even I am facing the same issue
Sorry, something went wrong.
No branches or pull requests
I got that compilation error while trying to build chaidnn using SDSoC v2018.3
Creating Vivado project and starting FPGA synthesis.
What could be the reason of that error ?
WARNING: [VPL 60-1142] Unabled to read data from '/home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/vivado/output/generated_reports.log', generated reports will not be copied.
ERROR: [VPL 60-341] Hardware accelerator integration failed. Aborting build_system. The following log file is available for debugging '/home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/vivado/vivado.log'. Contact your local Xilinx representative and provide the log file for further assistance.
ERROR: [VPL 60-806] Failed to finish platform linker
ERROR: [SdsCompiler 83-5019] Exiting sds++ : Error when calling '/opt/Xilinx_SDx/SDx/2018.3/bin/vpl --iprepo /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/iprepo/repo --iprepo /opt/Xilinx_SDx/SDx/2018.3/data/ip/xilinx --platform /opt/Xilinx_SDx/SDx/2018.3/platforms/zcu102/zcu102.xpfm --temp_dir /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0 --output_dir /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/vpl --input_file /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/p0/.xsd/top.bd.tcl --target hw --save_temps --kernels PoolTop:XiDeconvTop:XiConvolutionTop:adapter --webtalk_flag SDSoC --remote_ip_cache /home/aiembed/Desktop/Karim/sdsoc/ip_cache --xp "param:compiler.skipTimingCheckAndFrequencyScaling=1" --xp "vivado_prop:run.impl_1.{STEPS.OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.STEPS.PHYS_OPT_DESIGN.IS_ENABLED=1" --xp "vivado_prop:run.impl_1.{STEPS.PHYS_OPT_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.impl_1.{STEPS.ROUTE_DESIGN.ARGS.MORE OPTIONS}={-directive Explore}" --xp "vivado_prop:run.synth_1.{STEPS.SYNTH_DESIGN.TCL.PRE}={/src/conv/scripts/mcps.tcl}" --xp "vivado_prop:run.impl_1.{STEPS.PLACE_DESIGN.TCL.PRE}={/src/conv/scripts/mcps.tcl}" --xp "param:compiler.deleteDefaultReportConfigs=false" '
sds++ log file saved as /home/aiembed/Desktop/Karim/sdsoc/chaidnn/Release/_sds/reports/sds.log
ERROR: [SdsCompiler 83-5004] Build failed
sds++ completed at Mon Oct 28 16:49:59 CET 2019
The text was updated successfully, but these errors were encountered: