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qrc.ccl
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qrc.ccl
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#--------------------------------------------------------------------------------------
# Cadence Calibre-Quantus Extraction Option Command File
#--------------------------------------------------------------------------------------
capacitance \
# -decoupling_factor < value > default 1.0 for coupled C and decoupled C can be seted
# Mult Factor in Extraction Tab when choose Decoupled Cap Coupling Mode
-decoupling_factor "1.0" \
# -ground_net <ground_node_name> Ref Node in Extraction Tab
-ground_net "0"
distributed_processing \
# -multi_cpu < number> run on multiple processors Run Details Tab
-multi_cpu "10"
extract \
-selection "all" \
# Extraction Tab via Extraction Type and Cap Coupling Mode
-type "rc_coupled"
extraction_setup \
# -array_vias_spacing [< value >/auto] Filtering Tab
# < value > specifies the maximum edge-to-edge distance between vias or contacts that will be grouped into an array.
-array_vias_spacing "auto" \
# Extraction Tab Max fracture length and uint
-max_fracture_length "infinite" \
-max_fracture_length_unit "MICRONS" \
# -max_via_array_size < layer > [<size>/auto]
# Group vias array within max_via_array_size to one via
-max_via_array_size "auto" \
# -net_name_space [schematic/layout] Net name in Extraction Tab
-net_name_space "LAYOUT"
filter_cap \
# -exclude_self_cap [true/false]
# -exclude_self_cap is used to exclude parasitic capacitance between distributed RC nodes on the same net.
# This option only applies to extract -type rc_coupled .
-exclude_self_cap "true"
filter_coupling_cap \
# -coupling_cap_threshold_absolute <value> MinC in Filtering Tab
# This option only applies to Coupled Cap Coupling Mode
-coupling_cap_threshold_absolute "0.01" \
-coupling_cap_threshold_relative "0.001"
filter_res \
# -min_res < value> Specifies the minimum resistance value for extracted parasitic resistors.
-min_res "0.001" \
# -merge_parallel_res [true/false] specifies that parallel parasitic resistors should be merged in simple parallel fashion before netlisting.
-merge_parallel_res "true" \
# -remove_dangling_res [true/false]
-remove_dangling_res "false"
input_db -type calibre \
# -device_property_value <value> 7 by default in Calibre query
-device_property_value "7" \
# -directory_name <dir> specifies directory in which Calibre placed the output files of the LVS run.
-directory_name "./query_output" \
-hierarchy_delimiter "/" \
# -instance_property_value <value> 6 by default in Calibre query
-instance_property_value "6" \
# -layer_map_file <filename> specifies a layer mapping file between the GDS input layers and the layer names in the Calibre LVS rule file.
-layer_map_file "./query_output/Design.gds.map" \
# -net_property_value <value> 5 by default in Calibre query
-net_property_value "5" \
# -run_name <string> Specifies Calibre name assigned to the LVS run.
-run_name "Design"
output_db -type spice \
# -add_explicit_vias [true/false]
#The default false causes the resistance for vias and contacts to be added as part of the resistance of the metal layer interconnect which connects to the contact or via.
-add_explicit_vias true \
-hierarchy_delimiter "/" \
# -include_XXXX_model [false/true/comment]
# true models are included in-line in the output file
# false models are not written to the output file
# comment models are included as comments in the output file by deafult
-include_cap_model "false" \
-include_parasitic_cap_model "false" \
-include_parasitic_res_model "comment" \
-include_parasitic_res_width "false" \
-include_parasitic_res_width_drawn "false" \
-include_res_model "false" \
-sub_node_char "#" \
# -output_xy canonical_cap/parasitic_cap/canonical_res/parasitic_res/diode/mos/bipolar/generic
# Causes XY-coordinate information to be added to the output netlist for one or more designed device and parasitic component types.
-output_xy "parasitic_res" \
output_setup \
# -directory_name <directory> specifies directory to store the output file(s).
-directory_name "./" \
# -file_name < filename> specifies the name of the output file name generated by Quantus.
-file_name "./update.sp" \
# -net_name_space [schematic/layout] Specifies whether Quantus writes layout or schematic names to the output netlist in Netlisting Tab
-net_name_space "LAYOUT" \
# -temporary_directory_name <directory> specifies directory to write temporary files
-temporary_directory_name "tmp"
process_technology \
# -technology_directory <techpath1> specify the path for a single corner techfile only in the Quantus transistor-level flow.
# In Calibre-Quantus flow, the technology directory should contain lvsfile, qrcTechFile, RCXspiceINIT, RCXdspfINIT files.
-technology_directory "./typical" \
# -temperature <temperature1> Specifies the operating temperature for the design in degrees Celsius.
-temperature "25.0"