From 3ef564bcf40920a37ce7ad414d4ccc26bb5f7fa1 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Wed, 20 Mar 2024 08:57:52 +0000 Subject: [PATCH 01/26] Add issue and PR templates (#2294) * Add PR template. * Add issue templates. --- .github/ISSUE_TEMPLATE/bug_report_asm.md | 58 ++++++++++++++++++++ .github/ISSUE_TEMPLATE/bug_report_general.md | 40 ++++++++++++++ .github/ISSUE_TEMPLATE/feature_request.md | 19 +++++++ .github/PULL_REQUEST_TEMPLATE.md | 23 ++++++++ 4 files changed, 140 insertions(+) create mode 100644 .github/ISSUE_TEMPLATE/bug_report_asm.md create mode 100644 .github/ISSUE_TEMPLATE/bug_report_general.md create mode 100644 .github/ISSUE_TEMPLATE/feature_request.md create mode 100644 .github/PULL_REQUEST_TEMPLATE.md diff --git a/.github/ISSUE_TEMPLATE/bug_report_asm.md b/.github/ISSUE_TEMPLATE/bug_report_asm.md new file mode 100644 index 0000000000..1042bb7346 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug_report_asm.md @@ -0,0 +1,58 @@ +--- +name: Bug report - Incorrect disassembly +about: Create a report about incorrect disassembly. +--- + + + +### Work environment + + + +| Questions | Answers +|------------------------------------------|-------------------- +| OS/arch/bits | Debian arm 64, MacOS AArch64, MacOS x86, Windows x86 etc. +| Architecture | ppc, x86, cortexm, armv8 etc. +| Source of Capstone | `git clone`, brew, pip, release binaries etc. +| Version/git commit | v5.0.1, + + + +### Instruction bytes giving faulty results + +``` +0x00,0x00,0x00,0x00 +``` + +### Expected results + +It should be: +``` + +``` + +### Steps to get the wrong result + +With `cstool`: + +```sh +cstool arm -d 0x00,0x00,0x00,0x00 +``` + +or with `Python` + +```python +CODE = b'\x90\x90\x90\x90' + +md = Cs(CS_ARCH_ARM, CS_MODE_THUMB) +md.detail = True +for insn in md.disasm(CODE, 0x1000): + # Print the faulty disassembly +``` + + + +### Additional Logs, screenshots, source code, configuration dump, ... + +Drag and drop zip archives containing the Additional info here, don't use external services or link. +Screenshots can be directly dropped here. diff --git a/.github/ISSUE_TEMPLATE/bug_report_general.md b/.github/ISSUE_TEMPLATE/bug_report_general.md new file mode 100644 index 0000000000..b14585f5cb --- /dev/null +++ b/.github/ISSUE_TEMPLATE/bug_report_general.md @@ -0,0 +1,40 @@ +--- +name: Bug report - Other bugs +about: Create a report to help us improve + +--- + + + +### Work environment + + + +| Questions | Answers +|------------------------------------------|-------------------- +| OS/arch/bits | Debian arm 64, MacOS AArch64, MacOS x86, Windows x86 etc. +| Architecture | ppc, x86, cortexm, armv8 etc. +| Source of Capstone | `git clone`, brew, pip, release binaries etc. +| Version/git commit | v5.0.1, + + + +### Expected behavior + +### Actual behavior + +### Steps to reproduce the behavior + +- Use code markdown `CODE` to make your code visible + + + +### Additional Logs, screenshots, source code, configuration dump, ... + +Drag and drop zip archives containing the Additional info here, don't use external services or link. +Screenshots can be directly dropped here. \ No newline at end of file diff --git a/.github/ISSUE_TEMPLATE/feature_request.md b/.github/ISSUE_TEMPLATE/feature_request.md new file mode 100644 index 0000000000..77e3e33fd0 --- /dev/null +++ b/.github/ISSUE_TEMPLATE/feature_request.md @@ -0,0 +1,19 @@ +--- +name: Feature request +about: Suggest an idea for this project + +--- + +### Feature + +- [ ] New architecture module +- [ ] Support for processor extension +- [ ] Add more instruction details (elaborated below) +- [ ] Binding support for: `language` +- [ ] Other (elaborated below) + +**Describe the feature you'd like** +A clear and concise description of what you want to happen. + +**Additional context** +Add any other context about the feature request here. diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md new file mode 100644 index 0000000000..40deda3ed5 --- /dev/null +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -0,0 +1,23 @@ + + +**Your checklist for this pull request** +- [ ] I've documented or updated the documentation of every function and struct this PR changes. If not so I've explained why. +- [ ] I've added tests that prove my fix is effective or that my feature works (if possible) + +**Detailed description** + + + +... + +**Test plan** + + + +... + +**Closing issues** + + + +... From 989dca2a28d25b697c475ffeb87ae27a46e77751 Mon Sep 17 00:00:00 2001 From: Wu ChenXu Date: Wed, 20 Mar 2024 19:20:40 +0800 Subject: [PATCH 02/26] Add telegram group link to README.md --- README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/README.md b/README.md index 1932ac2c8b..23fb0d75c9 100644 --- a/README.md +++ b/README.md @@ -6,6 +6,9 @@ Capstone Engine [![pypi downloads](https://pepy.tech/badge/capstone)](https://pepy.tech/project/capstone) [![oss-fuzz Status](https://oss-fuzz-build-logs.storage.googleapis.com/badges/capstone.svg)](https://bugs.chromium.org/p/oss-fuzz/issues/list?sort=-opened&can=1&q=proj:capstone) +> [!TIP] +> Welcome to join our community group!   [](https://t.me/CapstoneEngine) + Capstone is a disassembly framework with the target of becoming the ultimate disasm engine for binary analysis and reversing in the security community. From 5d9942d13ffda479269edd4e383df9e15c67b80d Mon Sep 17 00:00:00 2001 From: Yudi Zheng Date: Thu, 21 Mar 2024 06:33:30 +0100 Subject: [PATCH 03/26] Avoid random access values for operands in not-yet-specified instructions. (#2259) --- arch/X86/X86ATTInstPrinter.c | 17 ++++++++++------- arch/X86/X86InstPrinterCommon.h | 2 +- arch/X86/X86IntelInstPrinter.c | 21 ++++++++++++--------- arch/X86/X86MappingInsnOp.inc | 3 +-- suite/cstest/issues.cs | 4 ++++ 5 files changed, 28 insertions(+), 19 deletions(-) diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index c7d8e3f098..800d9e4e70 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -286,6 +286,9 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64 uint8_t count, i; const uint8_t *arr = X86_get_op_access(h, id, eflags); + // initialize access + memset(access, 0, CS_X86_MAXIMUM_OPERAND_SIZE * sizeof(access[0])); + if (!arr) { access[0] = 0; return; @@ -313,7 +316,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) int reg; if (MI->csh->detail_opt) { - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; @@ -351,7 +354,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) { if (MI->csh->detail_opt) { - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; @@ -437,7 +440,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) int reg; if (MI->csh->detail_opt) { - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; @@ -563,7 +566,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) if (MI->csh->doing_mem) { MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); } else { - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].reg = X86_register_map(reg); @@ -712,7 +715,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) int64_t DispVal = 1; if (MI->csh->detail_opt) { - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].size = MI->x86opsize; @@ -877,7 +880,7 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) } if (MI->csh->detail_opt) { - uint8_t access[6] = {0}; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE] = {0}; // some instructions need to supply immediate 1 in the first op switch(MCInst_getOpcode(MI)) { @@ -983,7 +986,7 @@ void X86_ATT_printInst(MCInst *MI, SStream *OS, void *info) MI->flat_insn->detail->x86.operands[1].type = X86_OP_REG; MI->flat_insn->detail->x86.operands[1].reg = reg2; MI->flat_insn->detail->x86.operands[1].size = MI->csh->regsize_map[reg2]; - MI->flat_insn->detail->x86.operands[0].access = access2; + MI->flat_insn->detail->x86.operands[1].access = access2; MI->flat_insn->detail->x86.op_count = 2; } } diff --git a/arch/X86/X86InstPrinterCommon.h b/arch/X86/X86InstPrinterCommon.h index d6fe89f1b8..29a9ec3dea 100644 --- a/arch/X86/X86InstPrinterCommon.h +++ b/arch/X86/X86InstPrinterCommon.h @@ -7,10 +7,10 @@ #include "../../MCInst.h" #include "../../SStream.h" +#define CS_X86_MAXIMUM_OPERAND_SIZE 6 void printSSEAVXCC(MCInst *MI, unsigned Op, SStream *O); void printXOPCC(MCInst *MI, unsigned Op, SStream *O); void printRoundingControl(MCInst *MI, unsigned Op, SStream *O); #endif - diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index cb1167e31d..bdd4457850 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -430,6 +430,9 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64 uint8_t i; const uint8_t *arr = X86_get_op_access(h, id, eflags); + // initialize access + memset(access, 0, CS_X86_MAXIMUM_OPERAND_SIZE * sizeof(access[0])); + if (!arr) { access[0] = 0; return; @@ -456,7 +459,7 @@ static void printSrcIdx(MCInst *MI, unsigned Op, SStream *O) if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; @@ -496,7 +499,7 @@ static void printDstIdx(MCInst *MI, unsigned Op, SStream *O) { if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; @@ -592,7 +595,7 @@ static void printMemOffset(MCInst *MI, unsigned Op, SStream *O) if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; @@ -649,7 +652,7 @@ static void printU8Imm(MCInst *MI, unsigned Op, SStream *O) if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; @@ -714,7 +717,7 @@ void X86_Intel_printInst(MCInst *MI, SStream *O, void *Info) reg = X86_insn_reg_intel(MCInst_getOpcode(MI), &access1); if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6] = {0}; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE] = {0}; #endif // first op can be embedded in the asm by llvm. @@ -771,7 +774,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; @@ -810,7 +813,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.base = X86_register_map(reg); } else { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_REG; @@ -897,7 +900,7 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O) MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].mem.disp = imm; } else { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_IMM; @@ -937,7 +940,7 @@ static void printMemReference(MCInst *MI, unsigned Op, SStream *O) if (MI->csh->detail_opt) { #ifndef CAPSTONE_DIET - uint8_t access[6]; + uint8_t access[CS_X86_MAXIMUM_OPERAND_SIZE]; #endif MI->flat_insn->detail->x86.operands[MI->flat_insn->detail->x86.op_count].type = X86_OP_MEM; diff --git a/arch/X86/X86MappingInsnOp.inc b/arch/X86/X86MappingInsnOp.inc index 582d4414ed..16b2a4525b 100644 --- a/arch/X86/X86MappingInsnOp.inc +++ b/arch/X86/X86MappingInsnOp.inc @@ -16915,7 +16915,7 @@ { /* X86_VCMPSSZrr_Int, X86_INS_VCMP: vcmp */ 0, - { 0 } + { CS_AC_WRITE, CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_VCMPSSZrr_Intk, X86_INS_VCMP: vcmp */ @@ -75697,4 +75697,3 @@ X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_RESET_CF | X86_EFLAGS_RESET_OF | X86_EFLAGS_RESET_SF | X86_EFLAGS_RESET_PF | X86_EFLAGS_RESET_AF, { 0 } }, - diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs index 6bc78b1b53..fecd353716 100644 --- a/suite/cstest/issues.cs +++ b/suite/cstest/issues.cs @@ -1,3 +1,7 @@ +!# issue 2258 vcmpunordss incorrect read/modified register +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x62,0xd1,0x56,0x08,0xc2,0xca,0x03 == vcmpunordss k1, xmm5, xmm10 ; operands[0].access: WRITE ; operands[1].access: READ ; operands[2].access: READ + !# issue 2062 repz Prefix !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0xf3,0xc3 == repz ret ; Prefix:0xf3 0x00 0x00 0x00 From 0d12bcacd75da8ba02f6294505e7bedd55002a66 Mon Sep 17 00:00:00 2001 From: James Kang <164518010+majorteach@users.noreply.github.com> Date: Sat, 23 Mar 2024 19:42:19 +0800 Subject: [PATCH 04/26] Remove repetitive words (#2297) --- COMPILE_CMAKE.TXT | 2 +- .../tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h | 2 +- .../tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 +- suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h | 2 +- .../synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index 0a3a36c8f8..d36bd792e7 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -45,7 +45,7 @@ Get CMake for free from http://www.cmake.org. By default, all architectures are compiled in. If you're building a static library that you intend to link into multiple consumers, and they have differing architecture requirements, you may want -DCAPSTONE_USE_ARCH_REGISTRATION=1 and call cs_arch_register_*() for the architectures you need in each particular consumer. In this way you only pay - footprint size for the the architectures you're actually using in each consumer, without having to compile Capstone + footprint size for the architectures you're actually using in each consumer, without having to compile Capstone multiple times. Besides, Capstone also allows some more customization via following macros. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h index f6563971f9..dbc36888fb 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -295,7 +295,7 @@ template class CodeGenPassBuilder { /// all virtual registers. /// /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not - /// be honored. This is also not generally used for the the fast variant, + /// be honored. This is also not generally used for the fast variant, /// where the allocation and rewriting are done in one pass. void addPreRewrite(AddMachinePass &) const {} diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 3b2f937375..179f2f07ac 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -238,7 +238,7 @@ class LegalizerHelper { /// needs to be widened to evenly cover \p DstReg, inserts high bits /// corresponding to the extension opcode \p PadStrategy. /// - /// \p VRegs will be cleared, and the the result \p NarrowTy register pieces + /// \p VRegs will be cleared, and the result \p NarrowTy register pieces /// will replace it. Returns The complete LCMTy that \p VRegs will cover when /// merged. LLT buildLCMMergePieces(LLT DstTy, LLT NarrowTy, LLT GCDTy, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h index 51ffe28074..09ae23bb2c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h @@ -851,7 +851,7 @@ namespace llvm { /// V2: sub0 sub1 sub2 sub3 /// V1: sub0 sub1 /// - /// This offset will look like a composed subregidx in the the class: + /// This offset will look like a composed subregidx in the class: /// V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> /// => V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32> /// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h index 9b13b61fc9..ff23cffdcd 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h @@ -398,7 +398,7 @@ class TargetPassConfig : public ImmutablePass { /// all virtual registers. /// /// Note if the target overloads addRegAssignAndRewriteOptimized, this may not - /// be honored. This is also not generally used for the the fast variant, + /// be honored. This is also not generally used for the fast variant, /// where the allocation and rewriting are done in one pass. virtual bool addPreRewrite() { return false; From 9daa1ffbac35f553c4b2c0428af0b5cfdd6850d7 Mon Sep 17 00:00:00 2001 From: R3v0LT <87137964+R33v0LT@users.noreply.github.com> Date: Tue, 26 Mar 2024 08:58:56 +0300 Subject: [PATCH 05/26] Add HPPA(PA-RISC) architecture (#2265) * Refactor HPPA * Add full HPPA 1.1 instructions support * Add HPPA 1.1 cs tests * Fix HPPA dissassembler * Add HPPA 2.0 instructions * Add HPPA tests * Fix HPPA disasm & printer * Update HPPA tests * Remove unused code * Add implicit register access info & Refactor HPPA main files * Add python bindings/tests and cstests * Fix HPPA disasm wrong decoding * Rewrite invalid test cases * Update HPPA python constants * Make HPPA python test executable * Change HPPA python tests sequence to match c tests * Refactor HPPA main files * Write target instead of offset in details * Add HPPA detail function support in cstest * Rewrite targets in branch tests * Make correct string modifier addition * Add hppa test calls * Add zero operands check * Remove MCOperand array * Change immediate values printing * Add HPPA 2.0 wide support * Fix invalid break instruction decode Remove unused code * Add HPPA to fuzzing tests * Add HPPA to options * Add HPPA to docs * Refactor HPPA * Fix invalid branch insn decoding * Add HPPA to labeler * clang-format hppa files * Document internal structures and minor refactoring * Add missing default statements * Fix invalid default statement --- .github/labeler.yml | 7 + .gitignore | 2 + CMakeLists.txt | 27 +- COMPILE.TXT | 1 + COMPILE_CMAKE.TXT | 3 +- COMPILE_MSVC.TXT | 1 + CREDITS.TXT | 2 +- HACK.TXT | 1 + MCInst.c | 1 + MCInst.h | 1 + Makefile | 18 +- Mapping.c | 1 + Mapping.h | 4 + MathExtras.h | 18 + arch/HPPA/HPPAConstants.h | 74 + arch/HPPA/HPPADisassembler.c | 3837 ++++++++++++++++++++++++ arch/HPPA/HPPADisassembler.h | 13 + arch/HPPA/HPPAInstPrinter.c | 837 ++++++ arch/HPPA/HPPAInstPrinter.h | 25 + arch/HPPA/HPPAMapping.c | 440 +++ arch/HPPA/HPPAMapping.h | 19 + arch/HPPA/HPPAModule.c | 34 + arch/HPPA/HPPAModule.h | 12 + bindings/Makefile | 4 + bindings/const_generator.py | 3 +- bindings/python/Makefile | 2 +- bindings/python/capstone/__init__.py | 16 +- bindings/python/capstone/hppa.py | 72 + bindings/python/capstone/hppa_const.py | 453 +++ bindings/python/setup_cython.py | 2 +- bindings/python/test_all.py | 3 +- bindings/python/test_basic.py | 8 + bindings/python/test_detail.py | 8 + bindings/python/test_hppa.py | 75 + bindings/python/test_iter.py | 9 +- cmake.sh | 3 + config.mk | 2 +- cs.c | 32 +- cstool/cstool.c | 22 + cstool/cstool.h | 1 + cstool/cstool_hppa.c | 87 + include/capstone/capstone.h | 6 + include/capstone/hppa.h | 543 ++++ nmake.bat | 1 + suite/MC/HPPA/alu11.s.cs | 433 +++ suite/MC/HPPA/arith_imm11.s.cs | 97 + suite/MC/HPPA/assist20.s.cs | 32 + suite/MC/HPPA/branch11.s.cs | 9 + suite/MC/HPPA/branch20.s.cs | 43 + suite/MC/HPPA/computation20.s.cs | 63 + suite/MC/HPPA/copr_dw11.s.cs | 41 + suite/MC/HPPA/float11.s.cs | 89 + suite/MC/HPPA/float20.s.cs | 57 + suite/MC/HPPA/index_mem11.s.cs | 88 + suite/MC/HPPA/longimm20.s.cs | 4 + suite/MC/HPPA/mem_mgmt11.s.cs | 25 + suite/MC/HPPA/memory_reference20.s.cs | 99 + suite/MC/HPPA/multimedia20.s.cs | 14 + suite/MC/HPPA/no_grp11.s.cs | 109 + suite/MC/HPPA/sfu11.s.cs | 5 + suite/MC/HPPA/shexdep11.s.cs | 225 ++ suite/MC/HPPA/sysctrl20.s.cs | 49 + suite/MC/HPPA/system_op11.s.cs | 14 + suite/capstone_get_setup.c | 3 + suite/cstest/include/factory.h | 1 + suite/cstest/src/capstone_test.c | 3 + suite/cstest/src/hppa_detail.c | 96 + suite/cstest/src/main.c | 7 + suite/test_c.sh | 3 +- suite/test_corpus.py | 7 + suite/test_corpus3.py | 6 + suite/test_python.sh | 3 +- tests/Makefile | 4 + tests/test_all.sh | 3 +- tests/test_alpha.c | 2 +- tests/test_basic.c | 36 + tests/test_detail.c | 36 + tests/test_hppa.c | 186 ++ tests/test_iter.c | 37 + 79 files changed, 8639 insertions(+), 20 deletions(-) create mode 100644 arch/HPPA/HPPAConstants.h create mode 100644 arch/HPPA/HPPADisassembler.c create mode 100644 arch/HPPA/HPPADisassembler.h create mode 100644 arch/HPPA/HPPAInstPrinter.c create mode 100644 arch/HPPA/HPPAInstPrinter.h create mode 100644 arch/HPPA/HPPAMapping.c create mode 100644 arch/HPPA/HPPAMapping.h create mode 100644 arch/HPPA/HPPAModule.c create mode 100644 arch/HPPA/HPPAModule.h create mode 100644 bindings/python/capstone/hppa.py create mode 100644 bindings/python/capstone/hppa_const.py create mode 100755 bindings/python/test_hppa.py create mode 100644 cstool/cstool_hppa.c create mode 100644 include/capstone/hppa.h create mode 100644 suite/MC/HPPA/alu11.s.cs create mode 100644 suite/MC/HPPA/arith_imm11.s.cs create mode 100644 suite/MC/HPPA/assist20.s.cs create mode 100644 suite/MC/HPPA/branch11.s.cs create mode 100644 suite/MC/HPPA/branch20.s.cs create mode 100644 suite/MC/HPPA/computation20.s.cs create mode 100644 suite/MC/HPPA/copr_dw11.s.cs create mode 100644 suite/MC/HPPA/float11.s.cs create mode 100644 suite/MC/HPPA/float20.s.cs create mode 100644 suite/MC/HPPA/index_mem11.s.cs create mode 100644 suite/MC/HPPA/longimm20.s.cs create mode 100644 suite/MC/HPPA/mem_mgmt11.s.cs create mode 100644 suite/MC/HPPA/memory_reference20.s.cs create mode 100644 suite/MC/HPPA/multimedia20.s.cs create mode 100644 suite/MC/HPPA/no_grp11.s.cs create mode 100644 suite/MC/HPPA/sfu11.s.cs create mode 100644 suite/MC/HPPA/shexdep11.s.cs create mode 100644 suite/MC/HPPA/sysctrl20.s.cs create mode 100644 suite/MC/HPPA/system_op11.s.cs create mode 100644 suite/cstest/src/hppa_detail.c create mode 100644 tests/test_hppa.c diff --git a/.github/labeler.yml b/.github/labeler.yml index 9ae8548cba..a7c03cea93 100644 --- a/.github/labeler.yml +++ b/.github/labeler.yml @@ -57,6 +57,13 @@ EVM: - include/capstone/evm.h - tests/test_evm.c +HPPA: + - arch/HPPA/* + - cstool/cstool_hppa.c + - include/capstone/hppa.h + - suite/MC/HPPA/* + - tests/test_hppa.c + M680X: - arch/M680X/* - cstool/cstool_m680x.c diff --git a/.gitignore b/.gitignore index 2ffc794f2b..34dbd05bb4 100644 --- a/.gitignore +++ b/.gitignore @@ -75,6 +75,8 @@ tests/test_bpf tests/test_sh tests/test_riscv tests/test_sh +tests/test_alpha +tests/test_hppa # regress binaries suite/regress/invalid_read_in_print_operand diff --git a/CMakeLists.txt b/CMakeLists.txt index 3f0e9dcc1b..2a01ae8b6b 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -64,8 +64,8 @@ if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN) set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64") endif() -set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA) -set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha) +set(SUPPORTED_ARCHITECTURES ARM AARCH64 M68K MIPS PPC SPARC SYSZ XCORE X86 TMS320C64X M680X EVM MOS65XX WASM BPF RISCV SH TRICORE ALPHA HPPA) +set(SUPPORTED_ARCHITECTURE_LABELS ARM AARCH64 M68K MIPS PowerPC Sparc SystemZ XCore x86 TMS320C64x M680x EVM MOS65XX WASM BPF RISCV SH TriCore Alpha HPPA) list(LENGTH SUPPORTED_ARCHITECTURES count) math(EXPR count "${count}-1") @@ -169,6 +169,7 @@ set(HEADERS_COMMON include/capstone/platform.h include/capstone/sh.h include/capstone/alpha.h + include/capstone/hppa.h ) set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c) @@ -617,6 +618,24 @@ if (CAPSTONE_ALPHA_SUPPORT) set(TEST_SOURCES ${TEST_SOURCES} test_alpha.c) endif () +if(CAPSTONE_HPPA_SUPPORT) + add_definitions(-DCAPSTONE_HAS_HPPA) + set(SOURCES_HPPA + arch/HPPA/HPPADisassembler.c + arch/HPPA/HPPAInstPrinter.c + arch/HPPA/HPPAMapping.c + arch/HPPA/HPPAModule.c + ) + set(HEADERS_HPPA + arch/HPPA/HPPAConstants.h + arch/HPPA/HPPADisassembler.h + arch/HPPA/HPPAInstPrinter.h + arch/HPPA/HPPAMapping.h + arch/HPPA/HPPAModule.h + ) + set(TEST_SOURCES ${TEST_SOURCES} test_hppa.c) +endif() + if (CAPSTONE_OSXKERNEL_SUPPORT) add_definitions(-DCAPSTONE_HAS_OSXKERNEL) endif() @@ -642,6 +661,7 @@ set(ALL_SOURCES ${SOURCES_SH} ${SOURCES_TRICORE} ${SOURCES_ALPHA} + ${SOURCES_HPPA} ) set(ALL_HEADERS @@ -666,6 +686,7 @@ set(ALL_HEADERS ${HEADERS_SH} ${HEADERS_TRICORE} ${HEADERS_ALPHA} + ${HEADERS_HPPA} ) ## properties @@ -730,6 +751,7 @@ source_group("Source\\RISCV" FILES ${SOURCES_RISCV}) source_group("Source\\SH" FILES ${SOURCES_SH}) source_group("Source\\TriCore" FILES ${SOURCES_TRICORE}) source_group("Source\\Alpha" FILES ${SOURCES_ALPHA}) +source_group("Source\\HPPA" FILES ${SOURCES_HPPA}) source_group("Include\\Common" FILES ${HEADERS_COMMON}) source_group("Include\\Engine" FILES ${HEADERS_ENGINE}) @@ -752,6 +774,7 @@ source_group("Include\\RISCV" FILES ${HEADERS_RISCV}) source_group("Include\\SH" FILES ${HEADERS_SH}) source_group("Include\\TriCore" FILES ${HEADERS_TRICORE}) source_group("Include\\Alpha" FILES ${HEADERS_ALPHA}) +source_group("Include\\HPPA" FILES ${HEADERS_HPPA}) ## installation if(CAPSTONE_INSTALL) diff --git a/COMPILE.TXT b/COMPILE.TXT index 17e89afc3a..5d914ffc69 100644 --- a/COMPILE.TXT +++ b/COMPILE.TXT @@ -89,6 +89,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. /usr/include/capstone/bpf.h /usr/include/capstone/capstone.h /usr/include/capstone/evm.h + /usr/include/capstone/hppa.h /usr/include/capstone/m680x.h /usr/include/capstone/m68k.h /usr/include/capstone/mips.h diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT index d36bd792e7..dfe491f966 100644 --- a/COMPILE_CMAKE.TXT +++ b/COMPILE_CMAKE.TXT @@ -22,6 +22,7 @@ Get CMake for free from http://www.cmake.org. - CAPSTONE_ARM_SUPPORT: support ARM. Run cmake with -DCAPSTONE_ARM_SUPPORT=0 to remove ARM. - CAPSTONE_AARCH64_SUPPORT: support AARCH64. Run cmake with -DCAPSTONE_AARCH64_SUPPORT=0 to remove AARCH64. - CAPSTONE_ALPHA_SUPPORT: support Alpha. Run cmake with -DCAPSTONE_ALPHA_SUPPORT=0 to remove Alpha. + - CAPSTONE_HPPA_SUPPORT: support HPPA. Run cmake with -DCAPSTONE_HPPA_SUPPORT=0 to remove HPPA. - CAPSTONE_M680X_SUPPORT: support M680X. Run cmake with -DCAPSTONE_M680X_SUPPORT=0 to remove M680X. - CAPSTONE_M68K_SUPPORT: support M68K. Run cmake with -DCAPSTONE_M68K_SUPPORT=0 to remove M68K. - CAPSTONE_MIPS_SUPPORT: support Mips. Run cmake with -DCAPSTONE_MIPS_SUPPORT=0 to remove Mips. @@ -117,7 +118,7 @@ Get CMake for free from http://www.cmake.org. Will just target the x86 architecture. The list of available architectures is: ARM, AARCH64, M68K, MIPS, PowerPC, Sparc, SystemZ, XCore, x86, TMS320C64x, M680x, EVM, MOS65XX, - WASM, BPF, RISCV, Alpha. + WASM, BPF, RISCV, Alpha, HPPA. (4) You can also create an installation image with cmake, by using the 'install' target. Use: diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT index c9d41ae395..6b0d4e14bc 100644 --- a/COMPILE_MSVC.TXT +++ b/COMPILE_MSVC.TXT @@ -33,6 +33,7 @@ or newer versions are required. - CAPSTONE_HAS_ARM: support ARM. Delete this to remove ARM support. - CAPSTONE_HAS_AARCH64: support AARCH64. Delete this to remove AARCH64 support. - CAPSTONE_HAS_ALPHA: support Alpha. Delete this to remove Alpha support. + - CAPSTONE_HAS_HPPA: support HPPA. Delete this to remove HPPA support. - CAPSTONE_HAS_M68K: support M68K. Delete this to remove M68K support. - CAPSTONE_HAS_MIPS: support Mips. Delete this to remove Mips support. - CAPSTONE_HAS_POWERPC: support PPC. Delete this to remove PPC support. diff --git a/CREDITS.TXT b/CREDITS.TXT index e520e70816..81b94a8c0d 100644 --- a/CREDITS.TXT +++ b/CREDITS.TXT @@ -88,4 +88,4 @@ fanfuqiang & citypw & porto703 : RISCV architecture. Josh "blacktop" Maine: Arm64 architecture improvements. Finn Wilkinson: AArch64 update to Armv9.2-a (SME + SVE2 support) Billow & Sidneyp : TriCore architecture. -Dmitry Sibirtsev: Alpha architecture. \ No newline at end of file +Dmitry Sibirtsev: Alpha & HPPA architecture. \ No newline at end of file diff --git a/HACK.TXT b/HACK.TXT index a6b0dd69b4..5858f61cd9 100644 --- a/HACK.TXT +++ b/HACK.TXT @@ -10,6 +10,7 @@ Capstone source is organized as followings. │   ├── ARM <- ARM engine │   ├── BPF <- Berkeley Packet Filter engine │   ├── EVM <- Ethereum engine +│   ├── HPPA <- HPPA engine │   ├── M680X <- M680X engine │   ├── M68K <- M68K engine │   ├── Mips <- Mips engine diff --git a/MCInst.c b/MCInst.c index a0ca8ec6bd..aed26086ae 100644 --- a/MCInst.c +++ b/MCInst.c @@ -36,6 +36,7 @@ void MCInst_Init(MCInst *inst) inst->tied_op_idx[i] = -1; inst->isAliasInstr = false; inst->fillDetailOps = false; + memset(&inst->hppa_ext, 0, sizeof(inst->hppa_ext)); } void MCInst_clear(MCInst *inst) diff --git a/MCInst.h b/MCInst.h index 69c2bb9466..25f8f5c469 100644 --- a/MCInst.h +++ b/MCInst.h @@ -131,6 +131,7 @@ struct MCInst { uint8_t xAcquireRelease; // X86 xacquire/xrelease bool isAliasInstr; // Flag if this MCInst is an alias. bool fillDetailOps; // If set, detail->operands gets filled. + hppa_ext hppa_ext; ///< for HPPA operand. Contains info about modifiers and their effect on the instruction }; void MCInst_Init(MCInst *inst); diff --git a/Makefile b/Makefile index 78f6ab3f51..7a526abd16 100644 --- a/Makefile +++ b/Makefile @@ -335,11 +335,22 @@ ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) LIBOBJ_ALPHA += $(LIBSRC_ALPHA:%.c=$(OBJDIR)/%.o) endif +DEP_HPPA = +DEP_HPPA += $(wildcard arch/HPPA/HPPA*.inc) + +LIBOBJ_HPPA = +ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS))) + CFLAGS += -DCAPSTONE_HAS_HPPA + LIBSRC_HPPA += $(wildcard arch/HPPA/HPPA*.c) + LIBOBJ_HPPA += $(LIBSRC_HPPA:%.c=$(OBJDIR)/%.o) +endif + + LIBOBJ = LIBOBJ += $(OBJDIR)/cs.o $(OBJDIR)/utils.o $(OBJDIR)/SStream.o $(OBJDIR)/MCInstrDesc.o $(OBJDIR)/MCRegisterInfo.o $(OBJDIR)/MCInst.o $(OBJDIR)/MCInstPrinter.o $(OBJDIR)/Mapping.o LIBOBJ += $(LIBOBJ_ARM) $(LIBOBJ_AARCH64) $(LIBOBJ_M68K) $(LIBOBJ_MIPS) $(LIBOBJ_PPC) $(LIBOBJ_RISCV) $(LIBOBJ_SPARC) $(LIBOBJ_SYSZ) $(LIBOBJ_SH) LIBOBJ += $(LIBOBJ_X86) $(LIBOBJ_XCORE) $(LIBOBJ_TMS320C64X) $(LIBOBJ_M680X) $(LIBOBJ_EVM) $(LIBOBJ_MOS65XX) $(LIBOBJ_WASM) $(LIBOBJ_BPF) -LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) +LIBOBJ += $(LIBOBJ_TRICORE) $(LIBOBJ_ALPHA) $(LIBOBJ_HPPA) ifeq ($(PKG_EXTRA),) @@ -476,6 +487,7 @@ $(LIBOBJ_MOS65XX): $(DEP_MOS65XX) $(LIBOBJ_BPF): $(DEP_BPF) $(LIBOBJ_TRICORE): $(DEP_TRICORE) $(LIBOBJ_ALPHA): $(DEP_ALPHA) +$(LIBOBJ_HPPA): $(DEP_HPPA) ifeq ($(CAPSTONE_STATIC),yes) $(ARCHIVE): $(LIBOBJ) @@ -561,13 +573,13 @@ dist: git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip -TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore +TESTS = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore test_hppa TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static -TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static +TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static test_hppa.static check: $(TESTS) diff --git a/Mapping.c b/Mapping.c index 80741a7b20..580db8445b 100644 --- a/Mapping.c +++ b/Mapping.c @@ -334,6 +334,7 @@ DEFINE_get_detail_op(ppc, PPC); DEFINE_get_detail_op(tricore, TriCore); DEFINE_get_detail_op(aarch64, AArch64); DEFINE_get_detail_op(alpha, Alpha); +DEFINE_get_detail_op(hppa, HPPA); /// Returns true if for this architecture the /// alias operands should be filled. diff --git a/Mapping.h b/Mapping.h index 29cc3b9b55..9b5de0afe0 100644 --- a/Mapping.h +++ b/Mapping.h @@ -124,6 +124,7 @@ DECL_get_detail_op(ppc, PPC); DECL_get_detail_op(tricore, TriCore); DECL_get_detail_op(aarch64, AArch64); DECL_get_detail_op(alpha, Alpha); +DECL_get_detail_op(hppa, HPPA); /// Increments the detail->arch.op_count by one. #define DEFINE_inc_detail_op_count(arch, ARCH) \ @@ -149,6 +150,8 @@ DEFINE_inc_detail_op_count(aarch64, AArch64); DEFINE_dec_detail_op_count(aarch64, AArch64); DEFINE_inc_detail_op_count(alpha, Alpha); DEFINE_dec_detail_op_count(alpha, Alpha); +DEFINE_inc_detail_op_count(hppa, HPPA); +DEFINE_dec_detail_op_count(hppa, HPPA); /// Returns true if a memory operand is currently edited. static inline bool doing_mem(const MCInst *MI) @@ -175,6 +178,7 @@ DEFINE_get_arch_detail(ppc, PPC); DEFINE_get_arch_detail(tricore, TriCore); DEFINE_get_arch_detail(aarch64, AArch64); DEFINE_get_arch_detail(alpha, Alpha); +DEFINE_get_arch_detail(hppa, HPPA); static inline bool detail_is_set(const MCInst *MI) { diff --git a/MathExtras.h b/MathExtras.h index e0f37a5bae..eb3b989713 100644 --- a/MathExtras.h +++ b/MathExtras.h @@ -430,6 +430,12 @@ static inline int64_t SignExtend64(uint64_t X, unsigned B) { return (int64_t)(X << (64 - B)) >> (64 - B); } +/// \brief Removes the rightmost bit of x and extends the field to the left with that +/// bit to form a 64-bit quantity. The field is of size len +static inline int64_t LowSignExtend64(uint64_t x, unsigned len) { + return (x >> 1) - ((x & 1) << (len - 1)); +} + /// \brief One extend number X starting at bit B and returns it as int32_t. /// Requires 0 < B <= 32. static inline int32_t OneExtend32(uint32_t X, unsigned B) { @@ -467,4 +473,16 @@ static inline unsigned int countLeadingZeros(int x) return count; } +/// \brief Get specified field from 32-bit instruction. Returns bits from the segment [from, to] +static inline uint32_t get_insn_field(uint32_t insn, uint8_t from, uint8_t to) +{ + return insn >> (31 - to) & ((1 << (to - from + 1)) - 1); +} + +/// \brief Get specified bit from 32-bit instruction +static inline uint32_t get_insn_bit(uint32_t insn, uint8_t bit) +{ + return get_insn_field(insn, bit, bit); +} + #endif diff --git a/arch/HPPA/HPPAConstants.h b/arch/HPPA/HPPAConstants.h new file mode 100644 index 0000000000..d2ebb61b79 --- /dev/null +++ b/arch/HPPA/HPPAConstants.h @@ -0,0 +1,74 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +/* This file defines constants and macros used for parsing a HPPA instruction */ + +#ifndef CS_HPPA_CONSTANTS_H +#define CS_HPPA_CONSTANTS_H + +#define HPPA_OP_TYPE(byte) (byte) >> 2 +#define MODE_IS_HPPA_20(mode) (((mode)&CS_MODE_HPPA_20) != 0) +#define MODE_IS_HPPA_20W(mode) (((mode) & (1 << 3)) != 0) + +///> HPPA opcode types +#define HPPA_OP_TYPE_SYSOP 0x00 +#define HPPA_OP_TYPE_MEMMGMT 0x01 +#define HPPA_OP_TYPE_ALU 0x02 +#define HPPA_OP_TYPE_IDXMEM 0x03 +#define HPPA_OP_TYPE_SPOP 0x04 +#define HPPA_OP_TYPE_DIAG 0x05 +#define HPPA_OP_TYPE_FMPYADD 0x06 +#define HPPA_OP_TYPE_LDIL 0x08 +#define HPPA_OP_TYPE_COPRW 0x09 +#define HPPA_OP_TYPE_ADDIL 0x0a +#define HPPA_OP_TYPE_COPRDW 0x0b +#define HPPA_OP_TYPE_COPR 0x0c +#define HPPA_OP_TYPE_LDO 0x0d +#define HPPA_OP_TYPE_FLOAT 0x0e +#define HPPA_OP_TYPE_PRDSPEC 0x0f +#define HPPA_OP_TYPE_LDB 0x10 +#define HPPA_OP_TYPE_LDH 0x11 +#define HPPA_OP_TYPE_LDW 0x12 +#define HPPA_OP_TYPE_LDWM 0x13 +#define HPPA_OP_TYPE_LOADDW 0x14 +#define HPPA_OP_TYPE_FLDW 0x16 +#define HPPA_OP_TYPE_LOADW 0x17 +#define HPPA_OP_TYPE_STB 0x18 +#define HPPA_OP_TYPE_STH 0x19 +#define HPPA_OP_TYPE_STW 0x1a +#define HPPA_OP_TYPE_STWM 0x1b +#define HPPA_OP_TYPE_STOREDW 0x1c +#define HPPA_OP_TYPE_FSTW 0x1e +#define HPPA_OP_TYPE_STOREW 0x1f +#define HPPA_OP_TYPE_CMPBT 0x20 +#define HPPA_OP_TYPE_CMPIBT 0x21 +#define HPPA_OP_TYPE_CMPBF 0x22 +#define HPPA_OP_TYPE_CMPIBF 0x23 +#define HPPA_OP_TYPE_CMPICLR 0x24 +#define HPPA_OP_TYPE_SUBI 0x25 +#define HPPA_OP_TYPE_FMPYSUB 0x26 +#define HPPA_OP_TYPE_CMPBDWT 0x27 +#define HPPA_OP_TYPE_ADDBT 0x28 +#define HPPA_OP_TYPE_ADDIBT 0x29 +#define HPPA_OP_TYPE_ADDBF 0x2a +#define HPPA_OP_TYPE_ADDIBF 0x2b +#define HPPA_OP_TYPE_ADDIT 0x2c +#define HPPA_OP_TYPE_ADDI 0x2d +#define HPPA_OP_TYPE_FPFUSED 0x2e +#define HPPA_OP_TYPE_CMPBDWF 0x2f +#define HPPA_OP_TYPE_BBS 0x30 +#define HPPA_OP_TYPE_BB 0x31 +#define HPPA_OP_TYPE_MOVB 0x32 +#define HPPA_OP_TYPE_MOVIB 0x33 +#define HPPA_OP_TYPE_SHEXDEP0 0x34 +#define HPPA_OP_TYPE_SHEXDEP1 0x35 +#define HPPA_OP_TYPE_SHEXDEP2 0x36 +#define HPPA_OP_TYPE_BE 0x38 +#define HPPA_OP_TYPE_BLE 0x39 +#define HPPA_OP_TYPE_BRANCH 0x3a +#define HPPA_OP_TYPE_CMPIBDW 0x3b +#define HPPA_OP_TYPE_SHEXDEP3 0x3c +#define HPPA_OP_TYPE_SHEXDEP4 0x3d +#define HPPA_OP_TYPE_MULTMED 0x3e + +#endif // CS_HPPA_CONSTANTS_H \ No newline at end of file diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c new file mode 100644 index 0000000000..b962f2d521 --- /dev/null +++ b/arch/HPPA/HPPADisassembler.c @@ -0,0 +1,3837 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include +#include // offsetof macro +#include +#include "HPPADisassembler.h" +#include "HPPAConstants.h" + +#include "../../Mapping.h" +#include "../../MathExtras.h" +#include "../../utils.h" + +#define CMPLT_HAS_MODIFY_BIT(CMPLT) (((CMPLT)&1) == 1) + +#define HPPA_EXT_REF(MI) (&MI->hppa_ext) + +static const char *const compare_cond_names[] = { + "", "=", "<", "<=", "<<", "<<=", "sv", "od", + "tr", "<>", ">=", ">", ">>=", ">>", "nsv", "ev" +}; +static const char *const compare_cond_64_names[] = { + "*", "*=", "*<", "*<=", "*<<", "*<<=", "*sv", "*od", + "*tr", "*<>", "*>=", "*>", "*>>=", "*>>", "*nsv", "*ev" +}; +static const char *const cmpib_cond_64_names[] = { "*<<", "*=", "*<", "*<=", + "*>>=", "*<>", "*>=", "*>" }; +static const char *const add_cond_names[] = { + "", "=", "<", "<=", "nuv", "znv", "sv", "od", + "tr", "<>", ">=", ">", "uv", "vnz", "nsv", "ev" +}; +static const char *const add_cond_64_names[] = { + "*", "*=", "*<", "*<=", "*nuv", "*znv", "*sv", "*od", + "*tr", "*<>", "*>=", "*>", "*uv", "*vnz", "*nsv", "*ev" +}; +static const char *const wide_add_cond_names[] = { + "*", "=", "<", "<=", "nuv", "*=", "*<", "*<=", + "tr", "<>", ">=", ">", "uv", "*<>", "*>=", "*>" +}; +static const char *const logical_cond_names[] = { + "", "=", "<", "<=", "", "", "", "od", + "tr", "<>", ">=", ">", "", "", "", "ev" +}; +static const char *const logical_cond_64_names[] = { + "*", "*=", "*<", "*<=", "", "", "", "*od", + "*tr", "*<>", "*>=", "*>", "", "", "", "*ev" +}; +static const char *const unit_cond_names[] = { "", "swz", "sbz", "shz", + "sdc", "swc", "sbc", "shc", + "tr", "nwz", "nbz", "nhz", + "ndc", "nwc", "nbc", "nhc" }; +static const char *const unit_cond_64_names[] = { + "*", "*swz", "*sbz", "*shz", "*sdc", "*swc", "*sbc", "*shc", + "*tr", "*nwz", "*nbz", "*nhz", "*ndc", "*nwc", "*nbc", "*nhc" +}; +static const char *const shift_cond_names[] = { "", "=", "<", "od", + "tr", "<>", ">=", "ev" }; +static const char *const shift_cond_64_names[] = { "*", "*=", "*<", "*od", + "*tr", "*<>", "*>=", "*ev" }; +static const char *const index_compl_names[] = { "", "m", "s", "sm" }; +static const char *const short_ldst_compl_names[] = { "", "ma", "", "mb" }; +static const char *const short_bytes_compl_names[] = { "", "b,m", "e", "e,m" }; +static const char *const float_format_names[] = { "sgl", "dbl", "", "quad" }; +static const char *const float_cond_names[] = { + "", "acc", "rej", "", "", "acc8", "rej8", "", "", "acc6", "", + "", "", "acc4", "", "", "", "acc2", "", "", "", "", + "", "", "", "", "", "", "", "", "", "" +}; +static const char *const fcnv_fixed_names[] = { "w", "dw", "", "qw" }; +static const char *const fcnv_ufixed_names[] = { "uw", "udw", "", "uqw" }; +static const char *const float_comp_names[] = { + "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", + "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", + "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", + "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" +}; +static const char *const signed_unsigned_names[] = { "u", "s" }; +static const char *const saturation_names[] = { "us", "ss", "", "" }; +static const char *const add_compl_names[] = { "", "", "l", "tsv" }; + +#define CREATE_GR_REG(MI, gr) MCOperand_CreateReg0(MI, gr + HPPA_REG_GR0) +#define CREATE_SR_REG(MI, sr) MCOperand_CreateReg0(MI, sr + HPPA_REG_SR0) +#define CREATE_CR_REG(MI, cr) MCOperand_CreateReg0(MI, cr + HPPA_REG_CR0) +#define CREATE_FPR_REG(MI, fpr) MCOperand_CreateReg0(MI, fpr + HPPA_REG_FPR0) +#define CREATE_FPE_REG(MI, fpe) MCOperand_CreateReg0(MI, fpe + HPPA_REG_FPE0) +#define CREATE_SP_FPR_REG(MI, fpr) \ + MCOperand_CreateReg0(MI, fpr + HPPA_REG_SP_FPR0) + +static void create_float_reg_spec(MCInst *MI, uint32_t reg, uint32_t fpe_flag) +{ + if (fpe_flag == 1) { + CREATE_FPE_REG(MI, reg); + } else { + CREATE_FPR_REG(MI, reg); + } +} + +/* Get at various relevant fields of an instruction word. */ + +#define MASK_5 0x1f +#define MASK_10 0x3ff +#define MASK_11 0x7ff +#define MASK_14 0x3fff +#define MASK_16 0xffff +#define MASK_21 0x1fffff + +/* Routines to extract various sized constants out of hppa + instructions. */ + +/* Extract a 3-bit space register number from a be, ble, mtsp or mfsp. */ +static int extract_3(unsigned word) +{ + return get_insn_field(word, 18, 18) << 2 | get_insn_field(word, 16, 17); +} + +static int extract_5_load(unsigned word) +{ + return LowSignExtend64(word >> 16 & MASK_5, 5); +} + +/* Extract the immediate field from a st{bhw}s instruction. */ + +static int extract_5_store(unsigned word) +{ + return LowSignExtend64(word & MASK_5, 5); +} + +/* Extract an 11 bit immediate field. */ + +static int extract_11(unsigned word) +{ + return LowSignExtend64(word & MASK_11, 11); +} + +/* Extract a 14 bit immediate field. */ + +static int extract_14(unsigned word) +{ + return LowSignExtend64(word & MASK_14, 14); +} + +/* Extract a 16 bit immediate field. */ + +static int extract_16(unsigned word, bool wide) +{ + int m15, m0, m1; + + m0 = get_insn_bit(word, 16); + m1 = get_insn_bit(word, 17); + m15 = get_insn_bit(word, 31); + word = (word >> 1) & 0x1fff; + if (wide) { + word = word | (m15 << 15) | ((m15 ^ m0) << 14) | + ((m15 ^ m1) << 13); + } else { + word = word | (m15 << 15) | (m15 << 14) | (m15 << 13); + } + return SignExtend32(word, 16); +} + +/* Extract a 21 bit constant. */ + +static int extract_21(unsigned word) +{ + int val; + + word &= MASK_21; + word <<= 11; + val = get_insn_field(word, 20, 20); + val <<= 11; + val |= get_insn_field(word, 9, 19); + val <<= 2; + val |= get_insn_field(word, 5, 6); + val <<= 5; + val |= get_insn_field(word, 0, 4); + val <<= 2; + val |= get_insn_field(word, 7, 8); + return SignExtend32(val, 21) << 11; +} + +/* Extract a 12 bit constant from branch instructions. */ + +static int extract_12(unsigned word) +{ + return SignExtend32(get_insn_field(word, 19, 28) | + get_insn_field(word, 29, 29) << 10 | + (word & 0x1) << 11, + 12) + << 2; +} + +/* Extract a 17 bit constant from branch instructions, returning the + 19 bit signed value. */ + +static int extract_17(unsigned word) +{ + return SignExtend32(get_insn_field(word, 19, 28) | + get_insn_field(word, 29, 29) << 10 | + get_insn_field(word, 11, 15) << 11 | + (word & 0x1) << 16, + 17) + << 2; +} + +static int extract_22(unsigned word) +{ + return SignExtend32(get_insn_field(word, 19, 28) | + get_insn_field(word, 29, 29) << 10 | + get_insn_field(word, 11, 15) << 11 | + get_insn_field(word, 6, 10) << 16 | + (word & 0x1) << 21, + 22) + << 2; +} + +static void push_str_modifier(hppa_ext *hppa, const char *modifier) +{ + if (strcmp(modifier, "")) { + hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; + assert(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); + mod->type = HPPA_MOD_STR; + assert(strlen(modifier) <= HPPA_STR_MODIFIER_LEN); + strcpy(mod->str_mod, modifier); + } +} + +static void push_int_modifier(hppa_ext *hppa, uint64_t modifier) +{ + hppa_modifier *mod = &hppa->modifiers[hppa->mod_num++]; + assert(hppa->mod_num <= HPPA_MAX_MODIFIERS_LEN); + mod->type = HPPA_MOD_INT; + mod->int_mod = modifier; +} + +static void fill_sysop_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext8 = get_insn_field(insn, 19, 26); + uint32_t ext5 = get_insn_field(insn, 11, 15); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext8) { + case 0xa5: + MCInst_setOpcode(MI, HPPA_INS_MFIA); + return; + case 0xc6: + MCInst_setOpcode(MI, HPPA_INS_MTSARCM); + return; + case 0x65: + push_str_modifier(HPPA_EXT_REF(MI), "r"); + // fallthrough + case 0x60: + MCInst_setOpcode(MI, HPPA_INS_RFI); + return; + default: + break; + } + } + + switch (ext8) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_BREAK); + break; + case 0x20: + if (ext5 == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_SYNC); + } else if (ext5 == 0x10) { + MCInst_setOpcode(MI, HPPA_INS_SYNCDMA); + } + break; + case 0x60: + MCInst_setOpcode(MI, HPPA_INS_RFI); + break; + case 0x65: + MCInst_setOpcode(MI, HPPA_INS_RFIR); + break; + case 0x6b: + MCInst_setOpcode(MI, HPPA_INS_SSM); + break; + case 0x73: + MCInst_setOpcode(MI, HPPA_INS_RSM); + break; + case 0xc3: + MCInst_setOpcode(MI, HPPA_INS_MTSM); + break; + case 0x85: + MCInst_setOpcode(MI, HPPA_INS_LDSID); + break; + case 0xc1: + MCInst_setOpcode(MI, HPPA_INS_MTSP); + break; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_MFSP); + break; + case 0xc2: + MCInst_setOpcode(MI, HPPA_INS_MTCTL); + break; + case 0x45: + MCInst_setOpcode(MI, HPPA_INS_MFCTL); + if (get_insn_bit(insn, 17) == 1 && + MODE_IS_HPPA_20(MI->csh->mode)) { + push_str_modifier(HPPA_EXT_REF(MI), "w"); + } + break; + default: + break; + } +} + +static bool decode_sysop(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext8 = get_insn_field(insn, 19, 26); + uint32_t ext5 = get_insn_field(insn, 11, 15); + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t s = extract_3(insn); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext8) { + case 0xa5: + if (ext5 != 0) { + return false; + } + CREATE_GR_REG(MI, t); + return true; + case 0xc6: + CREATE_GR_REG(MI, r2); + return true; + default: + break; + } + } + + switch (ext8) { + case 0x00: + MCOperand_CreateImm0(MI, t); + MCOperand_CreateImm0(MI, get_insn_field(insn, 6, 18)); + return true; + case 0x20: + if (ext5 != 0x00 && ext5 != 0x10) { + return false; + } + // fallthrough + case 0x60: + case 0x65: + return true; + case 0x6b: + case 0x73: + MCOperand_CreateImm0(MI, get_insn_field(insn, 9, 15)); + CREATE_GR_REG(MI, t); + return true; + case 0xc3: + CREATE_GR_REG(MI, r2); + return true; + case 0x85: + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, t); + return true; + case 0xc1: + CREATE_GR_REG(MI, r2); + CREATE_SR_REG(MI, s); + return true; + case 0x25: + if (ext5 != 0) { + return false; + } + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, t); + return true; + case 0xc2: + CREATE_GR_REG(MI, r2); + CREATE_CR_REG(MI, r1); + return true; + case 0x45: + if (ext5 != 0) { + return false; + } + if (get_insn_bit(insn, 17) == 1 && MODE_IS_HPPA_20(ud->mode) && + r1 != 11) { + return false; + } + CREATE_CR_REG(MI, r1); + CREATE_GR_REG(MI, t); + return true; + default: + return false; + } +} + +static void fill_memmgmt_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x20: + MCInst_setOpcode(MI, HPPA_INS_IITLBT); + return; + case 0x18: + MCInst_setOpcode(MI, HPPA_INS_PITLB); + push_str_modifier(HPPA_EXT_REF(MI), "l"); + return; + case 0x60: + MCInst_setOpcode(MI, HPPA_INS_IDTLBT); + return; + case 0x58: + MCInst_setOpcode(MI, HPPA_INS_PDTLB); + push_str_modifier(HPPA_EXT_REF(MI), "l"); + return; + case 0x4f: + MCInst_setOpcode(MI, HPPA_INS_FIC); + return; + case 0x46: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBE); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBEI); + }; + push_str_modifier(HPPA_EXT_REF(MI), "r"); + return; + case 0x47: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBE); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBEI); + }; + push_str_modifier(HPPA_EXT_REF(MI), "w"); + return; + default: + break; + } + } + + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_IITLBP); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_IITLBA); + break; + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_PITLB); + break; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_PITLBE); + break; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_FIC); + break; + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_FICE); + break; + case 0x40: + MCInst_setOpcode(MI, HPPA_INS_IDTLBP); + break; + case 0x41: + MCInst_setOpcode(MI, HPPA_INS_IDTLBA); + break; + case 0x48: + MCInst_setOpcode(MI, HPPA_INS_PDTLB); + break; + case 0x49: + MCInst_setOpcode(MI, HPPA_INS_PDTLBE); + break; + case 0x4a: + MCInst_setOpcode(MI, HPPA_INS_FDC); + break; + case 0x4b: + MCInst_setOpcode(MI, HPPA_INS_FDCE); + break; + case 0x4e: + MCInst_setOpcode(MI, HPPA_INS_PDC); + break; + case 0x46: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBER); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBERI); + }; + break; + case 0x47: + if (get_insn_bit(insn, 18) == 0) { + MCInst_setOpcode(MI, HPPA_INS_PROBEW); + } else { + MCInst_setOpcode(MI, HPPA_INS_PROBEWI); + }; + break; + case 0x4d: + MCInst_setOpcode(MI, HPPA_INS_LPA); + break; + case 0x4c: + MCInst_setOpcode(MI, HPPA_INS_LCI); + break; + default: + break; + } +} + +static void fill_memmgmt_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint8_t cmplt = get_insn_bit(insn, 26); + uint32_t ext = get_insn_field(insn, 19, 25); + if (MODE_IS_HPPA_20(mode)) { + switch (ext) { + case 0x18: + case 0x58: + case 0x4f: + goto success; + default: + break; + } + } + + switch (ext) { + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4e: + case 0x4d: + break; + default: + return; + } +success: + if (CMPLT_HAS_MODIFY_BIT(cmplt)) { + hppa_ext->b_writeble = true; + } + push_str_modifier(hppa_ext, index_compl_names[cmplt]); +} + +static bool decode_memmgmt(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 25); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t s3 = extract_3(insn); + uint32_t s2 = get_insn_field(insn, 16, 17); + uint32_t t = get_insn_field(insn, 27, 31); + if (ext > 0x20 && get_insn_bit(insn, 18) == 1 && + (ext != 0x46 && ext != 0x47)) { + if (MODE_IS_HPPA_20(ud->mode)) { + if (ext != 0x4a) { + return false; + } + } else { + return false; + } + } + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x20: + case 0x60: + CREATE_GR_REG(MI, r); + CREATE_GR_REG(MI, b); + goto success; + case 0x58: + case 0x4f: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + goto success; + case 0x18: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s3); + CREATE_GR_REG(MI, b); + goto success; + case 0x4a: + if (get_insn_bit(insn, 18) == 1) { + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + } else { + CREATE_GR_REG(MI, r); + } + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + goto success; + default: + break; + } + } + + switch (ext) { + case 0x00: + case 0x01: + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s3); + CREATE_GR_REG(MI, b); + break; + case 0x40: + case 0x41: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4e: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + break; + case 0x46: + case 0x47: + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + if (get_insn_bit(insn, 18) == 0) { + CREATE_GR_REG(MI, r); + } else { + MCOperand_CreateImm0(MI, r); + } + CREATE_GR_REG(MI, t); + break; + case 0x4d: + case 0x4c: + CREATE_GR_REG(MI, r); + CREATE_SR_REG(MI, s2); + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } +success: + fill_memmgmt_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode); + return true; +} + +static void fill_alu_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 20, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x28: + case 0x38: + case 0x1c: + case 0x3c: + MCInst_setOpcode(MI, HPPA_INS_ADD); + return; + case 0x19: + case 0x29: + case 0x39: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x1b: + case 0x2b: + case 0x3b: + MCInst_setOpcode(MI, HPPA_INS_SHLADD); + return; + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + MCInst_setOpcode(MI, HPPA_INS_SUB); + return; + case 0x22: + MCInst_setOpcode(MI, HPPA_INS_CMPCLR); + return; + case 0x27: + MCInst_setOpcode(MI, HPPA_INS_UADDCM); + return; + case 0x2f: + MCInst_setOpcode(MI, HPPA_INS_DCOR); + return; + case 0x0f: + case 0x0d: + case 0x0c: + MCInst_setOpcode(MI, HPPA_INS_HADD); + return; + case 0x07: + case 0x05: + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_HSUB); + return; + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_HAVG); + return; + case 0x1d: + case 0x1e: + case 0x1f: + MCInst_setOpcode(MI, HPPA_INS_HSHLADD); + return; + case 0x15: + case 0x16: + case 0x17: + MCInst_setOpcode(MI, HPPA_INS_HSHRADD); + return; + default: + break; + } + } + + switch (ext) { + case 0x18: + MCInst_setOpcode(MI, HPPA_INS_ADD); + break; + case 0x38: + MCInst_setOpcode(MI, HPPA_INS_ADDO); + break; + case 0x1c: + MCInst_setOpcode(MI, HPPA_INS_ADDC); + break; + case 0x3c: + MCInst_setOpcode(MI, HPPA_INS_ADDCO); + break; + case 0x19: + MCInst_setOpcode(MI, HPPA_INS_SH1ADD); + break; + case 0x39: + MCInst_setOpcode(MI, HPPA_INS_SH1ADDO); + break; + case 0x1a: + MCInst_setOpcode(MI, HPPA_INS_SH2ADD); + break; + case 0x3a: + MCInst_setOpcode(MI, HPPA_INS_SH2ADDO); + break; + case 0x1b: + MCInst_setOpcode(MI, HPPA_INS_SH3ADD); + break; + case 0x3b: + MCInst_setOpcode(MI, HPPA_INS_SH3ADDO); + break; + case 0x10: + MCInst_setOpcode(MI, HPPA_INS_SUB); + break; + case 0x30: + MCInst_setOpcode(MI, HPPA_INS_SUBO); + break; + case 0x13: + MCInst_setOpcode(MI, HPPA_INS_SUBT); + break; + case 0x33: + MCInst_setOpcode(MI, HPPA_INS_SUBTO); + break; + case 0x14: + MCInst_setOpcode(MI, HPPA_INS_SUBB); + break; + case 0x34: + MCInst_setOpcode(MI, HPPA_INS_SUBBO); + break; + case 0x11: + MCInst_setOpcode(MI, HPPA_INS_DS); + break; + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_ANDCM); + break; + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_AND); + break; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_OR); + break; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_XOR); + break; + case 0x0e: + MCInst_setOpcode(MI, HPPA_INS_UXOR); + break; + case 0x22: + MCInst_setOpcode(MI, HPPA_INS_COMCLR); + break; + case 0x26: + MCInst_setOpcode(MI, HPPA_INS_UADDCM); + break; + case 0x27: + MCInst_setOpcode(MI, HPPA_INS_UADDCMT); + break; + case 0x28: + MCInst_setOpcode(MI, HPPA_INS_ADDL); + break; + case 0x29: + MCInst_setOpcode(MI, HPPA_INS_SH1ADDL); + break; + case 0x2a: + MCInst_setOpcode(MI, HPPA_INS_SH2ADDL); + break; + case 0x2b: + MCInst_setOpcode(MI, HPPA_INS_SH3ADDL); + break; + case 0x2e: + MCInst_setOpcode(MI, HPPA_INS_DCOR); + break; + case 0x2f: + MCInst_setOpcode(MI, HPPA_INS_IDCOR); + break; + default: + break; + } +} + +static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = (get_insn_field(insn, 19, 19) << 3) | + get_insn_field(insn, 16, 18); + uint32_t ext = get_insn_field(insn, 20, 25); + if (MODE_IS_HPPA_20(mode)) { + uint32_t e1 = get_insn_field(insn, 20, 21); + uint32_t e2 = get_insn_bit(insn, 23); + uint32_t e3 = get_insn_field(insn, 24, 25); + uint32_t d = get_insn_bit(insn, 26); + switch (ext) { + case 0x18: + case 0x28: + case 0x38: + case 0x1c: + case 0x3c: + if (e2 == 1) { + if (d == 1) { + push_str_modifier(hppa_ext, "dc"); + } else { + push_str_modifier(hppa_ext, "c"); + } + } + // fallthrough + case 0x19: + case 0x29: + case 0x39: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x1b: + case 0x2b: + case 0x3b: + push_str_modifier(hppa_ext, add_compl_names[e1]); + if (d == 1) { + push_str_modifier(hppa_ext, + add_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + add_cond_names[cond]); + } + return; + case 0x10: + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + if (e2 == 1) { + if (d == 1) { + push_str_modifier(hppa_ext, "db"); + } else { + push_str_modifier(hppa_ext, "b"); + } + } + if (e1 == 3) { + push_str_modifier(hppa_ext, "tsv"); + } + if (e3 == 3) { + push_str_modifier(hppa_ext, "tc"); + } + // fallthrough + case 0x22: + if (d == 1) { + push_str_modifier(hppa_ext, + compare_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + compare_cond_names[cond]); + } + return; + case 0x00: + case 0x08: + case 0x09: + case 0x0a: + if (d == 1) { + push_str_modifier(hppa_ext, + logical_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + logical_cond_names[cond]); + } + return; + case 0x27: + push_str_modifier(hppa_ext, "tc"); + goto unit_cond; + case 0x2f: + push_str_modifier(hppa_ext, "i"); + // fallthough + case 0x26: + case 0x0e: + case 0x2e: +unit_cond: + if (d == 1) { + push_str_modifier(hppa_ext, + unit_cond_64_names[cond]); + } else { + push_str_modifier(hppa_ext, + unit_cond_names[cond]); + } + return; + case 0x0d: + case 0x0c: + case 0x05: + case 0x04: + push_str_modifier(hppa_ext, saturation_names[e3]); + return; + default: + break; + } + } + + switch (ext) { + case 0x18: + case 0x38: + case 0x1c: + case 0x3c: + case 0x19: + case 0x39: + case 0x1a: + case 0x3a: + case 0x3b: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + push_str_modifier(hppa_ext, add_cond_names[cond]); + break; + case 0x10: + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + case 0x11: + case 0x22: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + case 0x00: + case 0x08: + case 0x09: + case 0x0a: + push_str_modifier(hppa_ext, logical_cond_names[cond]); + break; + case 0x0e: + case 0x26: + case 0x27: + case 0x2e: + case 0x2f: + push_str_modifier(hppa_ext, unit_cond_names[cond]); + break; + default: + break; + } +} + +static bool decode_alu(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 20, 25); + uint32_t r1 = get_insn_field(insn, 11, 15); + uint32_t r2 = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x19: + case 0x29: + case 0x39: + case 0x1a: + case 0x2a: + case 0x3a: + case 0x1b: + case 0x2b: + case 0x3b: + case 0x1d: + case 0x1e: + case 0x1f: + case 0x15: + case 0x16: + case 0x17: + case 0x0f: + case 0x0d: + case 0x0c: + case 0x07: + case 0x05: + case 0x04: + case 0x0b: + CREATE_GR_REG(MI, r1); + if (ext > 0x10) { + MCOperand_CreateImm0( + MI, get_insn_field(insn, 24, 25)); + } + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + goto success; + default: + break; + } + } + switch (ext) { + case 0x18: + case 0x38: + case 0x1c: + case 0x3c: + case 0x19: + case 0x39: + case 0x1a: + case 0x3a: + case 0x1b: + case 0x3b: + case 0x10: + case 0x30: + case 0x13: + case 0x33: + case 0x14: + case 0x34: + case 0x11: + case 0x00: + case 0x08: + case 0x09: + case 0x0a: + case 0x0e: + case 0x22: + case 0x26: + case 0x27: + case 0x28: + case 0x29: + case 0x2a: + case 0x2b: + CREATE_GR_REG(MI, r1); + // fallthrough + case 0x2e: + case 0x2f: + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } +success: + fill_alu_mods(insn, HPPA_EXT_REF(MI), MI->csh->mode); + return true; +} + +static void fill_idxmem_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 22, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_LDB); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_LDH); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_LDW); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_LDD); + return; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_LDDA); + return; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_LDCD); + return; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_LDWA); + return; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_LDCW); + return; + default: + break; + } + if (get_insn_bit(insn, 19) == 1) { + switch (ext) { + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_STB); + return; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_STH); + return; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_STW); + return; + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_STD); + return; + case 0x0c: + MCInst_setOpcode(MI, HPPA_INS_STBY); + return; + case 0x0d: + MCInst_setOpcode(MI, HPPA_INS_STDBY); + return; + case 0x0e: + MCInst_setOpcode(MI, HPPA_INS_STWA); + return; + case 0x0f: + MCInst_setOpcode(MI, HPPA_INS_STDA); + return; + default: + break; + } + } + } + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_LDBX); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_LDHX); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_LDWX); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_LDCWX); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_LDWAX); + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_LDBS); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_LDHS); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_LDWS); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_LDCWS); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_LDWAS); + break; + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_STBS); + break; + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_STHS); + break; + case 0x0a: + MCInst_setOpcode(MI, HPPA_INS_STWS); + break; + case 0x0c: + MCInst_setOpcode(MI, HPPA_INS_STBYS); + break; + case 0x0e: + MCInst_setOpcode(MI, HPPA_INS_STWAS); + break; + default: + break; + } + } +} + +static void fill_idxmem_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode, + uint32_t im5) +{ + uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26); + uint32_t cc = get_insn_field(insn, 20, 21); + uint32_t ext = get_insn_field(insn, 22, 25); + if (CMPLT_HAS_MODIFY_BIT(cmplt)) { + hppa_ext->b_writeble = true; + } + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + push_str_modifier(hppa_ext, index_compl_names[cmplt]); + if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + case 0x05: + case 0x07: + push_str_modifier(hppa_ext, index_compl_names[cmplt]); + if (cc == 1) { + push_str_modifier(hppa_ext, "co"); + } + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + case 0x04: + case 0x06: + if (cmplt == 1 && im5 == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier( + hppa_ext, + short_ldst_compl_names[cmplt]); + } + if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + case 0x05: + case 0x07: + if (cmplt == 1 && im5 == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier( + hppa_ext, + short_ldst_compl_names[cmplt]); + } + if (cc == 1) { + push_str_modifier(hppa_ext, "co"); + } + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0b: + case 0x0e: + case 0x0f: + if (cmplt == 1 && im5 == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier( + hppa_ext, + short_ldst_compl_names[cmplt]); + } + if (cc == 1) { + push_str_modifier(hppa_ext, "bc"); + } else if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + case 0x0c: + case 0x0d: + push_str_modifier(hppa_ext, + short_bytes_compl_names[cmplt]); + if (cc == 1) { + push_str_modifier(hppa_ext, "bc"); + } else if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } + break; + default: + break; + } + } +} + +static bool decode_idxmem(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 22, 25); + uint32_t im5; + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t s = get_insn_field(insn, 16, 17); + if (MODE_IS_HPPA_20(ud->mode)) { + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x03: + case 0x05: + case 0x04: + CREATE_GR_REG(MI, r); + if (ext != 0x04) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), + ud->mode, -1); + return true; + default: + break; + } + } else { + switch (ext) { + case 0x03: + case 0x05: + case 0x04: + im5 = extract_5_load(insn); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x04) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), + ud->mode, im5); + return true; + case 0x0b: + case 0x0d: + case 0x0f: + im5 = extract_5_store(insn); + CREATE_GR_REG(MI, r); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x0f) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), + ud->mode, im5); + return true; + default: + break; + } + } + } + if (get_insn_bit(insn, 19) == 0) { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x07: + case 0x06: + CREATE_GR_REG(MI, r); + if (ext != 0x06) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1); + return true; + } else { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x07: + case 0x06: + im5 = extract_5_load(insn); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x06) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + CREATE_GR_REG(MI, t); + break; + case 0x08: + case 0x09: + case 0x0a: + case 0x0c: + case 0x0e: + im5 = extract_5_store(insn); + CREATE_GR_REG(MI, r); + MCOperand_CreateImm0(MI, im5); + if (ext != 0x0e) { + CREATE_SR_REG(MI, s); + } + CREATE_GR_REG(MI, b); + break; + default: + return false; + } + if (MODE_IS_HPPA_20(ud->mode)) { + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, im5); + } else { + fill_idxmem_mods(insn, HPPA_EXT_REF(MI), ud->mode, -1); + } + return true; + } +} + +static void fill_ldst_dw_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t ext = get_insn_bit(insn, 30); + if (opcode == 0x14) { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_LDD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FLDD); + } + } else { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_STD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FSTD); + } + } +} + +static void fill_ldst_dw_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im) +{ + uint32_t cmplt = (get_insn_bit(insn, 29) << 1) | get_insn_bit(insn, 28); + if (cmplt == 1 && im == 0) { + push_str_modifier(hppa_ext, "o"); + } else { + push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]); + } +} + +static bool decode_ldst_dw(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + im &= ~7; + uint32_t ext = get_insn_bit(insn, 30); + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t s = get_insn_field(insn, 16, 17); + if (opcode == HPPA_OP_TYPE_LOADDW) { + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + if (ext == 0) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + } else { + if (ext == 0) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + } + fill_ldst_dw_mods(insn, HPPA_EXT_REF(MI), im); + return true; +} + +static void fill_ldst_w_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t ext = get_insn_bit(insn, 29); + if (opcode == 0x17) { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_FLDW); + } else { + MCInst_setOpcode(MI, HPPA_INS_LDW); + } + } else { + if (ext == 0) { + MCInst_setOpcode(MI, HPPA_INS_FSTW); + } else { + MCInst_setOpcode(MI, HPPA_INS_STW); + } + } +} + +static void fill_ldst_w_mods(uint32_t insn, hppa_ext *hppa_ext, uint32_t im) +{ + if (im >= 0) { + push_str_modifier(hppa_ext, "mb"); + } else { + push_str_modifier(hppa_ext, "ma"); + } +} + +static bool decode_ldst_w(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t ext = get_insn_bit(insn, 29); + uint32_t im = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + im &= ~3; + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t s = get_insn_field(insn, 16, 17); + if (opcode == 0x17) { + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + if (ext == 1) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + } else { + if (ext == 1) { + CREATE_GR_REG(MI, r); + } else { + CREATE_FPR_REG(MI, r); + } + MCOperand_CreateImm0(MI, im); + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + } + if (ext == 1) { + fill_ldst_w_mods(insn, HPPA_EXT_REF(MI), im); + } + return true; +} + +static void fill_arith_imm_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (opcode) { + case 0x2d: + case 0x2c: + MCInst_setOpcode(MI, HPPA_INS_ADDI); + return; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_SUBI); + return; + default: + break; + } + } + if (get_insn_bit(insn, 20) == 0) { + switch (opcode) { + case 0x2d: + MCInst_setOpcode(MI, HPPA_INS_ADDI); + break; + case 0x2c: + MCInst_setOpcode(MI, HPPA_INS_ADDIT); + break; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_SUBI); + break; + default: + break; + } + } else { + switch (opcode) { + case 0x2d: + MCInst_setOpcode(MI, HPPA_INS_ADDIO); + break; + case 0x2c: + MCInst_setOpcode(MI, HPPA_INS_ADDITO); + break; + case 0x25: + MCInst_setOpcode(MI, HPPA_INS_SUBIO); + break; + default: + break; + } + } +} + +static void fill_arith_imm_insn_mods(uint32_t insn, hppa_ext *hppa_ext, + cs_mode mode) +{ + uint32_t opcode = insn >> 26; + uint32_t cond = (get_insn_bit(insn, 19) << 3) | + get_insn_field(insn, 16, 18); + uint32_t cmplt = get_insn_bit(insn, 20); + if (MODE_IS_HPPA_20(mode)) { + if (cmplt == 1) { + push_str_modifier(hppa_ext, "tsv"); + } + if (opcode == 0x2c) { + push_str_modifier(hppa_ext, "tc"); + } + } + switch (opcode) { + case 0x2d: + case 0x2c: + push_str_modifier(hppa_ext, add_cond_names[cond]); + break; + case 0x25: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + default: + break; + } +} + +static bool decode_arith_imm(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + MCOperand_CreateImm0(MI, extract_11(insn)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + fill_arith_imm_insn_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_shexdep0_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t d = get_insn_bit(insn, 22); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x01: + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_SHRPD); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_SHRPW); + return; + case 0x06: + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_EXTRW); + return; + case 0x00: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_SHRPW); + } else { + MCInst_setOpcode(MI, HPPA_INS_SHRPD); + } + return; + case 0x04: + case 0x05: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_EXTRW); + } else { + MCInst_setOpcode(MI, HPPA_INS_EXTRD); + } + return; + default: + break; + } + } + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_VSHD); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_SHD); + break; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_VEXTRU); + break; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_VEXTRS); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_EXTRU); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_EXTRS); + break; + default: + break; + } +} + +static void fill_shexdep0_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = get_insn_field(insn, 16, 18); + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t d = get_insn_bit(insn, 22); + + if (ext >= 0x04 && MODE_IS_HPPA_20(mode)) { + push_str_modifier(hppa_ext, signed_unsigned_names[ext & 1]); + } + + if (MODE_IS_HPPA_20(mode)) { + switch (ext) { + case 0x00: + case 0x04: + case 0x05: + if (d == 0) { + break; + } + // fallthrough + case 0x01: + case 0x03: + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); + return; + default: + break; + } + } + push_str_modifier(hppa_ext, shift_cond_names[cond]); +} + +static bool decode_shexdep0(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t cp = get_insn_bit(insn, 20); + uint32_t cpos = get_insn_field(insn, 22, 26); + uint32_t sa = 63 - ((cp << 5) | cpos); + uint32_t r1 = get_insn_field(insn, 11, 15); + uint32_t r2 = get_insn_field(insn, 6, 10); + uint32_t clen_t = get_insn_field(insn, 27, 31); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x01: + case 0x00: + case 0x03: + case 0x02: + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, r2); + if (ext <= 0x01) { + CREATE_CR_REG(MI, 11); + HPPA_EXT_REF(MI)->is_alternative = true; + } else { + MCOperand_CreateImm0(MI, sa); + } + CREATE_GR_REG(MI, clen_t); + break; + case 0x06: + case 0x07: + case 0x04: + case 0x05: + CREATE_GR_REG(MI, r2); + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, cpos); + } else { + CREATE_CR_REG(MI, 11); + HPPA_EXT_REF(MI)->is_alternative = true; + } + MCOperand_CreateImm0(MI, 32 - clen_t); + CREATE_GR_REG(MI, r1); + break; + default: + return false; + } + } else { + switch (ext) { + case 0x00: + case 0x02: + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, r2); + if (ext == 0x02) { + MCOperand_CreateImm0(MI, 31 - cpos); + } + CREATE_GR_REG(MI, clen_t); + break; + case 0x04: + case 0x05: + case 0x06: + case 0x07: + CREATE_GR_REG(MI, r2); + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, cpos); + } + MCOperand_CreateImm0(MI, 32 - clen_t); + CREATE_GR_REG(MI, r1); + break; + default: + return false; + } + } + fill_shexdep0_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_shexdep1_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t d = get_insn_bit(insn, 22); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (ext) { + case 0x02: + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_DEPW); + break; + case 0x06: + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_DEPWI); + break; + case 0x00: + case 0x01: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_DEPW); + } else { + MCInst_setOpcode(MI, HPPA_INS_DEPD); + } + break; + case 0x04: + case 0x05: + if (d == 0) { + MCInst_setOpcode(MI, HPPA_INS_DEPWI); + } else { + MCInst_setOpcode(MI, HPPA_INS_DEPDI); + } + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_ZVDEP); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_VDEP); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_ZDEP); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_DEP); + break; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_ZVDEPI); + break; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_VDEPI); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_ZDEPI); + break; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_DEPI); + break; + default: + break; + } + } +} + +static void fill_shexdep1_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = get_insn_field(insn, 16, 18); + uint32_t cmplt = get_insn_bit(insn, 21); + uint32_t ext = get_insn_field(insn, 19, 21); + if (MODE_IS_HPPA_20(mode)) { + if (cmplt == 0) { + push_str_modifier(hppa_ext, "z"); + } + switch (ext) { + case 0x00: + case 0x01: + case 0x04: + case 0x05: + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); + return; + default: + break; + } + } + push_str_modifier(hppa_ext, shift_cond_names[cond]); +} + +static bool decode_shexdep1(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 19, 21); + uint32_t cl = get_insn_bit(insn, 23); + uint32_t clen = get_insn_field(insn, 27, 31); + uint32_t len = (cl + 1) * 32 - clen; + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t t = get_insn_field(insn, 6, 10); + uint32_t cpos = get_insn_field(insn, 22, 26); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (ext) { + case 0x02: + case 0x03: + case 0x06: + case 0x07: + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + } else { + CREATE_GR_REG(MI, r); + } + MCOperand_CreateImm0(MI, 31 - cpos); + MCOperand_CreateImm0(MI, 32 - clen); + CREATE_GR_REG(MI, t); + break; + case 0x00: + case 0x01: + case 0x04: + case 0x05: + if (ext >= 0x04) { + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + } else { + CREATE_GR_REG(MI, r); + } + CREATE_CR_REG(MI, 11); + HPPA_EXT_REF(MI)->is_alternative = true; + MCOperand_CreateImm0(MI, len); + CREATE_GR_REG(MI, t); + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + CREATE_GR_REG(MI, r); + if (ext >= 0x02) { + MCOperand_CreateImm0(MI, 31 - cpos); + } + MCOperand_CreateImm0(MI, 32 - clen); + CREATE_GR_REG(MI, t); + break; + case 0x04: + case 0x05: + case 0x06: + case 0x07: + MCOperand_CreateImm0(MI, LowSignExtend64(r, 5)); + if (ext >= 0x06) { + MCOperand_CreateImm0(MI, 31 - cpos); + } + MCOperand_CreateImm0(MI, 32 - clen); + CREATE_GR_REG(MI, t); + break; + default: + break; + } + } + fill_shexdep1_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_shexdep2_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t cmplt = get_insn_bit(insn, 21); + uint32_t cond = get_insn_field(insn, 16, 18); + push_str_modifier(hppa_ext, signed_unsigned_names[cmplt]); + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); +} + +static bool decode_shexdep2(MCInst *MI, uint32_t insn) +{ + uint32_t pos = (get_insn_bit(insn, 20) << 5) | + get_insn_field(insn, 22, 26); + uint32_t cl = get_insn_bit(insn, 19); + uint32_t clen = get_insn_field(insn, 27, 31); + uint32_t len = (cl + 1) * 32 - clen; + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + MCOperand_CreateImm0(MI, pos); + MCOperand_CreateImm0(MI, len); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + fill_shexdep2_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_shexdep3_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t cmplt = get_insn_bit(insn, 21); + uint32_t cond = get_insn_field(insn, 16, 18); + if (cmplt == 0) { + push_str_modifier(hppa_ext, "z"); + } + push_str_modifier(hppa_ext, shift_cond_64_names[cond]); +} + +static bool decode_shexdep3(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + if (opcode == HPPA_OP_TYPE_SHEXDEP3) { + MCInst_setOpcode(MI, HPPA_INS_DEPD); + } else { + MCInst_setOpcode(MI, HPPA_INS_DEPDI); + } + uint32_t pos = 63 - ((get_insn_bit(insn, 20) << 5) | + get_insn_field(insn, 22, 26)); + uint32_t cl = get_insn_bit(insn, 19); + uint32_t clen = get_insn_field(insn, 27, 31); + uint32_t len = (cl + 1) * 32 - clen; + if (opcode == HPPA_OP_TYPE_SHEXDEP3) { + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + } else { + MCOperand_CreateImm0( + MI, LowSignExtend64(get_insn_field(insn, 11, 15), 5)); + } + MCOperand_CreateImm0(MI, pos); + MCOperand_CreateImm0(MI, len); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + fill_shexdep3_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_multmed_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t bit_16 = get_insn_bit(insn, 16); + uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | + get_insn_field(insn, 20, 21); + if (bit_16 == 0) { + MCInst_setOpcode(MI, HPPA_INS_PERMH); + return; + } + switch (ext) { + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_HSHL); + break; + case 0x0a: + case 0x0b: + MCInst_setOpcode(MI, HPPA_INS_HSHR); + break; + case 0x00: + case 0x08: + MCInst_setOpcode(MI, HPPA_INS_MIXW); + break; + case 0x01: + case 0x09: + MCInst_setOpcode(MI, HPPA_INS_MIXH); + break; + default: + break; + } +} + +static void fill_multmed_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t bit_16 = get_insn_bit(insn, 16); + uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | + get_insn_field(insn, 20, 21); + uint32_t eb = get_insn_field(insn, 20, 21); + uint32_t ea = get_insn_field(insn, 17, 18); + if (bit_16 == 0) { + char c[5]; + snprintf(c, sizeof(c), "%d%d%d%d", get_insn_field(insn, 17, 18), + get_insn_field(insn, 20, 21), + get_insn_field(insn, 22, 23), + get_insn_field(insn, 24, 25)); + push_str_modifier(hppa_ext, c); + return; + } + switch (ext) { + case 0x0a: + case 0x0b: + if (eb >= 2) { + push_str_modifier(hppa_ext, + signed_unsigned_names[eb - 2]); + } + break; + case 0x00: + case 0x08: + case 0x01: + case 0x09: + if (ea == 2) { + push_str_modifier(hppa_ext, "l"); + } else if (ea == 0) { + push_str_modifier(hppa_ext, "r"); + } + break; + default: + break; + } +} + +static bool decode_multmed(MCInst *MI, uint32_t insn) +{ + uint32_t bit_16 = get_insn_bit(insn, 16); + uint32_t ext = (get_insn_field(insn, 17, 18) << 2) | + get_insn_field(insn, 20, 21); + uint32_t r1 = get_insn_field(insn, 11, 15); + uint32_t r2 = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t sa = get_insn_field(insn, 22, 25); + if (bit_16 == 0) { + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + goto success; + } + switch (ext) { + case 0x02: + case 0x0a: + case 0x0b: + if (ext >= 0x0a) { + CREATE_GR_REG(MI, r2); + } else { + CREATE_GR_REG(MI, r1); + } + MCOperand_CreateImm0(MI, sa); + CREATE_GR_REG(MI, t); + break; + case 0x00: + case 0x08: + case 0x01: + case 0x09: + CREATE_GR_REG(MI, r1); + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } +success: + fill_multmed_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_branch_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 16, 18); + uint32_t bit_19 = get_insn_bit(insn, 19); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (insn == 0xe8004005) { + MCInst_setOpcode(MI, HPPA_INS_CLRBTS); + return; + } else if (insn == 0xe8004001) { + MCInst_setOpcode(MI, HPPA_INS_PUSHNOM); + return; + } + + switch (ext) { + case 0x00: + case 0x01: + case 0x04: + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_B); + return; + case 0x06: + if (bit_19 == 0) { + MCInst_setOpcode(MI, HPPA_INS_BV); + } else { + MCInst_setOpcode(MI, HPPA_INS_BVE); + } + return; + case 0x07: + if (bit_19 == 1) { + MCInst_setOpcode(MI, HPPA_INS_BVE); + } + return; + case 0x02: + if (get_insn_field(insn, 19, 29) == 0 && + get_insn_bit(insn, 31) == 0) { + MCInst_setOpcode(MI, HPPA_INS_BLR); + return; + } + if (get_insn_field(insn, 19, 31) == 1) { + MCInst_setOpcode(MI, HPPA_INS_PUSHBTS); + return; + } + if (bit_19 == 0 && + get_insn_field(insn, 29, 31) == 0x5) { + MCInst_setOpcode(MI, HPPA_INS_POPBTS); + return; + } + return; + default: + return; + } + } + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_BL); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_GATE); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_BLR); + break; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_BV); + break; + default: + break; + } +} + +static void fill_branch_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t ext = get_insn_field(insn, 16, 18); + uint32_t n = get_insn_bit(insn, 30); + uint32_t p = get_insn_bit(insn, 31); + if (MODE_IS_HPPA_20(mode)) { + switch (ext) { + case 0x00: + case 0x05: + push_str_modifier(hppa_ext, "l"); + // fallthrough + case 0x02: + break; + case 0x01: + push_str_modifier(hppa_ext, "gate"); + break; + case 0x04: + push_str_modifier(hppa_ext, "l"); + push_str_modifier(hppa_ext, "push"); + break; + case 0x06: + case 0x07: + if (get_insn_bit(insn, 19) == 0) { + break; + } + if (ext == 7) { + push_str_modifier(hppa_ext, "l"); + hppa_ext->is_alternative = true; + if (p == 1) { + push_str_modifier(hppa_ext, "push"); + } + } else { + if (p == 1) { + push_str_modifier(hppa_ext, "pop"); + } + } + break; + default: + return; + } + } + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } +} + +static bool decode_branch(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 16, 18); + uint32_t t = get_insn_field(insn, 6, 10); + uint32_t i = get_insn_field(insn, 20, 28); + uint32_t r = get_insn_field(insn, 11, 15); + uint32_t bit_19 = get_insn_bit(insn, 19); + if (MODE_IS_HPPA_20(ud->mode)) { + if (insn == 0xe8004005 || insn == 0xe8004001) { + return true; + } + + switch (ext) { + case 0x01: + case 0x00: + MCOperand_CreateImm0(MI, extract_17(insn)); + CREATE_GR_REG(MI, t); + break; + case 0x04: + case 0x05: + MCOperand_CreateImm0(MI, extract_22(insn)); + CREATE_GR_REG(MI, t); + break; + case 0x02: + if (bit_19 == 1) { + return false; + } + if (get_insn_field(insn, 20, 31) == 1 && t == 0) { + CREATE_GR_REG(MI, r); + break; + } + if (r == 0 && t == 0 && + get_insn_field(insn, 29, 31) == 0x5) { + MCOperand_CreateImm0(MI, i); + break; + } + if (get_insn_bit(insn, 31) == 0 && + get_insn_field(insn, 19, 29) == 0) { + CREATE_GR_REG(MI, r); + CREATE_GR_REG(MI, t); + break; + } + return false; + case 0x06: + if (bit_19 == 0) { + CREATE_GR_REG(MI, r); + } + CREATE_GR_REG(MI, t); + break; + case 0x07: + if (bit_19 == 1) { + CREATE_GR_REG(MI, t); + CREATE_GR_REG(MI, 2); + break; + } + // fallthrough + default: + return false; + } + fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; + } else { + switch (ext) { + case 0x00: + case 0x01: + MCOperand_CreateImm0(MI, extract_17(insn)); + CREATE_GR_REG(MI, t); + break; + case 0x02: + case 0x06: + CREATE_GR_REG(MI, r); + CREATE_GR_REG(MI, t); + break; + default: + return false; + } + fill_branch_mods(insn, HPPA_EXT_REF(MI), ud->mode); + return true; + } +} + +static void fill_corpdw_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = (get_insn_field(insn, 19, 19) << 1) | + get_insn_field(insn, 22, 22); + uint32_t opcode = insn >> 26; + uint32_t uid = get_insn_field(insn, 23, 25); + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (opcode == 0x09) { + switch (ext) { + case 0x00: + case 0x02: + if (uid <= 0x01) { + MCInst_setOpcode(MI, HPPA_INS_FLDW); + } else { + MCInst_setOpcode(MI, HPPA_INS_CLDW); + } + return; + case 0x01: + case 0x03: + if (uid <= 0x01) { + MCInst_setOpcode(MI, HPPA_INS_FSTW); + } else { + MCInst_setOpcode(MI, HPPA_INS_CSTW); + } + return; + default: + break; + } + } else { + switch (ext) { + case 0x00: + case 0x02: + if (uid == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FLDD); + } else { + MCInst_setOpcode(MI, HPPA_INS_CLDD); + } + return; + case 0x01: + case 0x03: + if (uid == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FSTD); + } else { + MCInst_setOpcode(MI, HPPA_INS_CSTD); + } + return; + default: + break; + } + } + } + if (opcode == 0x09) { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_CLDWX); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_CSTWX); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_CLDWS); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_CSTWS); + break; + default: + break; + } + } else { + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_CLDDX); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_CSTDX); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_CLDDS); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_CSTDS); + break; + default: + break; + } + } +} + +static inline bool coprdw_has_uid_mod(uint32_t opcode, uint32_t uid) +{ + return !((opcode == HPPA_OP_TYPE_COPRW && uid <= 0x01) || + (opcode == HPPA_OP_TYPE_COPRDW && uid == 0x00)); +} + +static void fill_corpdw_mods(uint32_t insn, uint32_t im, hppa_ext *hppa_ext, + cs_mode mode) +{ + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t cmplt = (get_insn_bit(insn, 18) << 1) | get_insn_bit(insn, 26); + uint32_t cc = get_insn_field(insn, 20, 21); + uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22); + uint32_t opcode = insn >> 26; + + if (coprdw_has_uid_mod(opcode, uid)) { + push_int_modifier(hppa_ext, uid); + } + if (CMPLT_HAS_MODIFY_BIT(cmplt)) { + hppa_ext->b_writeble = true; + } + + switch (ext) { + case 0x00: + case 0x01: + push_str_modifier(hppa_ext, index_compl_names[cmplt]); + break; + case 0x02: + case 0x03: + if (MODE_IS_HPPA_20(mode)) { + if (cmplt == 1 && im == 0) { + push_str_modifier(hppa_ext, "o"); + break; + } + } + push_str_modifier(hppa_ext, short_ldst_compl_names[cmplt]); + break; + default: + break; + } + if ((ext & 1) == 1 && cc == 1) { + push_str_modifier(hppa_ext, "bc"); + } + if (cc == 2) { + push_str_modifier(hppa_ext, "sl"); + } +} + +static bool decode_corpdw(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = (get_insn_bit(insn, 19) << 1) | get_insn_bit(insn, 22); + uint32_t x = get_insn_field(insn, 11, 15); + uint32_t b = get_insn_field(insn, 6, 10); + uint32_t s = get_insn_field(insn, 16, 17); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t opcode = MCInst_getOpcode(MI); + switch (ext) { + case 0x00: + case 0x02: + if (ext == 0x02) { + x = LowSignExtend64(x, 5); + MCOperand_CreateImm0(MI, x); + } else { + CREATE_GR_REG(MI, x); + } + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + if (opcode == HPPA_INS_FLDW || opcode == HPPA_INS_FLDD) { + CREATE_FPR_REG(MI, t); + } else { + CREATE_GR_REG(MI, t); + } + break; + case 0x01: + case 0x03: + if (opcode == HPPA_INS_FSTW || opcode == HPPA_INS_FSTD) { + CREATE_FPR_REG(MI, t); + } else { + CREATE_GR_REG(MI, t); + } + if (ext == 0x03) { + x = LowSignExtend64(x, 5); + MCOperand_CreateImm0(MI, x); + } else { + CREATE_GR_REG(MI, x); + } + CREATE_SR_REG(MI, s); + CREATE_GR_REG(MI, b); + break; + default: + break; + } + fill_corpdw_mods(insn, x, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_spop_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 21, 22); + switch (ext) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_SPOP0); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_SPOP1); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_SPOP2); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_SPOP3); + break; + default: + break; + } +} + +static void fill_spop_mods(uint32_t insn, uint32_t ext, hppa_ext *hppa_ext) +{ + uint32_t sfu = get_insn_field(insn, 23, 25); + uint32_t n = get_insn_field(insn, 26, 26); + uint32_t sop; + + push_int_modifier(hppa_ext, sfu); + switch (ext) { + case 0x00: + sop = (get_insn_field(insn, 6, 20) << 5) | + get_insn_field(insn, 27, 31); + break; + case 0x01: + sop = get_insn_field(insn, 6, 20); + break; + case 0x02: + sop = (get_insn_field(insn, 11, 20) << 5) | + get_insn_field(insn, 27, 31); + break; + case 0x03: + sop = (get_insn_field(insn, 16, 20) << 5) | + get_insn_field(insn, 27, 31); + break; + default: + break; + } + push_int_modifier(hppa_ext, sop); + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } +} + +static bool decode_spop(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t ext = get_insn_field(insn, 21, 22); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t t = get_insn_field(insn, 27, 31); + switch (ext) { + case 0x00: + break; + case 0x01: + CREATE_GR_REG(MI, t); + break; + case 0x02: + CREATE_GR_REG(MI, r1); + break; + case 0x03: + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, r1); + break; + default: + return false; + } + fill_spop_mods(insn, ext, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_copr_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t subop; + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FID); + return; + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_FNEG); + return; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_FNEGABS); + return; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop != 4) { + MCInst_setOpcode(MI, HPPA_INS_FCNV); + return; + } + } else if (class == 2) { + if (get_insn_bit(insn, 26) == 0) { + MCInst_setOpcode(MI, HPPA_INS_FCMP); + } else { + MCInst_setOpcode(MI, HPPA_INS_FTEST); + } + return; + } + } + } + + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_COPR); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCPY); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FABS); + return; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_FSQRT); + return; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_FRND); + return; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FCNVFF); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FCNVXF); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCNVFX); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FCNVFXT); + return; + default: + break; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FCMP); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FTEST); + return; + default: + break; + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FADD); + return; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FSUB); + return; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FMPY); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FDIV); + return; + default: + break; + } + } + } else if (uid == 2) { + subop = get_insn_field(insn, 18, 22); + switch (subop) { + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_PMDIS); + return; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_PMENB); + return; + default: + break; + } + } + MCInst_setOpcode(MI, HPPA_INS_COPR); +} + +static void fill_copr_mods(uint32_t insn, uint32_t uid, uint32_t class, + hppa_ext *hppa_ext, uint32_t subop, cs_mode mode) +{ + uint32_t n = get_insn_field(insn, 26, 26); + uint32_t sf = get_insn_field(insn, 19, 20); + uint32_t df = get_insn_field(insn, 17, 18); + if (MODE_IS_HPPA_20(mode)) { + if (uid == 0) { + if (class == 0) { + switch (subop) { + case 0x00: + return; + default: + break; + } + } else if (class == 1) { + switch (subop) { + case 0x00: + push_str_modifier( + hppa_ext, + float_format_names[sf]); + push_str_modifier( + hppa_ext, + float_format_names[df]); + return; + case 0x01: + push_str_modifier(hppa_ext, + fcnv_fixed_names[sf]); + push_str_modifier( + hppa_ext, + float_format_names[df]); + return; + case 0x03: + push_str_modifier(hppa_ext, "t"); + // fallthrough + case 0x02: + push_str_modifier( + hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + fcnv_fixed_names[df]); + return; + case 0x05: + push_str_modifier( + hppa_ext, + fcnv_ufixed_names[sf]); + push_str_modifier( + hppa_ext, + float_format_names[df]); + return; + case 0x07: + push_str_modifier(hppa_ext, "t"); + // fallthrough + case 0x06: + push_str_modifier( + hppa_ext, + float_format_names[sf]); + push_str_modifier( + hppa_ext, + fcnv_ufixed_names[df]); + return; + default: + break; + } + } + } + } + + if (uid == 0) { + if (class == 0) { + switch (subop) { + case 0x00: + push_int_modifier(hppa_ext, 0); + push_int_modifier(hppa_ext, 0); + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + break; + case 0x02: + case 0x03: + case 0x04: + case 0x05: + case 0x06: + case 0x07: + push_str_modifier(hppa_ext, + float_format_names[sf]); + break; + default: + break; + } + } else if (class == 1) { + push_str_modifier(hppa_ext, float_format_names[sf]); + push_str_modifier(hppa_ext, float_format_names[df]); + } else if (class == 2) { + uint32_t cond = get_insn_field(insn, 27, 31); + if (n == 1 && subop == 1) { + push_str_modifier(hppa_ext, + float_cond_names[cond]); + } + if (n == 0) { + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + float_comp_names[cond]); + } + } else if (class == 3) { + push_str_modifier(hppa_ext, float_format_names[sf]); + } + } else if (uid == 2) { + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + } else { + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t sop = (get_insn_field(insn, 6, 22) << 5) | + get_insn_field(insn, 27, 31); + push_int_modifier(hppa_ext, uid); + push_int_modifier(hppa_ext, sop); + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + } +} + +static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t uid = get_insn_field(insn, 23, 25); + uint32_t subop; + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t t = get_insn_field(insn, 27, 31); + if (MODE_IS_HPPA_20(ud->mode)) { + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + if (subop == 0x01) { + return false; + } + if (subop >= 0x02) { + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop == 0x04) { + return false; + } + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + } else if (class == 2) { + uint32_t n = get_insn_bit(insn, 26); + subop = get_insn_field(insn, 16, 18); + if (n == 0) { + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + if (subop != 0) { + MCOperand_CreateImm0(MI, + subop - 1); + HPPA_EXT_REF(MI) + ->is_alternative = true; + } + } else { + if (subop != 1) { + MCOperand_CreateImm0( + MI, (subop ^ 1) - 1); + HPPA_EXT_REF(MI) + ->is_alternative = true; + } + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + if (subop >= 4) { + return false; + } + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + CREATE_FPR_REG(MI, t); + } + fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), + subop, ud->mode); + return true; + } + } + if (uid == 0) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x02: + case 0x03: + case 0x04: + case 0x05: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + // fallthough + case 0x00: + break; + default: + return false; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + switch (subop) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, t); + break; + default: + return false; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + // fallthough + case 0x01: + break; + default: + return false; + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + case 0x01: + case 0x02: + case 0x03: + CREATE_FPR_REG(MI, r1); + CREATE_FPR_REG(MI, r2); + CREATE_FPR_REG(MI, t); + break; + default: + return false; + } + } + fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } else if (uid == 2) { + subop = get_insn_field(insn, 18, 22); + switch (subop) { + case 0x01: + case 0x03: + break; + default: + return false; + } + } + fill_copr_mods(insn, uid, class, HPPA_EXT_REF(MI), -1, ud->mode); + return true; +} + +static void fill_float_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t subop; + if (MODE_IS_HPPA_20(MI->csh->mode)) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x06: + MCInst_setOpcode(MI, HPPA_INS_FNEG); + return; + case 0x07: + MCInst_setOpcode(MI, HPPA_INS_FNEGABS); + return; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop == 0x04) { + return; + } + MCInst_setOpcode(MI, HPPA_INS_FCNV); + return; + } else if (class == 2) { + MCInst_setOpcode(MI, HPPA_INS_FCMP); + return; + } + } + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCPY); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FABS); + break; + case 0x04: + MCInst_setOpcode(MI, HPPA_INS_FSQRT); + break; + case 0x05: + MCInst_setOpcode(MI, HPPA_INS_FRND); + break; + default: + break; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FCNVFF); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FCNVXF); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FCNVFX); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FCNVFXT); + break; + default: + break; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + if (subop == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FCMP); + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + uint32_t fixed = get_insn_field(insn, 23, 23); + if (fixed == 0) { + switch (subop) { + case 0x00: + MCInst_setOpcode(MI, HPPA_INS_FADD); + break; + case 0x01: + MCInst_setOpcode(MI, HPPA_INS_FSUB); + break; + case 0x02: + MCInst_setOpcode(MI, HPPA_INS_FMPY); + break; + case 0x03: + MCInst_setOpcode(MI, HPPA_INS_FDIV); + break; + default: + break; + } + } else { + if (subop == 0x02) { + MCInst_setOpcode(MI, HPPA_INS_XMPYU); + } + } + } +} + +static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext, + uint32_t subop, cs_mode mode) +{ + uint32_t sf = get_insn_field(insn, 19, 20); + uint32_t df = get_insn_field(insn, 17, 18); + + if (MODE_IS_HPPA_20(mode)) { + if (class == 1) { + switch (subop) { + case 0x00: + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + float_format_names[df]); + return; + case 0x01: + push_str_modifier(hppa_ext, + fcnv_fixed_names[sf]); + push_str_modifier(hppa_ext, + float_format_names[df]); + return; + case 0x03: + push_str_modifier(hppa_ext, "t"); + // fallthough + case 0x02: + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + fcnv_fixed_names[df]); + return; + case 0x05: + push_str_modifier(hppa_ext, + fcnv_ufixed_names[sf]); + push_str_modifier(hppa_ext, + float_format_names[df]); + return; + case 0x07: + push_str_modifier(hppa_ext, "t"); + // fallthrough + case 0x06: + push_str_modifier(hppa_ext, + float_format_names[sf]); + push_str_modifier(hppa_ext, + fcnv_ufixed_names[df]); + return; + default: + return; + } + } + } + + if (class == 0) { + uint32_t fmt = get_insn_field(insn, 19, 20); + push_str_modifier(hppa_ext, float_format_names[fmt]); + } else if (class == 1) { + push_str_modifier(hppa_ext, float_format_names[sf]); + push_str_modifier(hppa_ext, float_format_names[df]); + } else if (class == 2) { + uint32_t fmt = get_insn_field(insn, 20, 20); + uint32_t cond = get_insn_field(insn, 27, 31); + push_str_modifier(hppa_ext, float_format_names[fmt]); + push_str_modifier(hppa_ext, float_cond_names[cond]); + } else if (class == 3) { + if (get_insn_field(insn, 23, 23) == 0) { + uint32_t fmt = get_insn_field(insn, 20, 20); + push_str_modifier(hppa_ext, float_format_names[fmt]); + } + } +} + +static bool decode_float(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t class = get_insn_field(insn, 21, 22); + uint32_t subop; + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r1_fpe = get_insn_bit(insn, 24); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t r2_fpe = get_insn_bit(insn, 19); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t t_fpe = get_insn_bit(insn, 25); + if (MODE_IS_HPPA_20(ud->mode)) { + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + if (subop >= 0x02) { + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), + subop, ud->mode); + return true; + } + } else if (class == 1) { + subop = get_insn_field(insn, 14, 16); + if (subop == 0x04) { + return false; + } + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + if (subop != 0) { + MCOperand_CreateImm0(MI, subop - 1); + } + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } + } + if (class == 0) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x02: + case 0x03: + case 0x04: + case 0x05: + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + default: + return false; + } + } else if (class == 1) { + subop = get_insn_field(insn, 15, 16); + if (subop <= 0x03) { + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } + } else if (class == 2) { + subop = get_insn_field(insn, 16, 18); + switch (subop) { + case 0x00: + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + default: + return false; + } + } else if (class == 3) { + subop = get_insn_field(insn, 16, 18); + uint32_t fixed = get_insn_field(insn, 23, 23); + if ((fixed == 0 && subop <= 0x03) || + (fixed == 1 && subop == 0x02)) { + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_float_mods(insn, class, HPPA_EXT_REF(MI), subop, + ud->mode); + return true; + } + return false; + } + return false; +} + +static void fill_fpfused_insn_name(MCInst *MI, uint32_t insn) +{ + uint32_t subop = get_insn_bit(insn, 26); + if (subop == 0x00) { + MCInst_setOpcode(MI, HPPA_INS_FMPYFADD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FMPYNFADD); + } +} + +static void fill_fpfused_mods(uint32_t insn, hppa_ext *hppa_ext) +{ + uint32_t fmt = get_insn_bit(insn, 20); + push_str_modifier(hppa_ext, float_format_names[fmt]); +} + +static bool decode_fpfused(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r1_fpe = get_insn_bit(insn, 24); + uint32_t r2 = get_insn_field(insn, 11, 15); + uint32_t r2_fpe = get_insn_bit(insn, 19); + uint32_t ra = (get_insn_field(insn, 16, 18) << 2) | + get_insn_field(insn, 21, 22); + uint32_t ra_fpe = get_insn_bit(insn, 23); + uint32_t t = get_insn_field(insn, 27, 31); + uint32_t t_fpe = get_insn_bit(insn, 25); + create_float_reg_spec(MI, r1, r1_fpe); + create_float_reg_spec(MI, r2, r2_fpe); + create_float_reg_spec(MI, ra, ra_fpe); + create_float_reg_spec(MI, t, t_fpe); + fill_fpfused_mods(insn, HPPA_EXT_REF(MI)); + return true; +} + +static void fill_action_and_branch_insn_name(MCInst *MI, uint32_t opcode) +{ + if (MODE_IS_HPPA_20(MI->csh->mode)) { + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPBDWT: + case HPPA_OP_TYPE_CMPBDWF: + MCInst_setOpcode(MI, HPPA_INS_CMPB); + return; + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + case HPPA_OP_TYPE_CMPIBDW: + MCInst_setOpcode(MI, HPPA_INS_CMPIB); + return; + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + MCInst_setOpcode(MI, HPPA_INS_ADDB); + return; + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + MCInst_setOpcode(MI, HPPA_INS_ADDIB); + return; + case HPPA_OP_TYPE_BBS: + MCInst_setOpcode(MI, HPPA_INS_BB); + return; + default: + break; + } + } + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + MCInst_setOpcode(MI, HPPA_INS_COMBT); + break; + case HPPA_OP_TYPE_CMPBF: + MCInst_setOpcode(MI, HPPA_INS_COMBF); + break; + case HPPA_OP_TYPE_CMPIBT: + MCInst_setOpcode(MI, HPPA_INS_COMIBT); + break; + case HPPA_OP_TYPE_CMPIBF: + MCInst_setOpcode(MI, HPPA_INS_COMIBF); + break; + case HPPA_OP_TYPE_ADDBT: + MCInst_setOpcode(MI, HPPA_INS_ADDBT); + break; + case HPPA_OP_TYPE_ADDBF: + MCInst_setOpcode(MI, HPPA_INS_ADDBF); + break; + case HPPA_OP_TYPE_ADDIBT: + MCInst_setOpcode(MI, HPPA_INS_ADDIBT); + break; + case HPPA_OP_TYPE_ADDIBF: + MCInst_setOpcode(MI, HPPA_INS_ADDIBF); + break; + case HPPA_OP_TYPE_MOVB: + MCInst_setOpcode(MI, HPPA_INS_MOVB); + break; + case HPPA_OP_TYPE_MOVIB: + MCInst_setOpcode(MI, HPPA_INS_MOVIB); + break; + case HPPA_OP_TYPE_BBS: + MCInst_setOpcode(MI, HPPA_INS_BVB); + break; + case HPPA_OP_TYPE_BB: + MCInst_setOpcode(MI, HPPA_INS_BB); + break; + default: + break; + } +} + +static void fill_action_and_branch_mods(uint32_t insn, uint32_t opcode, + hppa_ext *hppa_ext, cs_mode mode) +{ + uint32_t cond = get_insn_field(insn, 16, 18); + uint32_t n = get_insn_bit(insn, 30); + uint32_t d = get_insn_bit(insn, 18); + + if (MODE_IS_HPPA_20(mode)) { + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPIBT: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPIBF: + push_str_modifier(hppa_ext, + compare_cond_names[cond + 8]); + break; + case HPPA_OP_TYPE_CMPBDWT: + push_str_modifier(hppa_ext, + compare_cond_64_names[cond]); + break; + case HPPA_OP_TYPE_CMPBDWF: + push_str_modifier(hppa_ext, + compare_cond_64_names[cond + 8]); + break; + case HPPA_OP_TYPE_CMPIBDW: + push_str_modifier(hppa_ext, cmpib_cond_64_names[cond]); + break; + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDIBT: + if (MODE_IS_HPPA_20W(mode)) { + push_str_modifier(hppa_ext, + wide_add_cond_names[cond]); + } else { + push_str_modifier(hppa_ext, + add_cond_names[cond]); + } + break; + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_ADDIBF: + if (MODE_IS_HPPA_20W(mode)) { + push_str_modifier( + hppa_ext, + wide_add_cond_names[cond + 8]); + } else { + push_str_modifier(hppa_ext, + add_cond_names[cond + 8]); + } + break; + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + if (d == 0) { + push_str_modifier(hppa_ext, + shift_cond_names[cond]); + } else { + push_str_modifier(hppa_ext, + shift_cond_64_names[cond]); + } + break; + case HPPA_OP_TYPE_MOVB: + case HPPA_OP_TYPE_MOVIB: + push_str_modifier(hppa_ext, shift_cond_names[cond]); + break; + default: + break; + } + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } + return; + } + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + push_str_modifier(hppa_ext, compare_cond_names[cond]); + break; + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + push_str_modifier(hppa_ext, add_cond_names[cond]); + break; + case HPPA_OP_TYPE_MOVB: + case HPPA_OP_TYPE_MOVIB: + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + push_str_modifier(hppa_ext, shift_cond_names[cond]); + break; + default: + break; + } + if (n == 1) { + push_str_modifier(hppa_ext, "n"); + } +} + +static bool fill_action_and_branch(const cs_struct *ud, MCInst *MI, + uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t r1 = get_insn_field(insn, 6, 10); + uint32_t r2 = get_insn_field(insn, 11, 15); + if (MODE_IS_HPPA_20(ud->mode)) { + switch (opcode) { + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_CMPBDWT: + case HPPA_OP_TYPE_CMPBDWF: + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_MOVB: + CREATE_GR_REG(MI, r2); + CREATE_GR_REG(MI, r1); + MCOperand_CreateImm0(MI, extract_12(insn)); + break; + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + case HPPA_OP_TYPE_CMPIBDW: + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + case HPPA_OP_TYPE_MOVIB: + MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5)); + CREATE_GR_REG(MI, r1); + MCOperand_CreateImm0(MI, extract_12(insn)); + break; + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + CREATE_GR_REG(MI, r2); + if ((opcode & 1) == 1) { + MCOperand_CreateImm0(MI, r1); + } else { + CREATE_CR_REG(MI, 11); + } + MCOperand_CreateImm0(MI, extract_12(insn)); + break; + default: + return false; + } + fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), + ud->mode); + return true; + } + if ((opcode & 1) == 0 || opcode == HPPA_OP_TYPE_BB) { + CREATE_GR_REG(MI, r2); + } else { + MCOperand_CreateImm0(MI, LowSignExtend64(r2, 5)); + } + if (opcode == HPPA_OP_TYPE_BB) { + MCOperand_CreateImm0(MI, r1); + } else if (opcode != HPPA_OP_TYPE_BBS) { + CREATE_GR_REG(MI, r1); + } + MCOperand_CreateImm0(MI, extract_12(insn)); + fill_action_and_branch_mods(insn, opcode, HPPA_EXT_REF(MI), ud->mode); + return true; +} + +static void fill_load_insn_name(MCInst *MI, uint32_t opcode) +{ + switch (opcode) { + case HPPA_OP_TYPE_LDB: + MCInst_setOpcode(MI, HPPA_INS_LDB); + break; + case HPPA_OP_TYPE_LDH: + MCInst_setOpcode(MI, HPPA_INS_LDH); + break; + case HPPA_OP_TYPE_LDW: + MCInst_setOpcode(MI, HPPA_INS_LDW); + break; + case HPPA_OP_TYPE_LDWM: + if (MODE_IS_HPPA_20(MI->csh->mode)) { + MCInst_setOpcode(MI, HPPA_INS_LDW); + } else { + MCInst_setOpcode(MI, HPPA_INS_LDWM); + } + break; + default: + break; + } +} + +static void fill_store_insn_name(MCInst *MI, uint32_t opcode) +{ + switch (opcode) { + case HPPA_OP_TYPE_STB: + MCInst_setOpcode(MI, HPPA_INS_STB); + break; + case HPPA_OP_TYPE_STH: + MCInst_setOpcode(MI, HPPA_INS_STH); + break; + case HPPA_OP_TYPE_STW: + MCInst_setOpcode(MI, HPPA_INS_STW); + break; + case HPPA_OP_TYPE_STWM: + if (MODE_IS_HPPA_20(MI->csh->mode)) { + MCInst_setOpcode(MI, HPPA_INS_STW); + } else { + MCInst_setOpcode(MI, HPPA_INS_STWM); + } + break; + default: + break; + } +} + +static bool decode_cmpclr(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t cond = (get_insn_bit(insn, 19) << 3) | + get_insn_field(insn, 16, 18); + uint32_t d = get_insn_bit(insn, 20); + if (MODE_IS_HPPA_20(ud->mode)) { + MCInst_setOpcode(MI, HPPA_INS_CMPICLR); + } else { + MCInst_setOpcode(MI, HPPA_INS_COMICLR); + } + + MCOperand_CreateImm0(MI, + LowSignExtend64(get_insn_field(insn, 21, 31), 11)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + + if (d == 0) { + push_str_modifier(HPPA_EXT_REF(MI), compare_cond_names[cond]); + } else { + push_str_modifier(HPPA_EXT_REF(MI), + compare_cond_64_names[cond]); + } + return true; +} + +static bool decode_be(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t n = get_insn_bit(insn, 30); + bool mode = MODE_IS_HPPA_20(ud->mode); + if (opcode == HPPA_OP_TYPE_BLE) { + if (!mode) { + MCInst_setOpcode(MI, HPPA_INS_BLE); + } else { + MCInst_setOpcode(MI, HPPA_INS_BE); + push_str_modifier(HPPA_EXT_REF(MI), "l"); + HPPA_EXT_REF(MI)->is_alternative = true; + } + } else { + MCInst_setOpcode(MI, HPPA_INS_BE); + } + + MCOperand_CreateImm0(MI, extract_17(insn)); + CREATE_SR_REG(MI, extract_3(insn)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + if (opcode == HPPA_OP_TYPE_BLE && mode) { + CREATE_SR_REG(MI, 0); + CREATE_GR_REG(MI, 31); + } + if (n == 1) { + push_str_modifier(HPPA_EXT_REF(MI), "n"); + } + return true; +} + +static bool decode_float_ldst(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t a = get_insn_bit(insn, 29); + uint32_t disp = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + disp &= ~3; + + if (opcode == HPPA_OP_TYPE_FLDW) { + MCInst_setOpcode(MI, HPPA_INS_FLDW); + MCOperand_CreateImm0(MI, disp); + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15)); + } else { + MCInst_setOpcode(MI, HPPA_INS_FSTW); + CREATE_FPR_REG(MI, get_insn_field(insn, 11, 15)); + MCOperand_CreateImm0(MI, disp); + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + } + + if (a == 0) { + push_str_modifier(HPPA_EXT_REF(MI), "ma"); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "mb"); + } + return true; +} + +static bool decode_fmpy(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + uint32_t rm1 = get_insn_field(insn, 6, 10); + uint32_t rm2 = get_insn_field(insn, 11, 15); + uint32_t ta = get_insn_field(insn, 16, 20); + uint32_t ra = get_insn_field(insn, 21, 25); + uint32_t tm = get_insn_field(insn, 27, 31); + uint32_t fmt = get_insn_field(insn, 26, 26); + + if (opcode == HPPA_OP_TYPE_FMPYADD) { + MCInst_setOpcode(MI, HPPA_INS_FMPYADD); + } else { + MCInst_setOpcode(MI, HPPA_INS_FMPYSUB); + } + + if (fmt == 0) { + push_str_modifier(HPPA_EXT_REF(MI), "dbl"); + CREATE_FPR_REG(MI, rm1); + CREATE_FPR_REG(MI, rm2); + CREATE_FPR_REG(MI, tm); + CREATE_FPR_REG(MI, ra); + CREATE_FPR_REG(MI, ta); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "sgl"); + CREATE_SP_FPR_REG(MI, rm1); + CREATE_SP_FPR_REG(MI, rm2); + CREATE_SP_FPR_REG(MI, tm); + CREATE_SP_FPR_REG(MI, ra); + CREATE_SP_FPR_REG(MI, ta); + } + + return true; +} + +static bool decode_load(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + if (MODE_IS_HPPA_20(ud->mode)) { + uint32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + if (opcode == HPPA_OP_TYPE_LDWM) { + if (d < 0) { + push_str_modifier(HPPA_EXT_REF(MI), "mb"); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "ma"); + } + } + MCOperand_CreateImm0(MI, d); + } else { + MCOperand_CreateImm0(MI, extract_14(insn)); + } + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + return true; +} + +static bool decode_store(const cs_struct *ud, MCInst *MI, uint32_t insn) +{ + uint32_t opcode = insn >> 26; + CREATE_GR_REG(MI, get_insn_field(insn, 11, 15)); + if (MODE_IS_HPPA_20(ud->mode)) { + uint32_t d = extract_16(insn, MODE_IS_HPPA_20W(ud->mode)); + if (opcode == HPPA_OP_TYPE_STWM) { + if (d < 0) { + push_str_modifier(HPPA_EXT_REF(MI), "mb"); + } else { + push_str_modifier(HPPA_EXT_REF(MI), "ma"); + } + } + MCOperand_CreateImm0(MI, d); + } else { + MCOperand_CreateImm0(MI, extract_14(insn)); + } + CREATE_SR_REG(MI, get_insn_field(insn, 16, 17)); + CREATE_GR_REG(MI, get_insn_field(insn, 6, 10)); + return true; +} + +static bool getInstruction(const cs_struct *ud, const uint8_t *code, + size_t code_len, MCInst *MI) +{ + if (code_len < 4) + return false; + + MCInst_clear(MI); + + uint32_t full_insn = readBytes32(MI, code); + uint8_t opcode = full_insn >> 26; + + if (MODE_IS_HPPA_20(ud->mode)) { + switch (opcode) { + case HPPA_OP_TYPE_LOADDW: + case HPPA_OP_TYPE_STOREDW: + fill_ldst_dw_insn_name(MI, full_insn); + return decode_ldst_dw(ud, MI, full_insn); + case HPPA_OP_TYPE_LOADW: + case HPPA_OP_TYPE_STOREW: + fill_ldst_w_insn_name(MI, full_insn); + return decode_ldst_w(ud, MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP2: + MCInst_setOpcode(MI, HPPA_INS_EXTRD); + return decode_shexdep2(MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP3: + case HPPA_OP_TYPE_SHEXDEP4: + return decode_shexdep3(ud, MI, full_insn); + case HPPA_OP_TYPE_MULTMED: + fill_multmed_insn_name(MI, full_insn); + return decode_multmed(MI, full_insn); + case HPPA_OP_TYPE_FPFUSED: + fill_fpfused_insn_name(MI, full_insn); + return decode_fpfused(ud, MI, full_insn); + case HPPA_OP_TYPE_FLDW: + case HPPA_OP_TYPE_FSTW: + return decode_float_ldst(ud, MI, full_insn); + case HPPA_OP_TYPE_CMPBDWT: + case HPPA_OP_TYPE_CMPBDWF: + case HPPA_OP_TYPE_CMPIBDW: + fill_action_and_branch_insn_name(MI, opcode); + return fill_action_and_branch(ud, MI, full_insn); + default: + break; + } + } + + switch (opcode) { + case HPPA_OP_TYPE_SYSOP: + fill_sysop_insn_name(MI, full_insn); + return decode_sysop(ud, MI, full_insn); + case HPPA_OP_TYPE_MEMMGMT: + fill_memmgmt_insn_name(MI, full_insn); + return decode_memmgmt(ud, MI, full_insn); + case HPPA_OP_TYPE_ALU: + fill_alu_insn_name(MI, full_insn); + return decode_alu(ud, MI, full_insn); + case HPPA_OP_TYPE_IDXMEM: + fill_idxmem_insn_name(MI, full_insn); + return decode_idxmem(ud, MI, full_insn); + case HPPA_OP_TYPE_ADDIT: + case HPPA_OP_TYPE_ADDI: + case HPPA_OP_TYPE_SUBI: + fill_arith_imm_insn_name(MI, full_insn); + return decode_arith_imm(ud, MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP0: + fill_shexdep0_insn_name(MI, full_insn); + return decode_shexdep0(ud, MI, full_insn); + case HPPA_OP_TYPE_SHEXDEP1: + fill_shexdep1_insn_name(MI, full_insn); + return decode_shexdep1(ud, MI, full_insn); + case HPPA_OP_TYPE_BRANCH: + fill_branch_insn_name(MI, full_insn); + return decode_branch(ud, MI, full_insn); + case HPPA_OP_TYPE_COPRW: + case HPPA_OP_TYPE_COPRDW: + fill_corpdw_insn_name(MI, full_insn); + return decode_corpdw(ud, MI, full_insn); + case HPPA_OP_TYPE_SPOP: + fill_spop_insn_name(MI, full_insn); + return decode_spop(ud, MI, full_insn); + case HPPA_OP_TYPE_COPR: + fill_copr_insn_name(MI, full_insn); + return decode_copr(ud, MI, full_insn); + case HPPA_OP_TYPE_FLOAT: + fill_float_insn_name(MI, full_insn); + return decode_float(ud, MI, full_insn); + case HPPA_OP_TYPE_DIAG: + MCInst_setOpcode(MI, HPPA_INS_DIAG); + MCOperand_CreateImm0(MI, get_insn_field(full_insn, 6, 31)); + return true; + case HPPA_OP_TYPE_FMPYADD: + case HPPA_OP_TYPE_FMPYSUB: + return decode_fmpy(ud, MI, full_insn); + case HPPA_OP_TYPE_LDIL: + case HPPA_OP_TYPE_ADDIL: + if (opcode == HPPA_OP_TYPE_LDIL) { + MCInst_setOpcode(MI, HPPA_INS_LDIL); + } else { + MCInst_setOpcode(MI, HPPA_INS_ADDIL); + } + MCOperand_CreateImm0(MI, extract_21(full_insn)); + CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10)); + return true; + case HPPA_OP_TYPE_LDO: + MCInst_setOpcode(MI, HPPA_INS_LDO); + if (MODE_IS_HPPA_20(ud->mode)) { + MCOperand_CreateImm0( + MI, extract_16(full_insn, + MODE_IS_HPPA_20W(ud->mode))); + } else { + MCOperand_CreateImm0(MI, extract_14(full_insn)); + } + CREATE_GR_REG(MI, get_insn_field(full_insn, 6, 10)); + CREATE_GR_REG(MI, get_insn_field(full_insn, 11, 15)); + return true; + case HPPA_OP_TYPE_LDB: + case HPPA_OP_TYPE_LDH: + case HPPA_OP_TYPE_LDW: + case HPPA_OP_TYPE_LDWM: + fill_load_insn_name(MI, opcode); + return decode_load(ud, MI, full_insn); + case HPPA_OP_TYPE_STB: + case HPPA_OP_TYPE_STH: + case HPPA_OP_TYPE_STW: + case HPPA_OP_TYPE_STWM: + fill_store_insn_name(MI, opcode); + return decode_store(ud, MI, full_insn); + case HPPA_OP_TYPE_CMPBT: + case HPPA_OP_TYPE_CMPBF: + case HPPA_OP_TYPE_ADDBT: + case HPPA_OP_TYPE_ADDBF: + case HPPA_OP_TYPE_MOVB: + case HPPA_OP_TYPE_CMPIBT: + case HPPA_OP_TYPE_CMPIBF: + case HPPA_OP_TYPE_ADDIBT: + case HPPA_OP_TYPE_ADDIBF: + case HPPA_OP_TYPE_MOVIB: + case HPPA_OP_TYPE_BBS: + case HPPA_OP_TYPE_BB: + fill_action_and_branch_insn_name(MI, opcode); + return fill_action_and_branch(ud, MI, full_insn); + case HPPA_OP_TYPE_CMPICLR: + return decode_cmpclr(ud, MI, full_insn); + case HPPA_OP_TYPE_BE: + case HPPA_OP_TYPE_BLE: + return decode_be(ud, MI, full_insn); + default: + return false; + } +} + +void init_details(MCInst *MI) +{ + cs_detail *detail = get_detail(MI); + if (detail) { + memset(detail, 0, offsetof(cs_detail, hppa) + sizeof(cs_hppa)); + } +} + +bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info) +{ + cs_struct *cs = (cs_struct *)ud; + init_details(instr); + if (!getInstruction(cs, code, code_len, instr)) { + *size = 0; + return false; + } + *size = 4; + return true; +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPADisassembler.h b/arch/HPPA/HPPADisassembler.h new file mode 100644 index 0000000000..f4d12e2137 --- /dev/null +++ b/arch/HPPA/HPPADisassembler.h @@ -0,0 +1,13 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPA_DISASSEMBLER_H +#define CS_HPPA_DISASSEMBLER_H + +#include "../../MCInst.h" + +bool HPPA_getInstruction(csh ud, const uint8_t *code, size_t code_len, + MCInst *instr, uint16_t *size, uint64_t address, + void *info); + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAInstPrinter.c b/arch/HPPA/HPPAInstPrinter.c new file mode 100644 index 0000000000..56a2ff6385 --- /dev/null +++ b/arch/HPPA/HPPAInstPrinter.c @@ -0,0 +1,837 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include +#include "../../Mapping.h" +#include "../../utils.h" + +#include "HPPAInstPrinter.h" +#include "HPPAMapping.h" + +static const struct pa_insn pa_insns[] = { + { HPPA_INS_LDI, HPPA_GRP_LONG_IMM }, + { HPPA_INS_CMPIB, HPPA_GRP_BRANCH }, + { HPPA_INS_COMIB, HPPA_GRP_BRANCH }, + { HPPA_INS_CMPB, HPPA_GRP_BRANCH }, + { HPPA_INS_COMB, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDB, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDIB, HPPA_GRP_BRANCH }, + { HPPA_INS_NOP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_COPY, HPPA_GRP_COMPUTATION }, + { HPPA_INS_MTSAR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LDD, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDW, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDH, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDB, HPPA_GRP_MEM_REF }, + { HPPA_INS_STD, HPPA_GRP_MEM_REF }, + { HPPA_INS_STW, HPPA_GRP_MEM_REF }, + { HPPA_INS_STH, HPPA_GRP_MEM_REF }, + { HPPA_INS_STB, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWM, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWM, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDHX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDBX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWA, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCW, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWA, HPPA_GRP_MEM_REF }, + { HPPA_INS_STBY, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDDA, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCD, HPPA_GRP_MEM_REF }, + { HPPA_INS_STDA, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWAX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCWX, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDHS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDBS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDWAS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDCWS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STHS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STBS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STWAS, HPPA_GRP_MEM_REF }, + { HPPA_INS_STDBY, HPPA_GRP_MEM_REF }, + { HPPA_INS_STBYS, HPPA_GRP_MEM_REF }, + { HPPA_INS_LDO, HPPA_GRP_LONG_IMM }, + { HPPA_INS_LDIL, HPPA_GRP_LONG_IMM }, + { HPPA_INS_ADDIL, HPPA_GRP_LONG_IMM }, + { HPPA_INS_B, HPPA_GRP_BRANCH }, + { HPPA_INS_BL, HPPA_GRP_BRANCH }, + { HPPA_INS_GATE, HPPA_GRP_BRANCH }, + { HPPA_INS_BLR, HPPA_GRP_BRANCH }, + { HPPA_INS_BV, HPPA_GRP_BRANCH }, + { HPPA_INS_BVE, HPPA_GRP_BRANCH }, + { HPPA_INS_BE, HPPA_GRP_BRANCH }, + { HPPA_INS_BLE, HPPA_GRP_BRANCH }, + { HPPA_INS_MOVB, HPPA_GRP_BRANCH }, + { HPPA_INS_MOVIB, HPPA_GRP_BRANCH }, + { HPPA_INS_COMBT, HPPA_GRP_BRANCH }, + { HPPA_INS_COMBF, HPPA_GRP_BRANCH }, + { HPPA_INS_COMIBT, HPPA_GRP_BRANCH }, + { HPPA_INS_COMIBF, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDBT, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDBF, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDIBT, HPPA_GRP_BRANCH }, + { HPPA_INS_ADDIBF, HPPA_GRP_BRANCH }, + { HPPA_INS_BB, HPPA_GRP_BRANCH }, + { HPPA_INS_BVB, HPPA_GRP_BRANCH }, + { HPPA_INS_CLRBTS, HPPA_GRP_BRANCH }, + { HPPA_INS_POPBTS, HPPA_GRP_BRANCH }, + { HPPA_INS_PUSHNOM, HPPA_GRP_BRANCH }, + { HPPA_INS_PUSHBTS, HPPA_GRP_BRANCH }, + { HPPA_INS_CMPCLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_COMCLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_OR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_XOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_AND, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ANDCM, HPPA_GRP_COMPUTATION }, + { HPPA_INS_UXOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_UADDCM, HPPA_GRP_COMPUTATION }, + { HPPA_INS_UADDCMT, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DCOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_IDCOR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDIO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDIT, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDITO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDC, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ADDCO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUB, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBB, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBBO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBT, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBTO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DS, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SUBIO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_CMPICLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_COMICLR, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SHLADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH1ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH1ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH1ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH2ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH2ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH2ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH3ADD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH3ADDL, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SH3ADDO, HPPA_GRP_COMPUTATION }, + { HPPA_INS_HADD, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HAVG, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHL, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHLADD, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHR, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSHRADD, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_HSUB, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_MIXH, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_MIXW, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_PERMH, HPPA_GRP_MULTIMEDIA }, + { HPPA_INS_SHRPD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SHRPW, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VSHD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_SHD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRW, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VEXTRU, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VEXTRS, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRU, HPPA_GRP_COMPUTATION }, + { HPPA_INS_EXTRS, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPD, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPDI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPW, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPWI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZVDEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VDEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZDEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEP, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZVDEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_VDEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_ZDEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_DEPI, HPPA_GRP_COMPUTATION }, + { HPPA_INS_BREAK, HPPA_GRP_SYSCTRL }, + { HPPA_INS_RFI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_RFIR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SSM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_RSM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTSM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LDSID, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTSP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTCTL, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTSARCM, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFIA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFSP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFCTL, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SYNC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SYNCDMA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBEI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBER, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBERI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBEW, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PROBEWI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LPA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_LCI, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PDTLB, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PITLB, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PDTLBE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PITLBE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IDTLBA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IITLBA, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IDTLBP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IITLBP, HPPA_GRP_SYSCTRL }, + { HPPA_INS_PDC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FDC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FIC, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FDCE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FICE, HPPA_GRP_SYSCTRL }, + { HPPA_INS_DIAG, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IDTLBT, HPPA_GRP_SYSCTRL }, + { HPPA_INS_IITLBT, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MTCPU, HPPA_GRP_SYSCTRL }, + { HPPA_INS_MFCPU, HPPA_GRP_SYSCTRL }, + { HPPA_INS_TOCEN, HPPA_GRP_SYSCTRL }, + { HPPA_INS_TOCDIS, HPPA_GRP_SYSCTRL }, + { HPPA_INS_SHDWGR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_GRSHDW, HPPA_GRP_SYSCTRL }, + { HPPA_INS_GFW, HPPA_GRP_SYSCTRL }, + { HPPA_INS_GFR, HPPA_GRP_SYSCTRL }, + { HPPA_INS_FLDW, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDD, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTW, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTD, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDWX, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDDX, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTWX, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTDX, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTQX, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDWS, HPPA_GRP_FLOAT }, + { HPPA_INS_FLDDS, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTWS, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTDS, HPPA_GRP_FLOAT }, + { HPPA_INS_FSTQS, HPPA_GRP_FLOAT }, + { HPPA_INS_FADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FSUB, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPY, HPPA_GRP_FLOAT }, + { HPPA_INS_FDIV, HPPA_GRP_FLOAT }, + { HPPA_INS_FSQRT, HPPA_GRP_FLOAT }, + { HPPA_INS_FABS, HPPA_GRP_FLOAT }, + { HPPA_INS_FREM, HPPA_GRP_FLOAT }, + { HPPA_INS_FRND, HPPA_GRP_FLOAT }, + { HPPA_INS_FCPY, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVFF, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVXF, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVFX, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNVFXT, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYFADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYNFADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FNEG, HPPA_GRP_FLOAT }, + { HPPA_INS_FNEGABS, HPPA_GRP_FLOAT }, + { HPPA_INS_FCNV, HPPA_GRP_FLOAT }, + { HPPA_INS_FCMP, HPPA_GRP_FLOAT }, + { HPPA_INS_XMPYU, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYADD, HPPA_GRP_FLOAT }, + { HPPA_INS_FMPYSUB, HPPA_GRP_FLOAT }, + { HPPA_INS_FTEST, HPPA_GRP_FLOAT }, + { HPPA_INS_FID, HPPA_GRP_FLOAT }, + { HPPA_INS_PMDIS, HPPA_GRP_PERFMON }, + { HPPA_INS_PMENB, HPPA_GRP_PERFMON }, + { HPPA_INS_SPOP0, HPPA_GRP_ASSIST }, + { HPPA_INS_SPOP1, HPPA_GRP_ASSIST }, + { HPPA_INS_SPOP2, HPPA_GRP_ASSIST }, + { HPPA_INS_SPOP3, HPPA_GRP_ASSIST }, + { HPPA_INS_COPR, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDW, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDD, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTW, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTD, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDWX, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDDX, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTWX, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTDX, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDWS, HPPA_GRP_ASSIST }, + { HPPA_INS_CLDDS, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTWS, HPPA_GRP_ASSIST }, + { HPPA_INS_CSTDS, HPPA_GRP_ASSIST }, + { HPPA_INS_CALL, HPPA_GRP_INVALID }, + { HPPA_INS_RET, HPPA_GRP_INVALID }, +}; + +static void set_op_imm(cs_hppa *hppa, uint64_t val) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_IMM; + op->imm = val; +} + +static void set_op_reg(cs_hppa *hppa, uint64_t val, cs_ac_type access) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_REG; + op->reg = val; + op->access = access; +} + +static void set_op_idx_reg(cs_hppa *hppa, uint64_t reg) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_IDX_REG; + op->reg = reg; + op->access = CS_AC_READ; +} + +static void set_op_disp(cs_hppa *hppa, uint64_t val) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_DISP; + op->imm = val; +} + +static void set_op_target(cs_hppa *hppa, uint64_t val) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_TARGET; + op->imm = val; +} + +static void set_op_mem(cs_hppa *hppa, uint32_t base, uint32_t space, + cs_ac_type base_access) +{ + cs_hppa_op *op = &hppa->operands[hppa->op_count++]; + op->type = HPPA_OP_MEM; + op->mem.base = base; + op->mem.space = space; + op->mem.base_access = base_access; +} +/* HPPA instruction formats (access) + i - imm arguments + R - read access register + W - write access register + w - read + write access register + r - index register (read only) + T - offset (pc relative) + o - displacement (imm) + x - [r] or [o] defined by the operand kind + b - base register (may be writable in some cases) +*/ +static const struct pa_insn_fmt pa_formats[] = { + { HPPA_INS_LDI, "iW", false }, + + { HPPA_INS_CMPIB, "iRT", false }, + { HPPA_INS_COMIB, "iRT", false }, + + { HPPA_INS_CMPB, "RRT", false }, + { HPPA_INS_COMB, "RRT", false }, + + { HPPA_INS_ADDB, "RwT", false }, + + { HPPA_INS_ADDIB, "iwT", false }, + + { HPPA_INS_NOP, "", false }, + { HPPA_INS_COPY, "RW", false }, + { HPPA_INS_MTSAR, "R", false }, + + { HPPA_INS_LDD, "x(Rb)W", false }, + { HPPA_INS_LDW, "x(Rb)W", false }, + { HPPA_INS_LDH, "x(Rb)W", false }, + { HPPA_INS_LDB, "x(Rb)W", false }, + { HPPA_INS_STD, "Ro(Rb)", false }, + { HPPA_INS_STW, "Ro(Rb)", false }, + { HPPA_INS_STH, "Ro(Rb)", false }, + { HPPA_INS_STB, "Ro(Rb)", false }, + { HPPA_INS_LDWM, "o(Rw)W", false }, + { HPPA_INS_STWM, "Ro(Rw)", false }, + { HPPA_INS_LDWX, "r(Rb)W", false }, + { HPPA_INS_LDHX, "r(Rb)W", false }, + { HPPA_INS_LDBX, "r(Rb)W", false }, + { HPPA_INS_LDWA, "x(R)W", false }, + { HPPA_INS_LDCW, "x(Rb)W", false }, + { HPPA_INS_STWA, "Ro(b)", false }, + { HPPA_INS_STBY, "Ro(Rb)", false }, + { HPPA_INS_LDDA, "x(b)W", false }, + { HPPA_INS_LDCD, "x(Rb)W", false }, + { HPPA_INS_STDA, "Ro(b)", false }, + { HPPA_INS_LDWAX, "r(b)W", false }, + { HPPA_INS_LDCWX, "r(Rb)W", false }, + { HPPA_INS_LDWS, "o(Rb)W", false }, + { HPPA_INS_LDHS, "o(Rb)W", false }, + { HPPA_INS_LDBS, "o(Rb)W", false }, + { HPPA_INS_LDWAS, "o(b)W", false }, + { HPPA_INS_LDCWS, "o(Rb)W", false }, + { HPPA_INS_STWS, "Ro(Rb)", false }, + { HPPA_INS_STHS, "Ro(Rb)", false }, + { HPPA_INS_STBS, "Ro(Rb)", false }, + { HPPA_INS_STWAS, "Ro(b)", false }, + { HPPA_INS_STDBY, "Ro(Rb)", false }, + { HPPA_INS_STBYS, "Ro(Rb)", false }, + + { HPPA_INS_LDO, "o(R)W", false }, + { HPPA_INS_LDIL, "iW", false }, + { HPPA_INS_ADDIL, "iR", false }, + + { HPPA_INS_B, "TW", false }, + { HPPA_INS_BL, "TW", false }, + { HPPA_INS_GATE, "TW", false }, + { HPPA_INS_BLR, "RW", false }, + { HPPA_INS_BV, "x(R)", false }, + { HPPA_INS_BVE, "(b)", false }, + { HPPA_INS_BVE, "(b)W", true }, + { HPPA_INS_BE, "o(RR)", false }, + { HPPA_INS_BE, "o(RR)WW", true }, + { HPPA_INS_BLE, "o(RR)", false }, + { HPPA_INS_MOVB, "RWT", false }, + { HPPA_INS_MOVIB, "iWT", false }, + { HPPA_INS_COMBT, "RRT", false }, + { HPPA_INS_COMBF, "RRT", false }, + { HPPA_INS_COMIBT, "iRT", false }, + { HPPA_INS_COMIBF, "iRT", false }, + { HPPA_INS_ADDBT, "RwT", false }, + { HPPA_INS_ADDBF, "RwT", false }, + { HPPA_INS_ADDIBT, "iwT", false }, + { HPPA_INS_ADDIBF, "iwT", false }, + { HPPA_INS_BB, "RiT", false }, + { HPPA_INS_BVB, "RT", false }, + { HPPA_INS_CLRBTS, "", false }, + { HPPA_INS_POPBTS, "i", false }, + { HPPA_INS_PUSHNOM, "", false }, + { HPPA_INS_PUSHBTS, "R", false }, + + { HPPA_INS_CMPCLR, "RRW", false }, + { HPPA_INS_COMCLR, "RRW", false }, + { HPPA_INS_OR, "RRW", false }, + { HPPA_INS_XOR, "RRW", false }, + { HPPA_INS_AND, "RRW", false }, + { HPPA_INS_ANDCM, "RRW", false }, + { HPPA_INS_UXOR, "RRW", false }, + { HPPA_INS_UADDCM, "RRW", false }, + { HPPA_INS_UADDCMT, "RRW", false }, + { HPPA_INS_DCOR, "RW", false }, + { HPPA_INS_IDCOR, "RW", false }, + { HPPA_INS_ADDI, "iRW", false }, + { HPPA_INS_ADDIO, "iRW", false }, + { HPPA_INS_ADDIT, "iRW", false }, + { HPPA_INS_ADDITO, "iRW", false }, + { HPPA_INS_ADD, "RRW", false }, + { HPPA_INS_ADDL, "RRW", false }, + { HPPA_INS_ADDO, "RRW", false }, + { HPPA_INS_ADDC, "RRW", false }, + { HPPA_INS_ADDCO, "RRW", false }, + { HPPA_INS_SUB, "RRW", false }, + { HPPA_INS_SUBO, "RRW", false }, + { HPPA_INS_SUBB, "RRW", false }, + { HPPA_INS_SUBBO, "RRW", false }, + { HPPA_INS_SUBT, "RRW", false }, + { HPPA_INS_SUBTO, "RRW", false }, + { HPPA_INS_DS, "RRW", false }, + { HPPA_INS_SUBI, "iRW", false }, + { HPPA_INS_SUBIO, "iRW", false }, + { HPPA_INS_CMPICLR, "iRW", false }, + { HPPA_INS_COMICLR, "iRW", false }, + { HPPA_INS_SHLADD, "RiRW", false }, + { HPPA_INS_SH1ADD, "RRW", false }, + { HPPA_INS_SH1ADDL, "RRW", false }, + { HPPA_INS_SH1ADDO, "RRW", false }, + { HPPA_INS_SH2ADD, "RRW", false }, + { HPPA_INS_SH2ADDL, "RRW", false }, + { HPPA_INS_SH2ADDO, "RRW", false }, + { HPPA_INS_SH3ADD, "RRW", false }, + { HPPA_INS_SH3ADDL, "RRW", false }, + { HPPA_INS_SH3ADDO, "RRW", false }, + + { HPPA_INS_HADD, "RRW", false }, + { HPPA_INS_HAVG, "RRW", false }, + { HPPA_INS_HSHL, "RiW", false }, + { HPPA_INS_HSHLADD, "RiRW", false }, + { HPPA_INS_HSHR, "RiW", false }, + { HPPA_INS_HSHRADD, "RiRW", false }, + { HPPA_INS_HSUB, "RRW", false }, + { HPPA_INS_MIXH, "RRW", false }, + { HPPA_INS_MIXW, "RRW", false }, + { HPPA_INS_PERMH, "RW", false }, + + { HPPA_INS_SHRPD, "RRiW", false }, + { HPPA_INS_SHRPD, "RRRW", true }, + { HPPA_INS_SHRPW, "RRiW", false }, + { HPPA_INS_SHRPW, "RRRW", true }, + { HPPA_INS_VSHD, "RRW", false }, + { HPPA_INS_SHD, "RRiW", false }, + { HPPA_INS_EXTRD, "RiiW", false }, + { HPPA_INS_EXTRD, "RRiW", true }, + { HPPA_INS_EXTRW, "RiiW", false }, + { HPPA_INS_EXTRW, "RRiW", true }, + { HPPA_INS_VEXTRU, "RiW", false }, + { HPPA_INS_VEXTRS, "RiW", false }, + { HPPA_INS_EXTRU, "RiiW", false }, + { HPPA_INS_EXTRS, "RiiW", false }, + { HPPA_INS_DEPD, "RiiW", false }, + { HPPA_INS_DEPDI, "iiiW", false }, + { HPPA_INS_DEPW, "RiiW", false }, + { HPPA_INS_DEPW, "RRiW", true }, + { HPPA_INS_DEPWI, "iiiW", false }, + { HPPA_INS_DEPWI, "iRiW", true }, + { HPPA_INS_ZVDEP, "RiW", false }, + { HPPA_INS_VDEP, "RiW", false }, + { HPPA_INS_ZDEP, "RiiW", false }, + { HPPA_INS_DEP, "RiiW", false }, + { HPPA_INS_ZVDEPI, "iiW", false }, + { HPPA_INS_VDEPI, "iiW", false }, + { HPPA_INS_ZDEPI, "iiiW", false }, + { HPPA_INS_DEPI, "iiiW", false }, + + { HPPA_INS_BREAK, "ii", false }, + { HPPA_INS_RFI, "", false }, + { HPPA_INS_RFIR, "", false }, + { HPPA_INS_SSM, "iW", false }, + { HPPA_INS_RSM, "iW", false }, + { HPPA_INS_MTSM, "R", false }, + { HPPA_INS_LDSID, "(RR)W", false }, + { HPPA_INS_MTSP, "RW", false }, + { HPPA_INS_MTCTL, "RW", false }, + { HPPA_INS_MTSARCM, "R", false }, + { HPPA_INS_MFIA, "W", false }, + { HPPA_INS_MFSP, "RW", false }, + { HPPA_INS_MFCTL, "RW", false }, + { HPPA_INS_SYNC, "", false }, + { HPPA_INS_SYNCDMA, "", false }, + { HPPA_INS_PROBE, "(RR)RW", false }, + { HPPA_INS_PROBEI, "(RR)iW", false }, + { HPPA_INS_PROBER, "(RR)RW", false }, + { HPPA_INS_PROBERI, "(RR)iW", false }, + { HPPA_INS_PROBEW, "(RR)RW", false }, + { HPPA_INS_PROBEWI, "(RR)iW", false }, + { HPPA_INS_LPA, "r(Rb)W", false }, + { HPPA_INS_LCI, "r(RR)W", false }, + { HPPA_INS_PDTLB, "r(Rb)", false }, + { HPPA_INS_PITLB, "r(Rb)", false }, + { HPPA_INS_PDTLBE, "r(Rb)", false }, + { HPPA_INS_PITLBE, "r(Rb)", false }, + { HPPA_INS_IDTLBA, "R(RR)", false }, + { HPPA_INS_IITLBA, "R(RR)", false }, + { HPPA_INS_IDTLBP, "R(RR)", false }, + { HPPA_INS_IITLBP, "R(RR)", false }, + { HPPA_INS_PDC, "r(Rb)", false }, + { HPPA_INS_FDC, "x(Rb)", false }, + { HPPA_INS_FIC, "r(Rb)", false }, + { HPPA_INS_FDCE, "r(Rb)", false }, + { HPPA_INS_FICE, "r(Rb)", false }, + { HPPA_INS_DIAG, "i", false }, + { HPPA_INS_IDTLBT, "RR", false }, + { HPPA_INS_IITLBT, "RR", false }, + + { HPPA_INS_FLDW, "x(Rb)W", false }, + { HPPA_INS_FLDD, "x(Rb)W", false }, + { HPPA_INS_FSTW, "Rx(Rb)", false }, + { HPPA_INS_FSTD, "Rx(Rb)", false }, + { HPPA_INS_FLDWX, "r(Rb)W", false }, + { HPPA_INS_FLDDX, "r(Rb)W", false }, + { HPPA_INS_FSTWX, "Rr(Rb)", false }, + { HPPA_INS_FSTDX, "Rr(Rb)", false }, + { HPPA_INS_FSTQX, "", false }, + { HPPA_INS_FLDWS, "o(Rb)W", false }, + { HPPA_INS_FLDDS, "o(Rb)W", false }, + { HPPA_INS_FSTWS, "Ro(Rb)", false }, + { HPPA_INS_FSTDS, "Ro(Rb)", false }, + { HPPA_INS_FSTQS, "Ro(Rb)", false }, + { HPPA_INS_FADD, "RRW", false }, + { HPPA_INS_FSUB, "RRW", false }, + { HPPA_INS_FMPY, "RRW", false }, + { HPPA_INS_FDIV, "RRW", false }, + { HPPA_INS_FSQRT, "RW", false }, + { HPPA_INS_FABS, "RW", false }, + { HPPA_INS_FREM, "", false }, + { HPPA_INS_FRND, "RW", false }, + { HPPA_INS_FCPY, "RW", false }, + { HPPA_INS_FCNVFF, "RW", false }, + { HPPA_INS_FCNVXF, "RW", false }, + { HPPA_INS_FCNVFX, "RW", false }, + { HPPA_INS_FCNVFXT, "RW", false }, + { HPPA_INS_FMPYFADD, "RRRW", false }, + { HPPA_INS_FMPYNFADD, "RRRW", false }, + { HPPA_INS_FNEG, "RW", false }, + { HPPA_INS_FNEGABS, "RW", false }, + { HPPA_INS_FCNV, "RW", false }, + { HPPA_INS_FCMP, "RR", false }, + { HPPA_INS_FCMP, "RRi", true }, + { HPPA_INS_XMPYU, "RRW", false }, + { HPPA_INS_FMPYADD, "RRWRw", false }, + { HPPA_INS_FMPYSUB, "RRWRw", false }, + { HPPA_INS_FTEST, "", false }, + { HPPA_INS_FTEST, "i", true }, + { HPPA_INS_FID, "", false }, + + { HPPA_INS_PMDIS, "", false }, + { HPPA_INS_PMENB, "", false }, + + { HPPA_INS_SPOP0, "", false }, + { HPPA_INS_SPOP1, "W", false }, + { HPPA_INS_SPOP2, "R", false }, + { HPPA_INS_SPOP3, "RR", false }, + { HPPA_INS_COPR, "", false }, + { HPPA_INS_CLDW, "x(Rb)W", false }, + { HPPA_INS_CLDD, "o(Rb)W", false }, + { HPPA_INS_CSTW, "Rx(Rb)", false }, + { HPPA_INS_CSTD, "Rx(Rb)", false }, + { HPPA_INS_CLDWX, "r(Rb)W", false }, + { HPPA_INS_CLDDX, "r(Rb)W", false }, + { HPPA_INS_CSTWX, "Rr(Rb)", false }, + { HPPA_INS_CSTDX, "Rr(Rb)", false }, + { HPPA_INS_CLDWS, "o(Rb)W", false }, + { HPPA_INS_CLDDS, "o(Rb)W", false }, + { HPPA_INS_CSTWS, "Ro(Rb)", false }, + { HPPA_INS_CSTDS, "Ro(Rb)", false }, + + { HPPA_INS_CALL, "", false }, + { HPPA_INS_RET, "", false }, +}; + +static void print_operand(MCInst *MI, SStream *O, const cs_hppa_op *op) +{ + switch (op->type) { + case HPPA_OP_INVALID: + SStream_concat(O, "invalid"); + break; + case HPPA_OP_REG: + SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg)); + break; + case HPPA_OP_IMM: + printInt32(O, op->imm); + break; + case HPPA_OP_DISP: + printInt32(O, op->imm); + break; + case HPPA_OP_IDX_REG: + SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->reg)); + break; + case HPPA_OP_MEM: + SStream_concat(O, "("); + if (op->mem.space != HPPA_OP_INVALID && + op->mem.space != HPPA_REG_SR0) { + SStream_concat(O, HPPA_reg_name((csh)MI->csh, + op->mem.space)); + SStream_concat(O, ","); + } + SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->mem.base)); + SStream_concat(O, ")"); + break; + case HPPA_OP_TARGET: + printUInt64(O, MI->address + op->imm); + break; + } +} + +#define NUMFMTS ARR_SIZE(pa_formats) + +static void fill_operands(MCInst *MI, cs_hppa *hppa) +{ + hppa->op_count = 0; + unsigned mc_op_count = MCInst_getNumOperands(MI); + if (mc_op_count == 0) + return; + + hppa_ext *hppa_ext = &MI->hppa_ext; + uint32_t opcode = MCInst_getOpcode(MI); + + for (int i = 0; i < NUMFMTS; ++i) { + const struct pa_insn_fmt *pa_fmt = &pa_formats[i]; + if (opcode != pa_fmt->insn_id || + hppa_ext->is_alternative != pa_fmt->is_alternative) { + continue; + } + const char *fmt = pa_fmt->format; + uint8_t idx = 0; + uint32_t space_regs[2] = { HPPA_REG_INVALID, HPPA_REG_INVALID }; + uint8_t space_reg_idx = 0; + cs_ac_type base_access = CS_AC_INVALID; + MCOperand *op = NULL; + while (*fmt) { + op = MCInst_getOperand(MI, idx++); + switch (*fmt++) { + case 'i': + if (MCOperand_isReg(op)) { + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_READ); + } else { + set_op_imm(hppa, MCOperand_getImm(op)); + } + break; + case 'o': + set_op_disp(hppa, MCOperand_getImm(op)); + break; + + case 'R': + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_READ); + break; + + case 'W': + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_WRITE); + break; + + case 'w': + set_op_reg(hppa, MCOperand_getReg(op), + CS_AC_READ_WRTE); + break; + + case 'r': + set_op_idx_reg(hppa, MCOperand_getReg(op)); + break; + + case 'T': + set_op_target(hppa, MCOperand_getImm(op) + 8); + break; + + case 'x': + if (MCOperand_isReg(op)) { + set_op_idx_reg(hppa, + MCOperand_getReg(op)); + } else { + set_op_disp(hppa, MCOperand_getImm(op)); + } + break; + + case '(': + while (*fmt != ')') { + if (space_reg_idx > 0) { + op = MCInst_getOperand(MI, + idx++); + } + assert(space_reg_idx < + ARR_SIZE(space_regs)); + space_regs[space_reg_idx] = + MCOperand_getReg(op); + if (*fmt == 'R') { + base_access = CS_AC_READ; + } else if (*fmt == 'W') { + base_access = CS_AC_WRITE; + } else if (*fmt == 'b') { + base_access = CS_AC_READ; + if (hppa_ext->b_writeble) + base_access |= + CS_AC_WRITE; + } + fmt++; + space_reg_idx++; + } + + if (space_regs[1] == HPPA_REG_INVALID) + set_op_mem(hppa, space_regs[0], + space_regs[1], base_access); + else + set_op_mem(hppa, space_regs[1], + space_regs[0], base_access); + fmt++; + break; + + default: + printf("Unknown: %c\n", *(fmt - 1)); + break; + } + } + break; + } +} + +static void print_modifiers(MCInst *MI, SStream *O) +{ + hppa_ext *hppa_ext = &MI->hppa_ext; + for (uint8_t i = 0; i < hppa_ext->mod_num; ++i) { + SStream_concat(O, ","); + if (hppa_ext->modifiers[i].type == HPPA_MOD_STR) + SStream_concat(O, hppa_ext->modifiers[i].str_mod); + else + SStream_concat(O, "%d", hppa_ext->modifiers[i].int_mod); + } +} + +static void add_groups(MCInst *MI) +{ + unsigned int opcode = MCInst_getOpcode(MI); + for (unsigned i = 0; i < ARR_SIZE(pa_insns); ++i) { + if (pa_insns[i].insn != opcode) { + continue; + } + add_group(MI, pa_insns[i].grp); + } +} + +static void update_regs_access(MCInst *MI, unsigned int opcode) +{ + if (opcode == HPPA_INS_INVALID) + return; + + hppa_ext *hppa_ext = &MI->hppa_ext; + switch (opcode) { + default: + break; + case HPPA_INS_BLE: + map_add_implicit_write(MI, HPPA_REG_GR31); + map_add_implicit_write(MI, HPPA_REG_SR0); + break; + case HPPA_INS_BVB: + map_add_implicit_read(MI, HPPA_REG_CR11); + break; + case HPPA_INS_RFI: + if (hppa_ext->mod_num == 0) { + break; + } + // fallthrough + case HPPA_INS_RFIR: + map_add_implicit_write(MI, HPPA_REG_GR1); + map_add_implicit_write(MI, HPPA_REG_GR8); + map_add_implicit_write(MI, HPPA_REG_GR9); + map_add_implicit_write(MI, HPPA_REG_GR16); + map_add_implicit_write(MI, HPPA_REG_GR17); + map_add_implicit_write(MI, HPPA_REG_GR24); + map_add_implicit_write(MI, HPPA_REG_GR25); + break; + case HPPA_INS_VDEP: + case HPPA_INS_VDEPI: + case HPPA_INS_VEXTRS: + case HPPA_INS_VEXTRU: + case HPPA_INS_VSHD: + case HPPA_INS_ZVDEPI: + map_add_implicit_read(MI, HPPA_REG_CR11); + break; + case HPPA_INS_ADDIL: + map_add_implicit_write(MI, HPPA_REG_GR1); + break; + } +} + +void HPPA_printInst(MCInst *MI, SStream *O, void *Info) +{ + cs_hppa hppa; + + /* set pubOpcode as instruction id */ + MCInst_setOpcodePub(MI, MCInst_getOpcode(MI)); + + SStream_concat(O, HPPA_insn_name((csh)MI->csh, MCInst_getOpcode(MI))); + print_modifiers(MI, O); + SStream_concat(O, " "); + fill_operands(MI, &hppa); + for (int i = 0; i < hppa.op_count; i++) { + cs_hppa_op *op = &hppa.operands[i]; + print_operand(MI, O, op); + if (op->type != HPPA_OP_IDX_REG && op->type != HPPA_OP_DISP && + i != hppa.op_count - 1) { + SStream_concat(O, ","); + } + } + + if (detail_is_set(MI)) { + cs_hppa *hppa_detail = HPPA_get_detail(MI); + *hppa_detail = hppa; + add_groups(MI); +#ifndef CAPSTONE_DIET + update_regs_access(MI, MCInst_getOpcode(MI)); +#endif + } +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAInstPrinter.h b/arch/HPPA/HPPAInstPrinter.h new file mode 100644 index 0000000000..8bf1c673b1 --- /dev/null +++ b/arch/HPPA/HPPAInstPrinter.h @@ -0,0 +1,25 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPAINSTPRINTER_H +#define CS_HPPAINSTPRINTER_H + +#include + +#include "../../MCInst.h" +#include "../../SStream.h" + +struct pa_insn { + hppa_insn insn; + hppa_insn_group grp; +}; + +struct pa_insn_fmt { + hppa_insn insn_id; + const char *format; + bool is_alternative; ///< true if some completer affects the instruction format +}; + +void HPPA_printInst(MCInst *MI, SStream *O, void *Info); + +#endif diff --git a/arch/HPPA/HPPAMapping.c b/arch/HPPA/HPPAMapping.c new file mode 100644 index 0000000000..75f03dc2d0 --- /dev/null +++ b/arch/HPPA/HPPAMapping.c @@ -0,0 +1,440 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include +#include + +#include "HPPAMapping.h" +#include "HPPAConstants.h" +#include "../../Mapping.h" +#include "../../utils.h" + +#ifndef CAPSTONE_DIET +static const name_map group_name_maps[] = { + { HPPA_GRP_INVALID, NULL }, + + { HPPA_GRP_COMPUTATION, "computation" }, + { HPPA_GRP_MULTIMEDIA, "multimedia" }, + { HPPA_GRP_MEM_REF, "memory_reference" }, + { HPPA_GRP_LONG_IMM, "long_imm" }, + { HPPA_GRP_BRANCH, "branch" }, + { HPPA_GRP_SYSCTRL, "system_control" }, + { HPPA_GRP_ASSIST, "assist" }, + { HPPA_GRP_FLOAT, "float" }, +}; +#endif + +const char *HPPA_group_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(group_name_maps, ARR_SIZE(group_name_maps), id); +#else + return NULL; +#endif +} + +#ifndef CAPSTONE_DIET +static const name_map insn_name_maps[HPPA_INS_ENDING] = { + { HPPA_INS_INVALID, NULL }, + + { HPPA_INS_ADD, "add" }, + { HPPA_INS_ADDI, "addi" }, + { HPPA_INS_ADDIO, "addio" }, + { HPPA_INS_ADDIT, "addit" }, + { HPPA_INS_ADDITO, "addito" }, + { HPPA_INS_ADDB, "addb" }, + { HPPA_INS_ADDBT, "addbt" }, + { HPPA_INS_ADDBF, "addbf" }, + { HPPA_INS_ADDIB, "addib" }, + { HPPA_INS_ADDIBT, "addibt" }, + { HPPA_INS_ADDIBF, "addibf" }, + { HPPA_INS_ADDIL, "addil" }, + { HPPA_INS_ADDC, "addc" }, + { HPPA_INS_ADDCO, "addco" }, + { HPPA_INS_ADDL, "addl" }, + { HPPA_INS_ADDO, "addo" }, + { HPPA_INS_AND, "and" }, + { HPPA_INS_ANDCM, "andcm" }, + { HPPA_INS_B, "b" }, + { HPPA_INS_BB, "bb" }, + { HPPA_INS_BE, "be" }, + { HPPA_INS_BL, "bl" }, + { HPPA_INS_BLE, "ble" }, + { HPPA_INS_BLR, "blr" }, + { HPPA_INS_BREAK, "break" }, + { HPPA_INS_BV, "bv" }, + { HPPA_INS_BVB, "bvb" }, + { HPPA_INS_BVE, "bve" }, + { HPPA_INS_CALL, "call" }, + { HPPA_INS_CLDD, "cldd" }, + { HPPA_INS_CLDDS, "cldds" }, + { HPPA_INS_CLDDX, "clddx" }, + { HPPA_INS_CLDW, "cldw" }, + { HPPA_INS_CLDWS, "cldws" }, + { HPPA_INS_CLDWX, "cldwx" }, + { HPPA_INS_CLRBTS, "clrbts" }, + { HPPA_INS_CMPB, "cmpb" }, + { HPPA_INS_CMPCLR, "cmpclr" }, + { HPPA_INS_CMPIB, "cmpib" }, + { HPPA_INS_CMPICLR, "cmpiclr" }, + { HPPA_INS_COMB, "comb" }, + { HPPA_INS_COMBT, "combt" }, + { HPPA_INS_COMBF, "combf" }, + { HPPA_INS_COMCLR, "comclr" }, + { HPPA_INS_COMIB, "comib" }, + { HPPA_INS_COMIBT, "comibt" }, + { HPPA_INS_COMIBF, "comibf" }, + { HPPA_INS_COMICLR, "comiclr" }, + { HPPA_INS_COPR, "copr" }, + { HPPA_INS_COPY, "copy" }, + { HPPA_INS_CSTD, "cstd" }, + { HPPA_INS_CSTDS, "cstds" }, + { HPPA_INS_CSTDX, "cstdx" }, + { HPPA_INS_CSTW, "cstw" }, + { HPPA_INS_CSTWS, "cstws" }, + { HPPA_INS_CSTWX, "cstwx" }, + { HPPA_INS_DCOR, "dcor" }, + { HPPA_INS_DEP, "dep" }, + { HPPA_INS_DEPI, "depi" }, + { HPPA_INS_DEPD, "depd" }, + { HPPA_INS_DEPDI, "depdi" }, + { HPPA_INS_DEPW, "depw" }, + { HPPA_INS_DEPWI, "depwi" }, + { HPPA_INS_DIAG, "diag" }, + { HPPA_INS_DS, "ds" }, + { HPPA_INS_EXTRD, "extrd" }, + { HPPA_INS_EXTRS, "extrs" }, + { HPPA_INS_EXTRU, "extru" }, + { HPPA_INS_EXTRW, "extrw" }, + { HPPA_INS_FABS, "fabs" }, + { HPPA_INS_FADD, "fadd" }, + { HPPA_INS_FCMP, "fcmp" }, + { HPPA_INS_FCNV, "fcnv" }, + { HPPA_INS_FCNVFF, "fcnvff" }, + { HPPA_INS_FCNVFX, "fcnvfx" }, + { HPPA_INS_FCNVFXT, "fcnvfxt" }, + { HPPA_INS_FCNVXF, "fcnvxf" }, + { HPPA_INS_FCPY, "fcpy" }, + { HPPA_INS_FDC, "fdc" }, + { HPPA_INS_FDCE, "fdce" }, + { HPPA_INS_FDIV, "fdiv" }, + { HPPA_INS_FIC, "fic" }, + { HPPA_INS_FICE, "fice" }, + { HPPA_INS_FID, "fid" }, + { HPPA_INS_FLDD, "fldd" }, + { HPPA_INS_FLDDS, "fldds" }, + { HPPA_INS_FLDDX, "flddx" }, + { HPPA_INS_FLDW, "fldw" }, + { HPPA_INS_FLDWS, "fldws" }, + { HPPA_INS_FLDWX, "fldwx" }, + { HPPA_INS_FMPY, "fmpy" }, + { HPPA_INS_FMPYADD, "fmpyadd" }, + { HPPA_INS_FMPYFADD, "fmpyfadd" }, + { HPPA_INS_FMPYNFADD, "fmpynfadd" }, + { HPPA_INS_FMPYSUB, "fmpysub" }, + { HPPA_INS_FNEG, "fneg" }, + { HPPA_INS_FNEGABS, "fnegabs" }, + { HPPA_INS_FREM, "frem" }, + { HPPA_INS_FRND, "frnd" }, + { HPPA_INS_FSQRT, "fsqrt" }, + { HPPA_INS_FSTD, "fstd" }, + { HPPA_INS_FSTDS, "fstds" }, + { HPPA_INS_FSTDX, "fstdx" }, + { HPPA_INS_FSTW, "fstw" }, + { HPPA_INS_FSTWS, "fstws" }, + { HPPA_INS_FSTWX, "fstwx" }, + { HPPA_INS_FSTQS, "fstqs" }, + { HPPA_INS_FSTQX, "fstqx" }, + { HPPA_INS_FSUB, "fsub" }, + { HPPA_INS_FTEST, "ftest" }, + { HPPA_INS_GATE, "gate" }, + { HPPA_INS_GFR, "gfr" }, + { HPPA_INS_GFW, "gfw" }, + { HPPA_INS_GRSHDW, "grshdw" }, + { HPPA_INS_HADD, "hadd" }, + { HPPA_INS_HAVG, "havg" }, + { HPPA_INS_HSHL, "hshl" }, + { HPPA_INS_HSHLADD, "hshladd" }, + { HPPA_INS_HSHR, "hshr" }, + { HPPA_INS_HSHRADD, "hshradd" }, + { HPPA_INS_HSUB, "hsub" }, + { HPPA_INS_IDTLBA, "idtlba" }, + { HPPA_INS_IDTLBP, "idtlbp" }, + { HPPA_INS_IDTLBT, "idtlbt" }, + { HPPA_INS_IDCOR, "idcor" }, + { HPPA_INS_IITLBA, "iitlba" }, + { HPPA_INS_IITLBP, "iitlbp" }, + { HPPA_INS_IITLBT, "iitlbt" }, + { HPPA_INS_LCI, "lci" }, + { HPPA_INS_LDB, "ldb" }, + { HPPA_INS_LDBS, "ldbs" }, + { HPPA_INS_LDBX, "ldbx" }, + { HPPA_INS_LDCD, "ldcd" }, + { HPPA_INS_LDCW, "ldcw" }, + { HPPA_INS_LDCWS, "ldcws" }, + { HPPA_INS_LDCWX, "ldcwx" }, + { HPPA_INS_LDD, "ldd" }, + { HPPA_INS_LDDA, "ldda" }, + { HPPA_INS_LDH, "ldh" }, + { HPPA_INS_LDHS, "ldhs" }, + { HPPA_INS_LDHX, "ldhx" }, + { HPPA_INS_LDI, "ldi" }, + { HPPA_INS_LDIL, "ldil" }, + { HPPA_INS_LDO, "ldo" }, + { HPPA_INS_LDSID, "ldsid" }, + { HPPA_INS_LDW, "ldw" }, + { HPPA_INS_LDWA, "ldwa" }, + { HPPA_INS_LDWAS, "ldwas" }, + { HPPA_INS_LDWAX, "ldwax" }, + { HPPA_INS_LDWM, "ldwm" }, + { HPPA_INS_LDWS, "ldws" }, + { HPPA_INS_LDWX, "ldwx" }, + { HPPA_INS_LPA, "lpa" }, + { HPPA_INS_MFCPU, "mfcpu" }, + { HPPA_INS_MFCTL, "mfctl" }, + { HPPA_INS_MFIA, "mfia" }, + { HPPA_INS_MFSP, "mfsp" }, + { HPPA_INS_MIXH, "mixh" }, + { HPPA_INS_MIXW, "mixw" }, + { HPPA_INS_MOVB, "movb" }, + { HPPA_INS_MOVIB, "movib" }, + { HPPA_INS_MTCPU, "mtcpu" }, + { HPPA_INS_MTCTL, "mtctl" }, + { HPPA_INS_MTSAR, "mtsar" }, + { HPPA_INS_MTSARCM, "mtsarcm" }, + { HPPA_INS_MTSM, "mtsm" }, + { HPPA_INS_MTSP, "mtsp" }, + { HPPA_INS_NOP, "nop" }, + { HPPA_INS_OR, "or" }, + { HPPA_INS_PDC, "pdc" }, + { HPPA_INS_PDTLB, "pdtlb" }, + { HPPA_INS_PDTLBE, "pdtlbe" }, + { HPPA_INS_PERMH, "permh" }, + { HPPA_INS_PITLB, "pitlb" }, + { HPPA_INS_PITLBE, "pitlbe" }, + { HPPA_INS_PMDIS, "pmdis" }, + { HPPA_INS_PMENB, "pmenb" }, + { HPPA_INS_POPBTS, "popbts" }, + { HPPA_INS_PROBE, "probe" }, + { HPPA_INS_PROBEI, "probei" }, + { HPPA_INS_PROBER, "prober" }, + { HPPA_INS_PROBERI, "proberi" }, + { HPPA_INS_PROBEW, "probew" }, + { HPPA_INS_PROBEWI, "probewi" }, + { HPPA_INS_PUSHBTS, "pushbts" }, + { HPPA_INS_PUSHNOM, "pushnom" }, + { HPPA_INS_RET, "ret" }, + { HPPA_INS_RFI, "rfi" }, + { HPPA_INS_RFIR, "rfir" }, + { HPPA_INS_RSM, "rsm" }, + { HPPA_INS_SHDWGR, "shdwgr" }, + { HPPA_INS_SHLADD, "shladd" }, + { HPPA_INS_SH1ADD, "sh1add" }, + { HPPA_INS_SH1ADDL, "sh1addl" }, + { HPPA_INS_SH1ADDO, "sh1addo" }, + { HPPA_INS_SH2ADD, "sh2add" }, + { HPPA_INS_SH2ADDL, "sh2addl" }, + { HPPA_INS_SH2ADDO, "sh2addo" }, + { HPPA_INS_SH3ADD, "sh3add" }, + { HPPA_INS_SH3ADDL, "sh3addl" }, + { HPPA_INS_SH3ADDO, "sh3addo" }, + { HPPA_INS_SHD, "shd" }, + { HPPA_INS_SHRPD, "shrpd" }, + { HPPA_INS_SHRPW, "shrpw" }, + { HPPA_INS_SPOP0, "spop0" }, + { HPPA_INS_SPOP1, "spop1" }, + { HPPA_INS_SPOP2, "spop2" }, + { HPPA_INS_SPOP3, "spop3" }, + { HPPA_INS_SSM, "ssm" }, + { HPPA_INS_STB, "stb" }, + { HPPA_INS_STBS, "stbs" }, + { HPPA_INS_STBY, "stby" }, + { HPPA_INS_STBYS, "stbys" }, + { HPPA_INS_STD, "std" }, + { HPPA_INS_STDA, "stda" }, + { HPPA_INS_STDBY, "stdby" }, + { HPPA_INS_STH, "sth" }, + { HPPA_INS_STHS, "sths" }, + { HPPA_INS_STW, "stw" }, + { HPPA_INS_STWA, "stwa" }, + { HPPA_INS_STWAS, "stwas" }, + { HPPA_INS_STWS, "stws" }, + { HPPA_INS_STWM, "stwm" }, + { HPPA_INS_SUB, "sub" }, + { HPPA_INS_SUBB, "subb" }, + { HPPA_INS_SUBBO, "subbo" }, + { HPPA_INS_SUBI, "subi" }, + { HPPA_INS_SUBIO, "subio" }, + { HPPA_INS_SUBO, "subo" }, + { HPPA_INS_SUBT, "subt" }, + { HPPA_INS_SUBTO, "subto" }, + { HPPA_INS_SYNC, "sync" }, + { HPPA_INS_SYNCDMA, "syncdma" }, + { HPPA_INS_TOCDIS, "tocdis" }, + { HPPA_INS_TOCEN, "tocen" }, + { HPPA_INS_UADDCM, "uaddcm" }, + { HPPA_INS_UADDCMT, "uaddcmt" }, + { HPPA_INS_UXOR, "uxor" }, + { HPPA_INS_VDEP, "vdep" }, + { HPPA_INS_VDEPI, "vdepi" }, + { HPPA_INS_VEXTRS, "vextrs" }, + { HPPA_INS_VEXTRU, "vextru" }, + { HPPA_INS_VSHD, "vshd" }, + { HPPA_INS_XMPYU, "xmpyu" }, + { HPPA_INS_XOR, "xor" }, + { HPPA_INS_ZDEP, "zdep" }, + { HPPA_INS_ZDEPI, "zdepi" }, + { HPPA_INS_ZVDEP, "zvdep" }, + { HPPA_INS_ZVDEPI, "zvdepi" }, +}; +#endif + +const char *HPPA_insn_name(csh handle, unsigned int id) +{ +#ifndef CAPSTONE_DIET + return id2name(insn_name_maps, ARR_SIZE(insn_name_maps), id); +#else + return NULL; +#endif +} + +/* Integer register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const reg_names[] = { + "flags", "r1", "rp", "r3", "r4", "r5", "r6", "r7", + "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", + "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", + "r24", "r25", "r26", "dp", "ret0", "ret1", "sp", "r31" +}; + +/* Floating point register names, indexed by the numbers which appear in the + opcodes. */ +static const char *const fp_reg_names[] = { + "fpsr", "fpe2", "fpe4", "fpe6", "fr4", "fr5", "fr6", "fr7", + "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", + "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", + "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31" +}; + +static const char *const control_reg[] = { + "rctr", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", + "pidr1", "pidr2", "ccr", "sar", "pidr3", "pidr4", "iva", "eiem", + "itmr", "pcsq", "pcoq", "iir", "isr", "ior", "ipsw", "eirr", + "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7" +}; + +static const char *const space_reg[] = { "sr0", "sr1", "sr2", "sr3", + "sr4", "sr5", "sr6", "sr7" }; + +static const char *const fpe_reg[] = { + "fpe1", "fpe3", "fpe5", "fpe7", "fr4R", "fr5R", "fr6R", "fr7R", + "fr8R", "fr9R", "fr10R", "fr11R", "fr12R", "fr13R", "fr14R", "fr15R", + "fr16R", "fr17R", "fr18R", "fr19R", "fr20R", "fr21R", "fr22R", "fr23R", + "fr24R", "fr25R", "fr26R", "fr27R", "fr28R", "fr29R", "fr30R", "fr31R" +}; + +static const char *const sp_fp_reg[] = { + "fr16L", "fr17L", "fr18L", "fr19L", "fr20L", "fr21L", "fr22L", "fr23L", + "fr24L", "fr25L", "fr26L", "fr27L", "fr28L", "fr29L", "fr30L", "fr31L", + "fr16R", "fr17R", "fr18R", "fr19R", "fr20R", "fr21R", "fr22R", "fr23R", + "fr24R", "fr25R", "fr26R", "fr27R", "fr28R", "fr29R", "fr30R", "fr31R" +}; + +const char *HPPA_reg_name(csh handle, unsigned int reg) +{ +#ifndef CAPSTONE_DIET + if (reg >= HPPA_REG_GR0 && reg <= HPPA_REG_GR31) + return reg_names[reg - HPPA_REG_GR0]; + else if (reg >= HPPA_REG_FPR0 && reg <= HPPA_REG_FPR31) + return fp_reg_names[reg - HPPA_REG_FPR0]; + else if (reg >= HPPA_REG_SR0 && reg <= HPPA_REG_SR7) + return space_reg[reg - HPPA_REG_SR0]; + else if (reg >= HPPA_REG_CR0 && reg <= HPPA_REG_CR31) + return control_reg[reg - HPPA_REG_CR0]; + else if (reg >= HPPA_REG_FPE0 && reg <= HPPA_REG_FPE31) + return fpe_reg[reg - HPPA_REG_FPE0]; + else if (reg >= HPPA_REG_SP_FPR0 && reg <= HPPA_REG_SP_FPR31) + return sp_fp_reg[reg - HPPA_REG_SP_FPR0]; + return NULL; +#else + return NULL; +#endif +} + +void HPPA_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int opcode) +{ + insn->id = opcode; +} + +static void sort_and_uniq(cs_regs arr, uint8_t n, uint8_t *new_n) +{ + /* arr is always a tiny (usually n < 3) array, + * a simple O(n^2) sort is efficient enough. */ + int i; + int j; + int iMin; + int tmp; + + /* a modified selection sort for sorting and making unique */ + for (j = 0; j < n; j++) { + /* arr[iMin] will be min(arr[j .. n-1]) */ + iMin = j; + for (i = j + 1; i < n; i++) { + if (arr[i] < arr[iMin]) + iMin = i; + } + if (j != 0 && arr[iMin] == arr[j - 1]) { // duplicate ele found + arr[iMin] = arr[n - 1]; + --n; + } else { + tmp = arr[iMin]; + arr[iMin] = arr[j]; + arr[j] = tmp; + } + } + + *new_n = n; +} + +void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count) +{ + uint8_t read_count = 0; + uint8_t write_count = 0; + const cs_hppa *hppa = &(insn->detail->hppa); + + for (unsigned i = 0; i < hppa->op_count; ++i) { + const cs_hppa_op *op = &(hppa->operands[i]); + switch (op->type) { + case HPPA_OP_REG: + case HPPA_OP_IDX_REG: + if (op->access & CS_AC_READ) { + regs_read[read_count++] = op->reg; + } + if (op->access & CS_AC_WRITE) { + regs_write[write_count++] = op->reg; + } + break; + case HPPA_OP_MEM: + if (op->mem.space != HPPA_OP_INVALID) + regs_read[read_count++] = op->mem.space; + if (op->mem.base_access & CS_AC_READ) { + regs_read[read_count++] = op->mem.base; + } + if (op->mem.base_access & CS_AC_WRITE) { + regs_write[write_count++] = op->mem.base; + } + break; + default: + break; + } + } + + sort_and_uniq(regs_read, read_count, regs_read_count); + sort_and_uniq(regs_write, write_count, regs_write_count); +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAMapping.h b/arch/HPPA/HPPAMapping.h new file mode 100644 index 0000000000..6b62fe3a3a --- /dev/null +++ b/arch/HPPA/HPPAMapping.h @@ -0,0 +1,19 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPAMAPPING_H +#define CS_HPPAMAPPING_H + +#include + +#include "../../cs_priv.h" + +const char *HPPA_group_name(csh handle, unsigned int id); +const char *HPPA_insn_name(csh handle, unsigned int id); +const char *HPPA_reg_name(csh handle, unsigned int reg); +void HPPA_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id); +void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read, + uint8_t *regs_read_count, cs_regs regs_write, + uint8_t *regs_write_count); + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAModule.c b/arch/HPPA/HPPAModule.c new file mode 100644 index 0000000000..ad4c9663ef --- /dev/null +++ b/arch/HPPA/HPPAModule.c @@ -0,0 +1,34 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifdef CAPSTONE_HAS_HPPA + +#include "HPPADisassembler.h" +#include "HPPAInstPrinter.h" +#include "HPPAMapping.h" +#include "HPPAModule.h" + +cs_err HPPA_global_init(cs_struct *ud) +{ + ud->printer = HPPA_printInst; + ud->reg_name = HPPA_reg_name; + ud->insn_id = HPPA_get_insn_id; + ud->insn_name = HPPA_insn_name; + ud->group_name = HPPA_group_name; +#ifndef CAPSTONE_DIET + ud->reg_access = HPPA_reg_access; +#endif + ud->disasm = HPPA_getInstruction; + + return CS_ERR_OK; +} + +cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value) +{ + if (type == CS_OPT_MODE) + handle->mode = (cs_mode)value; + + return CS_ERR_OK; +} + +#endif \ No newline at end of file diff --git a/arch/HPPA/HPPAModule.h b/arch/HPPA/HPPAModule.h new file mode 100644 index 0000000000..c1949ec1b5 --- /dev/null +++ b/arch/HPPA/HPPAModule.h @@ -0,0 +1,12 @@ +/* Capstone Disassembly Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#ifndef CS_HPPA_MODULE_H +#define CS_HPPA_MODULE_H + +#include "../../utils.h" + +cs_err HPPA_global_init(cs_struct *ud); +cs_err HPPA_option(cs_struct *handle, cs_opt_type type, size_t value); + +#endif diff --git a/bindings/Makefile b/bindings/Makefile index c730917d40..85e5705001 100644 --- a/bindings/Makefile +++ b/bindings/Makefile @@ -24,6 +24,7 @@ TEST_TRICORE = $(TMPDIR)/test_tricore TEST_SH = $(TMPDIR)/test_sh TEST_TMS320C64X = $(TMPDIR)/test_tms320c64x TEST_ALPHA = $(TMPDIR)/test_alpha +TEST_HPPA = $(TMPDIR)/test_hppa PYTHON3 ?= python3 @@ -66,6 +67,7 @@ expected: ../tests/test_tricore > $(TEST_TRICORE)_e ../tests/test_tms320c64x > $(TEST_TMS320C64X)_e ../tests/test_alpha > $(TEST_ALPHA)_e + ../tests/test_hppa > $(TEST_HPPA)_e python: FORCE cd python && $(MAKE) @@ -91,6 +93,7 @@ python: FORCE $(PYTHON3) python/test_tricore.py > $(TEST_TRICORE)_o $(PYTHON3) python/test_tms320c64x.py > $(TEST_TMS320C64X)_o $(PYTHON3) python/test_alpha.py > $(TEST_ALPHA)_o + $(PYTHON3) python/test_hppa.py > $(TEST_HPPA)_o $(MAKE) test_diff java: FORCE @@ -131,6 +134,7 @@ test_diff: FORCE $(DIFF) $(TEST_TRICORE)_e $(TEST_TRICORE)_o $(DIFF) $(TEST_TMS320C64X)_e $(TEST_TMS320C64X)_o $(DIFF) $(TEST_ALPHA)_e $(TEST_ALPHA)_o + $(DIFF) $(TEST_HPPA)_e $(TEST_HPPA)_o clean: rm -rf $(TMPDIR) diff --git a/bindings/const_generator.py b/bindings/const_generator.py index 2171c7b78c..70bd94ef33 100644 --- a/bindings/const_generator.py +++ b/bindings/const_generator.py @@ -5,7 +5,7 @@ INCL_DIR = '../include/capstone/' -include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h' ] +include = [ 'arm.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h' ] template = { 'java': { @@ -54,6 +54,7 @@ 'sh.h': 'sh', 'tricore.h': ['TRICORE', 'TriCore'], 'alpha.h': ['ALPHA', 'Alpha'], + 'hppa.h': 'hppa', 'comment_open': '#', 'comment_close': '', }, diff --git a/bindings/python/Makefile b/bindings/python/Makefile index a1e6f7bf19..10b9af3134 100644 --- a/bindings/python/Makefile +++ b/bindings/python/Makefile @@ -71,7 +71,7 @@ clean: TESTS = test_basic.py test_detail.py test_arm.py test_aarch64.py test_m68k.py test_mips.py TESTS += test_ppc.py test_sparc.py test_systemz.py test_x86.py test_xcore.py test_tms320c64x.py TESTS += test_m680x.py test_skipdata.py test_mos65xx.py test_bpf.py test_riscv.py -TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py +TESTS += test_evm.py test_tricore.py test_wasm.py test_sh.py test_hppa.py TESTS += test_lite.py test_iter.py test_customized_mnem.py test_alpha.py check: diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 729fb58296..8e1174e396 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -42,6 +42,7 @@ 'CS_ARCH_SH', 'CS_ARCH_TRICORE', 'CS_ARCH_ALPHA', + 'CS_ARCH_HPPA', 'CS_ARCH_ALL', 'CS_MODE_LITTLE_ENDIAN', @@ -106,6 +107,9 @@ 'CS_MODE_TRICORE_160', 'CS_MODE_TRICORE_161', 'CS_MODE_TRICORE_162', + 'CS_MODE_HPPA_11', + 'CS_MODE_HPPA_20', + 'CS_MODE_HPPA_20W', 'CS_OPT_SYNTAX', 'CS_OPT_SYNTAX_DEFAULT', @@ -219,7 +223,8 @@ CS_ARCH_SH = 16 CS_ARCH_TRICORE = 17 CS_ARCH_ALPHA = 18 -CS_ARCH_MAX = 19 +CS_ARCH_HPPA = 19 +CS_ARCH_MAX = 20 CS_ARCH_ALL = 0xFFFF # disasm mode @@ -285,6 +290,9 @@ CS_MODE_TRICORE_160 = 1 << 5 # Tricore 1.6 CS_MODE_TRICORE_161 = 1 << 6 # Tricore 1.6.1 CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2 +CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1 +CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0 +CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide # Capstone option type CS_OPT_INVALID = 0 # No option specified @@ -443,7 +451,7 @@ def copy_ctypes_list(src): return [copy_ctypes(n) for n in src] # Weird import placement because these modules are needed by the below code but need the above functions -from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha +from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha, hppa class _cs_arch(ctypes.Union): _fields_ = ( @@ -466,6 +474,7 @@ class _cs_arch(ctypes.Union): ('sh', sh.CsSH), ('tricore', tricore.CsTriCore), ('alpha', alpha.CsAlpha), + ('hppa', hppa.CsHPPA), ) class _cs_detail(ctypes.Structure): @@ -817,6 +826,8 @@ def __gen_detail(self): (self.update_flags, self.operands) = tricore.get_arch_info(self._raw.detail.contents.arch.tricore) elif arch == CS_ARCH_ALPHA: (self.operands) = alpha.get_arch_info(self._raw.detail.contents.arch.alpha) + elif arch == CS_ARCH_HPPA: + (self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa) def __getattr__(self, name): @@ -1310,6 +1321,7 @@ def debug(): "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX, 'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE, 'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA, + 'hppa': CS_ARCH_HPPA } all_archs = "" diff --git a/bindings/python/capstone/hppa.py b/bindings/python/capstone/hppa.py new file mode 100644 index 0000000000..3bc1077de4 --- /dev/null +++ b/bindings/python/capstone/hppa.py @@ -0,0 +1,72 @@ +# Capstone Python bindings, by Dmitry Sibirtsev + +import ctypes +from . import copy_ctypes_list +from .hppa_const import * + + + +class HPPAOpMem(ctypes.Structure): + _fields_ = ( + ('base', ctypes.c_uint), + ('space', ctypes.c_uint), + ('base_access', ctypes.c_uint8), + ) + +class HPPAModifierValue(ctypes.Union): + _fields_ = ( + ('str_mod', ctypes.c_char_p), + ('int_mod', ctypes.c_uint32) + ) + +class HPPAModifier(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_int), + ('value', HPPAModifierValue) + ) + +class HPPAExt(ctypes.Structure): + _fields_ = ( + ('modifiers', HPPAModifier * 5), + ('mod_num', ctypes.c_uint8), + ('b_writable', ctypes.c_bool), + ('cmplt', ctypes.c_bool) + ) + +class HPPAOpValue(ctypes.Union): + _fields_ = ( + ('reg', ctypes.c_uint), + ('imm', ctypes.c_int64), + ('mem', HPPAOpMem) + ) + + +class HPPAOp(ctypes.Structure): + _fields_ = ( + ('type', ctypes.c_uint8), + ('value', HPPAOpValue), + ('access', ctypes.c_uint8) + ) + + @property + def imm(self): + return self.value.imm + + @property + def reg(self): + return self.value.reg + + @property + def mem(self): + return self.value.mem + + +# Instruction structure +class CsHPPA(ctypes.Structure): + _fields_ = ( + ('op_count', ctypes.c_uint8), + ('operands', HPPAOp * 5) + ) + +def get_arch_info(a): + return (copy_ctypes_list(a.operands[:a.op_count])) diff --git a/bindings/python/capstone/hppa_const.py b/bindings/python/capstone/hppa_const.py new file mode 100644 index 0000000000..060ce987c9 --- /dev/null +++ b/bindings/python/capstone/hppa_const.py @@ -0,0 +1,453 @@ +from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM +# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [hppa_const.py] +HPPA_MAX_OPS = 5 +HPPA_STR_MODIFIER_LEN = 8 +HPPA_MAX_MODIFIERS_LEN = 5 + +HPPA_OP_INVALID = 0 +HPPA_OP_REG = 1 +HPPA_OP_IMM = 2 +HPPA_OP_IDX_REG = 3 +HPPA_OP_DISP = 4 +HPPA_OP_MEM = 5 +HPPA_OP_TARGET = 6 + +# HPPA registers + +HPPA_REG_INVALID = 0 +HPPA_REG_GR0 = 1 +HPPA_REG_GR1 = 2 +HPPA_REG_GR2 = 3 +HPPA_REG_GR3 = 4 +HPPA_REG_GR4 = 5 +HPPA_REG_GR5 = 6 +HPPA_REG_GR6 = 7 +HPPA_REG_GR7 = 8 +HPPA_REG_GR8 = 9 +HPPA_REG_GR9 = 10 +HPPA_REG_GR10 = 11 +HPPA_REG_GR11 = 12 +HPPA_REG_GR12 = 13 +HPPA_REG_GR13 = 14 +HPPA_REG_GR14 = 15 +HPPA_REG_GR15 = 16 +HPPA_REG_GR16 = 17 +HPPA_REG_GR17 = 18 +HPPA_REG_GR18 = 19 +HPPA_REG_GR19 = 20 +HPPA_REG_GR20 = 21 +HPPA_REG_GR21 = 22 +HPPA_REG_GR22 = 23 +HPPA_REG_GR23 = 24 +HPPA_REG_GR24 = 25 +HPPA_REG_GR25 = 26 +HPPA_REG_GR26 = 27 +HPPA_REG_GR27 = 28 +HPPA_REG_GR28 = 29 +HPPA_REG_GR29 = 30 +HPPA_REG_GR30 = 31 +HPPA_REG_GR31 = 32 +HPPA_REG_FPR0 = 33 +HPPA_REG_FPR1 = 34 +HPPA_REG_FPR2 = 35 +HPPA_REG_FPR3 = 36 +HPPA_REG_FPR4 = 37 +HPPA_REG_FPR5 = 38 +HPPA_REG_FPR6 = 39 +HPPA_REG_FPR7 = 40 +HPPA_REG_FPR8 = 41 +HPPA_REG_FPR9 = 42 +HPPA_REG_FPR10 = 43 +HPPA_REG_FPR11 = 44 +HPPA_REG_FPR12 = 45 +HPPA_REG_FPR13 = 46 +HPPA_REG_FPR14 = 47 +HPPA_REG_FPR15 = 48 +HPPA_REG_FPR16 = 49 +HPPA_REG_FPR17 = 50 +HPPA_REG_FPR18 = 51 +HPPA_REG_FPR19 = 52 +HPPA_REG_FPR20 = 53 +HPPA_REG_FPR21 = 54 +HPPA_REG_FPR22 = 55 +HPPA_REG_FPR23 = 56 +HPPA_REG_FPR24 = 57 +HPPA_REG_FPR25 = 58 +HPPA_REG_FPR26 = 59 +HPPA_REG_FPR27 = 60 +HPPA_REG_FPR28 = 61 +HPPA_REG_FPR29 = 62 +HPPA_REG_FPR30 = 63 +HPPA_REG_FPR31 = 64 +HPPA_REG_SR0 = 65 +HPPA_REG_SR1 = 66 +HPPA_REG_SR2 = 67 +HPPA_REG_SR3 = 68 +HPPA_REG_SR4 = 69 +HPPA_REG_SR5 = 70 +HPPA_REG_SR6 = 71 +HPPA_REG_SR7 = 72 +HPPA_REG_CR0 = 73 +HPPA_REG_CR1 = 74 +HPPA_REG_CR2 = 75 +HPPA_REG_CR3 = 76 +HPPA_REG_CR4 = 77 +HPPA_REG_CR5 = 78 +HPPA_REG_CR6 = 79 +HPPA_REG_CR7 = 80 +HPPA_REG_CR8 = 81 +HPPA_REG_CR9 = 82 +HPPA_REG_CR10 = 83 +HPPA_REG_CR11 = 84 +HPPA_REG_CR12 = 85 +HPPA_REG_CR13 = 86 +HPPA_REG_CR14 = 87 +HPPA_REG_CR15 = 88 +HPPA_REG_CR16 = 89 +HPPA_REG_CR17 = 90 +HPPA_REG_CR18 = 91 +HPPA_REG_CR19 = 92 +HPPA_REG_CR20 = 93 +HPPA_REG_CR21 = 94 +HPPA_REG_CR22 = 95 +HPPA_REG_CR23 = 96 +HPPA_REG_CR24 = 97 +HPPA_REG_CR25 = 98 +HPPA_REG_CR26 = 99 +HPPA_REG_CR27 = 100 +HPPA_REG_CR28 = 101 +HPPA_REG_CR29 = 102 +HPPA_REG_CR30 = 103 +HPPA_REG_CR31 = 104 +HPPA_REG_FPE0 = 105 +HPPA_REG_FPE1 = 106 +HPPA_REG_FPE2 = 107 +HPPA_REG_FPE3 = 108 +HPPA_REG_FPE4 = 109 +HPPA_REG_FPE5 = 110 +HPPA_REG_FPE6 = 111 +HPPA_REG_FPE7 = 112 +HPPA_REG_FPE8 = 113 +HPPA_REG_FPE9 = 114 +HPPA_REG_FPE10 = 115 +HPPA_REG_FPE11 = 116 +HPPA_REG_FPE12 = 117 +HPPA_REG_FPE13 = 118 +HPPA_REG_FPE14 = 119 +HPPA_REG_FPE15 = 120 +HPPA_REG_FPE16 = 121 +HPPA_REG_FPE17 = 122 +HPPA_REG_FPE18 = 123 +HPPA_REG_FPE19 = 124 +HPPA_REG_FPE20 = 125 +HPPA_REG_FPE21 = 126 +HPPA_REG_FPE22 = 127 +HPPA_REG_FPE23 = 128 +HPPA_REG_FPE24 = 129 +HPPA_REG_FPE25 = 130 +HPPA_REG_FPE26 = 131 +HPPA_REG_FPE27 = 132 +HPPA_REG_FPE28 = 133 +HPPA_REG_FPE29 = 134 +HPPA_REG_FPE30 = 135 +HPPA_REG_FPE31 = 136 +HPPA_REG_SP_FPR0 = 137 +HPPA_REG_SP_FPR1 = 138 +HPPA_REG_SP_FPR2 = 139 +HPPA_REG_SP_FPR3 = 140 +HPPA_REG_SP_FPR4 = 141 +HPPA_REG_SP_FPR5 = 142 +HPPA_REG_SP_FPR6 = 143 +HPPA_REG_SP_FPR7 = 144 +HPPA_REG_SP_FPR8 = 145 +HPPA_REG_SP_FPR9 = 146 +HPPA_REG_SP_FPR10 = 147 +HPPA_REG_SP_FPR11 = 148 +HPPA_REG_SP_FPR12 = 149 +HPPA_REG_SP_FPR13 = 150 +HPPA_REG_SP_FPR14 = 151 +HPPA_REG_SP_FPR15 = 152 +HPPA_REG_SP_FPR16 = 153 +HPPA_REG_SP_FPR17 = 154 +HPPA_REG_SP_FPR18 = 155 +HPPA_REG_SP_FPR19 = 156 +HPPA_REG_SP_FPR20 = 157 +HPPA_REG_SP_FPR21 = 158 +HPPA_REG_SP_FPR22 = 159 +HPPA_REG_SP_FPR23 = 160 +HPPA_REG_SP_FPR24 = 161 +HPPA_REG_SP_FPR25 = 162 +HPPA_REG_SP_FPR26 = 163 +HPPA_REG_SP_FPR27 = 164 +HPPA_REG_SP_FPR28 = 165 +HPPA_REG_SP_FPR29 = 166 +HPPA_REG_SP_FPR30 = 167 +HPPA_REG_SP_FPR31 = 168 +HPPA_REG_ENDING = 169 + +HPPA_INS_INVALID = 0 +HPPA_INS_ADD = 1 +HPPA_INS_ADDI = 2 +HPPA_INS_ADDIO = 3 +HPPA_INS_ADDIT = 4 +HPPA_INS_ADDITO = 5 +HPPA_INS_ADDB = 6 +HPPA_INS_ADDBT = 7 +HPPA_INS_ADDBF = 8 +HPPA_INS_ADDIB = 9 +HPPA_INS_ADDIBT = 10 +HPPA_INS_ADDIBF = 11 +HPPA_INS_ADDIL = 12 +HPPA_INS_ADDC = 13 +HPPA_INS_ADDCO = 14 +HPPA_INS_ADDL = 15 +HPPA_INS_ADDO = 16 +HPPA_INS_AND = 17 +HPPA_INS_ANDCM = 18 +HPPA_INS_B = 19 +HPPA_INS_BB = 20 +HPPA_INS_BE = 21 +HPPA_INS_BL = 22 +HPPA_INS_BLE = 23 +HPPA_INS_BLR = 24 +HPPA_INS_BREAK = 25 +HPPA_INS_BV = 26 +HPPA_INS_BVB = 27 +HPPA_INS_BVE = 28 +HPPA_INS_CALL = 29 +HPPA_INS_CLDD = 30 +HPPA_INS_CLDDS = 31 +HPPA_INS_CLDDX = 32 +HPPA_INS_CLDW = 33 +HPPA_INS_CLDWS = 34 +HPPA_INS_CLDWX = 35 +HPPA_INS_CLRBTS = 36 +HPPA_INS_CMPB = 37 +HPPA_INS_CMPCLR = 38 +HPPA_INS_CMPIB = 39 +HPPA_INS_CMPICLR = 40 +HPPA_INS_COMB = 41 +HPPA_INS_COMBT = 42 +HPPA_INS_COMBF = 43 +HPPA_INS_COMCLR = 44 +HPPA_INS_COMIB = 45 +HPPA_INS_COMIBT = 46 +HPPA_INS_COMIBF = 47 +HPPA_INS_COMICLR = 48 +HPPA_INS_COPR = 49 +HPPA_INS_COPY = 50 +HPPA_INS_CSTD = 51 +HPPA_INS_CSTDS = 52 +HPPA_INS_CSTDX = 53 +HPPA_INS_CSTW = 54 +HPPA_INS_CSTWS = 55 +HPPA_INS_CSTWX = 56 +HPPA_INS_DCOR = 57 +HPPA_INS_DEP = 58 +HPPA_INS_DEPI = 59 +HPPA_INS_DEPD = 60 +HPPA_INS_DEPDI = 61 +HPPA_INS_DEPW = 62 +HPPA_INS_DEPWI = 63 +HPPA_INS_DIAG = 64 +HPPA_INS_DS = 65 +HPPA_INS_EXTRD = 66 +HPPA_INS_EXTRS = 67 +HPPA_INS_EXTRU = 68 +HPPA_INS_EXTRW = 69 +HPPA_INS_FABS = 70 +HPPA_INS_FADD = 71 +HPPA_INS_FCMP = 72 +HPPA_INS_FCNV = 73 +HPPA_INS_FCNVFF = 74 +HPPA_INS_FCNVFX = 75 +HPPA_INS_FCNVFXT = 76 +HPPA_INS_FCNVXF = 77 +HPPA_INS_FCPY = 78 +HPPA_INS_FDC = 79 +HPPA_INS_FDCE = 80 +HPPA_INS_FDIV = 81 +HPPA_INS_FIC = 82 +HPPA_INS_FICE = 83 +HPPA_INS_FID = 84 +HPPA_INS_FLDD = 85 +HPPA_INS_FLDDS = 86 +HPPA_INS_FLDDX = 87 +HPPA_INS_FLDW = 88 +HPPA_INS_FLDWS = 89 +HPPA_INS_FLDWX = 90 +HPPA_INS_FMPY = 91 +HPPA_INS_FMPYADD = 92 +HPPA_INS_FMPYFADD = 93 +HPPA_INS_FMPYNFADD = 94 +HPPA_INS_FMPYSUB = 95 +HPPA_INS_FNEG = 96 +HPPA_INS_FNEGABS = 97 +HPPA_INS_FREM = 98 +HPPA_INS_FRND = 99 +HPPA_INS_FSQRT = 100 +HPPA_INS_FSTD = 101 +HPPA_INS_FSTDS = 102 +HPPA_INS_FSTDX = 103 +HPPA_INS_FSTW = 104 +HPPA_INS_FSTWS = 105 +HPPA_INS_FSTWX = 106 +HPPA_INS_FSTQS = 107 +HPPA_INS_FSTQX = 108 +HPPA_INS_FSUB = 109 +HPPA_INS_FTEST = 110 +HPPA_INS_GATE = 111 +HPPA_INS_GFR = 112 +HPPA_INS_GFW = 113 +HPPA_INS_GRSHDW = 114 +HPPA_INS_HADD = 115 +HPPA_INS_HAVG = 116 +HPPA_INS_HSHL = 117 +HPPA_INS_HSHLADD = 118 +HPPA_INS_HSHR = 119 +HPPA_INS_HSHRADD = 120 +HPPA_INS_HSUB = 121 +HPPA_INS_IDTLBA = 122 +HPPA_INS_IDTLBP = 123 +HPPA_INS_IDTLBT = 124 +HPPA_INS_IDCOR = 125 +HPPA_INS_IITLBA = 126 +HPPA_INS_IITLBP = 127 +HPPA_INS_IITLBT = 128 +HPPA_INS_LCI = 129 +HPPA_INS_LDB = 130 +HPPA_INS_LDBS = 131 +HPPA_INS_LDBX = 132 +HPPA_INS_LDCD = 133 +HPPA_INS_LDCW = 134 +HPPA_INS_LDCWS = 135 +HPPA_INS_LDCWX = 136 +HPPA_INS_LDD = 137 +HPPA_INS_LDDA = 138 +HPPA_INS_LDH = 139 +HPPA_INS_LDHS = 140 +HPPA_INS_LDHX = 141 +HPPA_INS_LDI = 142 +HPPA_INS_LDIL = 143 +HPPA_INS_LDO = 144 +HPPA_INS_LDSID = 145 +HPPA_INS_LDW = 146 +HPPA_INS_LDWA = 147 +HPPA_INS_LDWAS = 148 +HPPA_INS_LDWAX = 149 +HPPA_INS_LDWM = 150 +HPPA_INS_LDWS = 151 +HPPA_INS_LDWX = 152 +HPPA_INS_LPA = 153 +HPPA_INS_MFCPU = 154 +HPPA_INS_MFCTL = 155 +HPPA_INS_MFIA = 156 +HPPA_INS_MFSP = 157 +HPPA_INS_MIXH = 158 +HPPA_INS_MIXW = 159 +HPPA_INS_MOVB = 160 +HPPA_INS_MOVIB = 161 +HPPA_INS_MTCPU = 162 +HPPA_INS_MTCTL = 163 +HPPA_INS_MTSAR = 164 +HPPA_INS_MTSARCM = 165 +HPPA_INS_MTSM = 166 +HPPA_INS_MTSP = 167 +HPPA_INS_NOP = 168 +HPPA_INS_OR = 169 +HPPA_INS_PDC = 170 +HPPA_INS_PDTLB = 171 +HPPA_INS_PDTLBE = 172 +HPPA_INS_PERMH = 173 +HPPA_INS_PITLB = 174 +HPPA_INS_PITLBE = 175 +HPPA_INS_PMDIS = 176 +HPPA_INS_PMENB = 177 +HPPA_INS_POPBTS = 178 +HPPA_INS_PROBE = 179 +HPPA_INS_PROBEI = 180 +HPPA_INS_PROBER = 181 +HPPA_INS_PROBERI = 182 +HPPA_INS_PROBEW = 183 +HPPA_INS_PROBEWI = 184 +HPPA_INS_PUSHBTS = 185 +HPPA_INS_PUSHNOM = 186 +HPPA_INS_RET = 187 +HPPA_INS_RFI = 188 +HPPA_INS_RFIR = 189 +HPPA_INS_RSM = 190 +HPPA_INS_SHDWGR = 191 +HPPA_INS_SHLADD = 192 +HPPA_INS_SH1ADD = 193 +HPPA_INS_SH1ADDL = 194 +HPPA_INS_SH1ADDO = 195 +HPPA_INS_SH2ADD = 196 +HPPA_INS_SH2ADDL = 197 +HPPA_INS_SH2ADDO = 198 +HPPA_INS_SH3ADD = 199 +HPPA_INS_SH3ADDL = 200 +HPPA_INS_SH3ADDO = 201 +HPPA_INS_SHD = 202 +HPPA_INS_SHRPD = 203 +HPPA_INS_SHRPW = 204 +HPPA_INS_SPOP0 = 205 +HPPA_INS_SPOP1 = 206 +HPPA_INS_SPOP2 = 207 +HPPA_INS_SPOP3 = 208 +HPPA_INS_SSM = 209 +HPPA_INS_STB = 210 +HPPA_INS_STBS = 211 +HPPA_INS_STBY = 212 +HPPA_INS_STBYS = 213 +HPPA_INS_STD = 214 +HPPA_INS_STDA = 215 +HPPA_INS_STDBY = 216 +HPPA_INS_STH = 217 +HPPA_INS_STHS = 218 +HPPA_INS_STW = 219 +HPPA_INS_STWA = 220 +HPPA_INS_STWAS = 221 +HPPA_INS_STWS = 222 +HPPA_INS_STWM = 223 +HPPA_INS_SUB = 224 +HPPA_INS_SUBB = 225 +HPPA_INS_SUBBO = 226 +HPPA_INS_SUBI = 227 +HPPA_INS_SUBIO = 228 +HPPA_INS_SUBO = 229 +HPPA_INS_SUBT = 230 +HPPA_INS_SUBTO = 231 +HPPA_INS_SYNC = 232 +HPPA_INS_SYNCDMA = 233 +HPPA_INS_TOCDIS = 234 +HPPA_INS_TOCEN = 235 +HPPA_INS_UADDCM = 236 +HPPA_INS_UADDCMT = 237 +HPPA_INS_UXOR = 238 +HPPA_INS_VDEP = 239 +HPPA_INS_VDEPI = 240 +HPPA_INS_VEXTRS = 241 +HPPA_INS_VEXTRU = 242 +HPPA_INS_VSHD = 243 +HPPA_INS_XMPYU = 244 +HPPA_INS_XOR = 245 +HPPA_INS_ZDEP = 246 +HPPA_INS_ZDEPI = 247 +HPPA_INS_ZVDEP = 248 +HPPA_INS_ZVDEPI = 249 +HPPA_INS_ENDING = 250 + +HPPA_MOD_STR = 0 +HPPA_MOD_INT = 1 + +HPPA_GRP_INVALID = 0 +HPPA_GRP_COMPUTATION = 128 +HPPA_GRP_MULTIMEDIA = 129 +HPPA_GRP_MEM_REF = 130 +HPPA_GRP_LONG_IMM = 131 +HPPA_GRP_BRANCH = 132 +HPPA_GRP_SYSCTRL = 133 +HPPA_GRP_ASSIST = 134 +HPPA_GRP_FLOAT = 135 +HPPA_GRP_PERFMON = 136 +HPPA_GRP_ENDING = 137 diff --git a/bindings/python/setup_cython.py b/bindings/python/setup_cython.py index 9d4de46caa..18323b563c 100644 --- a/bindings/python/setup_cython.py +++ b/bindings/python/setup_cython.py @@ -69,7 +69,7 @@ compile_args = ['-O3', '-fomit-frame-pointer', '-I' + HEADERS_DIR] link_args = ['-L' + LIBS_DIR] -ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const', 'alpha', 'alpha_const' ] +ext_module_names = ['arm', 'arm_const', 'aarch64', 'aarch64_const', 'm68k', 'm68k_const', 'm680x', 'm680x_const', 'mips', 'mips_const', 'ppc', 'ppc_const', 'x86', 'x86_const', 'sparc', 'sparc_const', 'systemz', 'sysz_const', 'xcore', 'xcore_const', 'tms320c64x', 'tms320c64x_const', 'evm', 'evm_const', 'mos65xx', 'mos65xx_const', 'wasm', 'wasm_const', 'bpf', 'bpf_const', 'riscv', 'riscv_const', 'sh', 'sh_const', 'tricore', 'tricore_const', 'alpha', 'alpha_const', 'hppa', 'hppa_const' ] ext_modules = [Extension("capstone.ccapstone", ["pyx/ccapstone.pyx"], diff --git a/bindings/python/test_all.py b/bindings/python/test_all.py index 2e70de6fdc..95b4c77322 100755 --- a/bindings/python/test_all.py +++ b/bindings/python/test_all.py @@ -2,7 +2,7 @@ import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \ test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \ - test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha + test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha, test_hppa test_basic.test_class() test_arm.test_class() @@ -23,3 +23,4 @@ test_xcore.test_class() test_riscv.test_class() test_alpha.test_class() +test_hppa.test_class() diff --git a/bindings/python/test_basic.py b/bindings/python/test_basic.py index fce582ad10..025715abb7 100755 --- a/bindings/python/test_basic.py +++ b/bindings/python/test_basic.py @@ -42,6 +42,10 @@ RISCV_CODE64 = b"\x13\x04\xa8\x7a" ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' all_tests = ( @@ -79,6 +83,10 @@ (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "RISCV64", None), (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), ) # ## Test cs_disasm_quick() diff --git a/bindings/python/test_detail.py b/bindings/python/test_detail.py index fc8cbeae80..56555871c8 100755 --- a/bindings/python/test_detail.py +++ b/bindings/python/test_detail.py @@ -32,6 +32,10 @@ EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00" ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' all_tests = ( (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), @@ -61,6 +65,10 @@ (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None), (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), ) diff --git a/bindings/python/test_hppa.py b/bindings/python/test_hppa.py new file mode 100755 index 0000000000..75fcd0c29d --- /dev/null +++ b/bindings/python/test_hppa.py @@ -0,0 +1,75 @@ +#!/usr/bin/env python3 + +# Capstone Python bindings, by Dmitry Sibirtsev + +from __future__ import print_function +from capstone import * +from capstone.hppa import * +from xprint import to_x, to_hex + +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' + +all_tests = ( + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)"), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)"), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)"), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)"), +) + + +def print_insn_detail(insn): + # print address, mnemonic and operands + print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str)) + + # "data" instruction generated by SKIPDATA option has no detail + if insn.id == 0: + return + + if len(insn.operands) > 0: + print("\top_count: %u" % len(insn.operands)) + c = 0 + for i in insn.operands: + if i.type == HPPA_OP_REG: + print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == HPPA_OP_IMM: + print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm))) + if i.type == HPPA_OP_IDX_REG: + print("\t\toperands[%u].type: IDX_REG = %s" % (c, insn.reg_name(i.reg))) + if i.type == HPPA_OP_DISP: + print("\t\toperands[%u].type: DISP = 0x%s" % (c, to_x(i.imm))) + if i.type == HPPA_OP_MEM: + print("\t\toperands[%u].type: MEM" % c) + if i.mem.space != HPPA_OP_INVALID: + print("\t\t\toperands[%u].mem.space: REG = %s" % (c, insn.reg_name(i.mem.space))) + print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base))) + if i.type == HPPA_OP_TARGET: + if i.imm >= 0x8000000000000000: + print("TARGET = -0x%lx" % i.imm) + else: + print("TARGET = 0x%lx" % i.imm) + c += 1 + +# ## Test class Cs +def test_class(): + for (arch, mode, code, comment) in all_tests: + print("*" * 16) + print("Platform: %s" % comment) + print("Code: %s" % to_hex(code)) + print("Disasm:") + + try: + md = Cs(arch, mode) + md.detail = True + for insn in md.disasm(code, 0x1000): + print_insn_detail(insn) + print() + print("0x%x:\n" % (insn.address + insn.size)) + except CsError as e: + print("ERROR: %s" % e) + + +if __name__ == '__main__': + test_class() diff --git a/bindings/python/test_iter.py b/bindings/python/test_iter.py index d966367cc7..abdac0678a 100755 --- a/bindings/python/test_iter.py +++ b/bindings/python/test_iter.py @@ -30,7 +30,10 @@ M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39" ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7' ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00' - +HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad' +HPPA_20_CODE = b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14' +HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1' +HPPA_11_CODE = b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c' all_tests = ( (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None), @@ -60,6 +63,10 @@ (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None), (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None), (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None), + (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None), + (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None), ) # ## Test class Cs diff --git a/cmake.sh b/cmake.sh index da942fd8ee..9e19c12d0d 100755 --- a/cmake.sh +++ b/cmake.sh @@ -60,6 +60,9 @@ case $1 in RISCV) ARCH=RISCV ;; + HPPA) + ARCH=HPPA + ;; *) ;; esac diff --git a/config.mk b/config.mk index 65ba9a0fcc..5b7a3d14e0 100644 --- a/config.mk +++ b/config.mk @@ -4,7 +4,7 @@ ################################################################################ # Specify which archs you want to compile in. By default, we build all archs. -CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha +CAPSTONE_ARCHS ?= arm aarch64 m68k mips powerpc sparc systemz x86 xcore tms320c64x m680x evm riscv mos65xx wasm bpf sh tricore alpha hppa ################################################################################ diff --git a/cs.c b/cs.c index 2e456830c1..25476df9f6 100644 --- a/cs.c +++ b/cs.c @@ -71,6 +71,7 @@ #include "arch/SH/SHModule.h" #include "arch/TriCore/TriCoreModule.h" #include "arch/Alpha/AlphaModule.h" +#include "arch/HPPA/HPPAModule.h" typedef struct cs_arch_config { // constructor initialization @@ -309,6 +310,16 @@ static const cs_arch_config arch_configs[MAX_ARCH] = { #else { NULL, NULL, 0 }, #endif +#ifdef CAPSTONE_HAS_HPPA + { + HPPA_global_init, + HPPA_option, + ~(CS_MODE_LITTLE_ENDIAN | CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11 + | CS_MODE_HPPA_20 | CS_MODE_HPPA_20W), + }, +#else + { NULL, NULL, 0 }, +#endif }; // bitmask of enabled architectures @@ -370,6 +381,9 @@ static const uint32_t all_arch = 0 #ifdef CAPSTONE_HAS_ALPHA | (1 << CS_ARCH_ALPHA) #endif +#ifdef CAPSTONE_HAS_HPPA + | (1 << CS_ARCH_HPPA) +#endif ; #endif @@ -603,7 +617,7 @@ bool CAPSTONE_API cs_support(int query) (1 << CS_ARCH_RISCV) | (1 << CS_ARCH_MOS65XX) | (1 << CS_ARCH_WASM) | (1 << CS_ARCH_BPF) | (1 << CS_ARCH_SH) | (1 << CS_ARCH_TRICORE) | - (1 << CS_ARCH_ALPHA)); + (1 << CS_ARCH_ALPHA) | (1 << CS_ARCH_HPPA)); if ((unsigned int)query < CS_ARCH_MAX) return all_arch & (1 << query); @@ -939,6 +953,9 @@ static uint8_t skipdata_size(cs_struct *handle) case CS_ARCH_ALPHA: // Alpha alignment is 4. return 4; + case CS_ARCH_HPPA: + // Hppa alignment is 4. + return 4; } } @@ -1683,6 +1700,11 @@ int CAPSTONE_API cs_op_count(csh ud, const cs_insn *insn, unsigned int op_type) if (insn->detail->alpha.operands[i].type == (alpha_op_type)op_type) count++; break; + case CS_ARCH_HPPA: + for (i = 0; i < insn->detail->hppa.op_count; i++) + if (insn->detail->hppa.operands[i].type == (hppa_op_type)op_type) + count++; + break; } return count; @@ -1874,6 +1896,14 @@ int CAPSTONE_API cs_op_index(csh ud, const cs_insn *insn, unsigned int op_type, return i; } break; + case CS_ARCH_HPPA: + for (i = 0; i < insn->detail->hppa.op_count; i++) { + if (insn->detail->hppa.operands[i].type == (hppa_op_type)op_type) + count++; + if (count == post) + return i; + } + break; } return -1; diff --git a/cstool/cstool.c b/cstool/cstool.c index 243c7b176e..88bc94a178 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -116,6 +116,12 @@ static struct { { "tc162", CS_ARCH_TRICORE, CS_MODE_TRICORE_162 }, { "alpha", CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN }, { "alphabe", CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN }, + { "hppa11", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_LITTLE_ENDIAN }, + { "hppa11be", CS_ARCH_HPPA, CS_MODE_HPPA_11 | CS_MODE_BIG_ENDIAN }, + { "hppa20", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_LITTLE_ENDIAN }, + { "hppa20be", CS_ARCH_HPPA, CS_MODE_HPPA_20 | CS_MODE_BIG_ENDIAN }, + { "hppa20w", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_LITTLE_ENDIAN }, + { "hppa20wbe", CS_ARCH_HPPA, CS_MODE_HPPA_20W | CS_MODE_BIG_ENDIAN }, { NULL } }; @@ -215,6 +221,15 @@ static void usage(char *prog) printf(" alphabe alpha + big endian\n"); } + if (cs_support(CS_ARCH_HPPA)) { + printf(" hppa11 hppa V1.1 + little endian\n"); + printf(" hppa11be hppa V1.1 + big endian\n"); + printf(" hppa20 hppa V2.0 + little endian\n"); + printf(" hppa20be hppa V2.0 + big endian\n"); + printf(" hppa20w hppa V2.0 wide + little endian\n"); + printf(" hppa20wbe hppa V2.0 wide + big endian\n"); + } + if (cs_support(CS_ARCH_MIPS)) { printf(" mips mips32 + little endian\n"); printf(" mipsbe mips32 + big endian\n"); @@ -402,6 +417,9 @@ static void print_details(csh handle, cs_arch arch, cs_mode md, cs_insn *ins) case CS_ARCH_ALPHA: print_insn_detail_alpha(handle, ins); break; + case CS_ARCH_HPPA: + print_insn_detail_hppa(handle, ins); + break; default: break; } @@ -541,6 +559,10 @@ int main(int argc, char **argv) if (cs_support(CS_ARCH_ALPHA)) { printf("alpha=1 "); } + + if (cs_support(CS_ARCH_HPPA)) { + printf("hppa=1 "); + } printf("\n"); return 0; diff --git a/cstool/cstool.h b/cstool/cstool.h index 076c7b604e..dfcf03bfa3 100644 --- a/cstool/cstool.h +++ b/cstool/cstool.h @@ -20,5 +20,6 @@ void print_insn_detail_bpf(csh handle, cs_insn *ins); void print_insn_detail_sh(csh handle, cs_insn *ins); void print_insn_detail_tricore(csh handle, cs_insn *ins); void print_insn_detail_alpha(csh handle, cs_insn *ins); +void print_insn_detail_hppa(csh handle, cs_insn *ins); #endif //CAPSTONE_CSTOOL_CSTOOL_H_ diff --git a/cstool/cstool_hppa.c b/cstool/cstool_hppa.c new file mode 100644 index 0000000000..f41b843180 --- /dev/null +++ b/cstool/cstool_hppa.c @@ -0,0 +1,87 @@ +#include + +#include +#include +#include "cstool.h" +#include "limits.h" + +void print_insn_detail_hppa(csh handle, cs_insn *ins) +{ + cs_hppa *hppa; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + if (ins->detail == NULL) + return; + + hppa = &ins->detail->hppa; + + printf("\top_count: %u\n", hppa->op_count); + for (unsigned i = 0; i < hppa->op_count; i++) { + cs_hppa_op *op = &(hppa->operands[i]); + uint64_t target_addr; + switch (op->type) { + case HPPA_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_IMM: + if (op->imm < 0) + printf("\t\toperands[%u].type: IMM = -0x%" PRIx64 + "\n", + i, -(op->imm)); + else + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 + "\n", + i, op->imm); + break; + case HPPA_OP_IDX_REG: + printf("\t\toperands[%u].type: IDX_REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_DISP: + if (op->imm < 0) + printf("\t\toperands[%u].type: DISP = -0x%" PRIx64 + "\n", + i, -(op->imm)); + else + printf("\t\toperands[%u].type: DISP = 0x%" PRIx64 + "\n", + i, op->imm); + break; + case HPPA_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.space != HPPA_OP_INVALID) { + printf("\t\t\toperands[%u].mem.space: REG = %s\n", + i, cs_reg_name(handle, op->mem.space)); + } + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, + cs_reg_name(handle, op->mem.base)); + break; + case HPPA_OP_TARGET: + printf("\t\toperands[%u].type: ", i); + target_addr = ins->address + op->imm; + printf("TARGET = 0x%" PRIx64 "\n", target_addr); + break; + } + } + + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + printf("\tRegisters read:"); + for (unsigned i = 0; i < regs_read_count; i++) + printf(" %s", + cs_reg_name(handle, regs_read[i])); + printf("\n"); + } + + if (regs_write_count) { + printf("\tRegisters modified:"); + for (unsigned i = 0; i < regs_write_count; i++) + printf(" %s", + cs_reg_name(handle, regs_write[i])); + printf("\n"); + } + } +} \ No newline at end of file diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h index a73137542f..4fed66ef08 100644 --- a/include/capstone/capstone.h +++ b/include/capstone/capstone.h @@ -151,6 +151,7 @@ typedef enum cs_arch { CS_ARCH_SH, ///< SH architecture CS_ARCH_TRICORE, ///< TriCore architecture CS_ARCH_ALPHA, ///< Alpha architecture + CS_ARCH_HPPA, ///< HPPA architecture CS_ARCH_MAX, CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support() } cs_arch; @@ -230,6 +231,9 @@ typedef enum cs_mode { CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6 CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1 CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2 + CS_MODE_HPPA_11 = 1 << 1, ///< HPPA 1.1 + CS_MODE_HPPA_20 = 1 << 2, ///< HPPA 2.0 + CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3), ///< HPPA 2.0 wide } cs_mode; typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size); @@ -372,6 +376,7 @@ typedef struct cs_opt_skipdata { #include "sh.h" #include "tricore.h" #include "alpha.h" +#include "hppa.h" #define MAX_IMPL_W_REGS 47 #define MAX_IMPL_R_REGS 20 @@ -417,6 +422,7 @@ typedef struct cs_detail { cs_sh sh; ///< SH architecture cs_tricore tricore; ///< TriCore architecture cs_alpha alpha; ///< Alpha architecture + cs_hppa hppa; ///< HPPA architecture }; } cs_detail; diff --git a/include/capstone/hppa.h b/include/capstone/hppa.h new file mode 100644 index 0000000000..1fa66be63b --- /dev/null +++ b/include/capstone/hppa.h @@ -0,0 +1,543 @@ +#ifndef CAPSTONE_HPPA_H +#define CAPSTONE_HPPA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "cs_operand.h" +#include "platform.h" + +#define HPPA_MAX_OPS 5 +#define HPPA_STR_MODIFIER_LEN 8 +#define HPPA_MAX_MODIFIERS_LEN 5 + +/// Operand type for instruction's operands +typedef enum hppa_op_type { + HPPA_OP_INVALID = 0, + + HPPA_OP_REG, + HPPA_OP_IMM, + HPPA_OP_IDX_REG, + HPPA_OP_DISP, + HPPA_OP_MEM, + HPPA_OP_TARGET, + +} hppa_op_type; + +//> HPPA registers +typedef enum hppa_reg { + HPPA_REG_INVALID = 0, + + ///> General registers + HPPA_REG_GR0, + HPPA_REG_GR1, + HPPA_REG_GR2, + HPPA_REG_GR3, + HPPA_REG_GR4, + HPPA_REG_GR5, + HPPA_REG_GR6, + HPPA_REG_GR7, + HPPA_REG_GR8, + HPPA_REG_GR9, + HPPA_REG_GR10, + HPPA_REG_GR11, + HPPA_REG_GR12, + HPPA_REG_GR13, + HPPA_REG_GR14, + HPPA_REG_GR15, + HPPA_REG_GR16, + HPPA_REG_GR17, + HPPA_REG_GR18, + HPPA_REG_GR19, + HPPA_REG_GR20, + HPPA_REG_GR21, + HPPA_REG_GR22, + HPPA_REG_GR23, + HPPA_REG_GR24, + HPPA_REG_GR25, + HPPA_REG_GR26, + HPPA_REG_GR27, + HPPA_REG_GR28, + HPPA_REG_GR29, + HPPA_REG_GR30, + HPPA_REG_GR31, + + ///> Floating-point registers + HPPA_REG_FPR0, + HPPA_REG_FPR1, + HPPA_REG_FPR2, + HPPA_REG_FPR3, + HPPA_REG_FPR4, + HPPA_REG_FPR5, + HPPA_REG_FPR6, + HPPA_REG_FPR7, + HPPA_REG_FPR8, + HPPA_REG_FPR9, + HPPA_REG_FPR10, + HPPA_REG_FPR11, + HPPA_REG_FPR12, + HPPA_REG_FPR13, + HPPA_REG_FPR14, + HPPA_REG_FPR15, + HPPA_REG_FPR16, + HPPA_REG_FPR17, + HPPA_REG_FPR18, + HPPA_REG_FPR19, + HPPA_REG_FPR20, + HPPA_REG_FPR21, + HPPA_REG_FPR22, + HPPA_REG_FPR23, + HPPA_REG_FPR24, + HPPA_REG_FPR25, + HPPA_REG_FPR26, + HPPA_REG_FPR27, + HPPA_REG_FPR28, + HPPA_REG_FPR29, + HPPA_REG_FPR30, + HPPA_REG_FPR31, + + ///> Space registers + HPPA_REG_SR0, + HPPA_REG_SR1, + HPPA_REG_SR2, + HPPA_REG_SR3, + HPPA_REG_SR4, + HPPA_REG_SR5, + HPPA_REG_SR6, + HPPA_REG_SR7, + + ///> Control registers + HPPA_REG_CR0, + HPPA_REG_CR1, + HPPA_REG_CR2, + HPPA_REG_CR3, + HPPA_REG_CR4, + HPPA_REG_CR5, + HPPA_REG_CR6, + HPPA_REG_CR7, + HPPA_REG_CR8, + HPPA_REG_CR9, + HPPA_REG_CR10, + HPPA_REG_CR11, + HPPA_REG_CR12, + HPPA_REG_CR13, + HPPA_REG_CR14, + HPPA_REG_CR15, + HPPA_REG_CR16, + HPPA_REG_CR17, + HPPA_REG_CR18, + HPPA_REG_CR19, + HPPA_REG_CR20, + HPPA_REG_CR21, + HPPA_REG_CR22, + HPPA_REG_CR23, + HPPA_REG_CR24, + HPPA_REG_CR25, + HPPA_REG_CR26, + HPPA_REG_CR27, + HPPA_REG_CR28, + HPPA_REG_CR29, + HPPA_REG_CR30, + HPPA_REG_CR31, + + ///> Special floating point exception registers + HPPA_REG_FPE0, + HPPA_REG_FPE1, + HPPA_REG_FPE2, + HPPA_REG_FPE3, + HPPA_REG_FPE4, + HPPA_REG_FPE5, + HPPA_REG_FPE6, + HPPA_REG_FPE7, + HPPA_REG_FPE8, + HPPA_REG_FPE9, + HPPA_REG_FPE10, + HPPA_REG_FPE11, + HPPA_REG_FPE12, + HPPA_REG_FPE13, + HPPA_REG_FPE14, + HPPA_REG_FPE15, + HPPA_REG_FPE16, + HPPA_REG_FPE17, + HPPA_REG_FPE18, + HPPA_REG_FPE19, + HPPA_REG_FPE20, + HPPA_REG_FPE21, + HPPA_REG_FPE22, + HPPA_REG_FPE23, + HPPA_REG_FPE24, + HPPA_REG_FPE25, + HPPA_REG_FPE26, + HPPA_REG_FPE27, + HPPA_REG_FPE28, + HPPA_REG_FPE29, + HPPA_REG_FPE30, + HPPA_REG_FPE31, + + ///> Single-precision floating point registers + HPPA_REG_SP_FPR0, + HPPA_REG_SP_FPR1, + HPPA_REG_SP_FPR2, + HPPA_REG_SP_FPR3, + HPPA_REG_SP_FPR4, + HPPA_REG_SP_FPR5, + HPPA_REG_SP_FPR6, + HPPA_REG_SP_FPR7, + HPPA_REG_SP_FPR8, + HPPA_REG_SP_FPR9, + HPPA_REG_SP_FPR10, + HPPA_REG_SP_FPR11, + HPPA_REG_SP_FPR12, + HPPA_REG_SP_FPR13, + HPPA_REG_SP_FPR14, + HPPA_REG_SP_FPR15, + HPPA_REG_SP_FPR16, + HPPA_REG_SP_FPR17, + HPPA_REG_SP_FPR18, + HPPA_REG_SP_FPR19, + HPPA_REG_SP_FPR20, + HPPA_REG_SP_FPR21, + HPPA_REG_SP_FPR22, + HPPA_REG_SP_FPR23, + HPPA_REG_SP_FPR24, + HPPA_REG_SP_FPR25, + HPPA_REG_SP_FPR26, + HPPA_REG_SP_FPR27, + HPPA_REG_SP_FPR28, + HPPA_REG_SP_FPR29, + HPPA_REG_SP_FPR30, + HPPA_REG_SP_FPR31, + + HPPA_REG_ENDING, +} hppa_reg; + +/// HPPA instruction +typedef enum hppa_insn { + HPPA_INS_INVALID = 0, + + HPPA_INS_ADD, + HPPA_INS_ADDI, + HPPA_INS_ADDIO, + HPPA_INS_ADDIT, + HPPA_INS_ADDITO, + HPPA_INS_ADDB, + HPPA_INS_ADDBT, + HPPA_INS_ADDBF, + HPPA_INS_ADDIB, + HPPA_INS_ADDIBT, + HPPA_INS_ADDIBF, + HPPA_INS_ADDIL, + HPPA_INS_ADDC, + HPPA_INS_ADDCO, + HPPA_INS_ADDL, + HPPA_INS_ADDO, + HPPA_INS_AND, + HPPA_INS_ANDCM, + HPPA_INS_B, + HPPA_INS_BB, + HPPA_INS_BE, + HPPA_INS_BL, + HPPA_INS_BLE, + HPPA_INS_BLR, + HPPA_INS_BREAK, + HPPA_INS_BV, + HPPA_INS_BVB, + HPPA_INS_BVE, + HPPA_INS_CALL, + HPPA_INS_CLDD, + HPPA_INS_CLDDS, + HPPA_INS_CLDDX, + HPPA_INS_CLDW, + HPPA_INS_CLDWS, + HPPA_INS_CLDWX, + HPPA_INS_CLRBTS, + HPPA_INS_CMPB, + HPPA_INS_CMPCLR, + HPPA_INS_CMPIB, + HPPA_INS_CMPICLR, + HPPA_INS_COMB, + HPPA_INS_COMBT, + HPPA_INS_COMBF, + HPPA_INS_COMCLR, + HPPA_INS_COMIB, + HPPA_INS_COMIBT, + HPPA_INS_COMIBF, + HPPA_INS_COMICLR, + HPPA_INS_COPR, + HPPA_INS_COPY, + HPPA_INS_CSTD, + HPPA_INS_CSTDS, + HPPA_INS_CSTDX, + HPPA_INS_CSTW, + HPPA_INS_CSTWS, + HPPA_INS_CSTWX, + HPPA_INS_DCOR, + HPPA_INS_DEP, + HPPA_INS_DEPI, + HPPA_INS_DEPD, + HPPA_INS_DEPDI, + HPPA_INS_DEPW, + HPPA_INS_DEPWI, + HPPA_INS_DIAG, + HPPA_INS_DS, + HPPA_INS_EXTRD, + HPPA_INS_EXTRS, + HPPA_INS_EXTRU, + HPPA_INS_EXTRW, + HPPA_INS_FABS, + HPPA_INS_FADD, + HPPA_INS_FCMP, + HPPA_INS_FCNV, + HPPA_INS_FCNVFF, + HPPA_INS_FCNVFX, + HPPA_INS_FCNVFXT, + HPPA_INS_FCNVXF, + HPPA_INS_FCPY, + HPPA_INS_FDC, + HPPA_INS_FDCE, + HPPA_INS_FDIV, + HPPA_INS_FIC, + HPPA_INS_FICE, + HPPA_INS_FID, + HPPA_INS_FLDD, + HPPA_INS_FLDDS, + HPPA_INS_FLDDX, + HPPA_INS_FLDW, + HPPA_INS_FLDWS, + HPPA_INS_FLDWX, + HPPA_INS_FMPY, + HPPA_INS_FMPYADD, + HPPA_INS_FMPYFADD, + HPPA_INS_FMPYNFADD, + HPPA_INS_FMPYSUB, + HPPA_INS_FNEG, + HPPA_INS_FNEGABS, + HPPA_INS_FREM, + HPPA_INS_FRND, + HPPA_INS_FSQRT, + HPPA_INS_FSTD, + HPPA_INS_FSTDS, + HPPA_INS_FSTDX, + HPPA_INS_FSTW, + HPPA_INS_FSTWS, + HPPA_INS_FSTWX, + HPPA_INS_FSTQS, + HPPA_INS_FSTQX, + HPPA_INS_FSUB, + HPPA_INS_FTEST, + HPPA_INS_GATE, + HPPA_INS_GFR, + HPPA_INS_GFW, + HPPA_INS_GRSHDW, + HPPA_INS_HADD, + HPPA_INS_HAVG, + HPPA_INS_HSHL, + HPPA_INS_HSHLADD, + HPPA_INS_HSHR, + HPPA_INS_HSHRADD, + HPPA_INS_HSUB, + HPPA_INS_IDTLBA, + HPPA_INS_IDTLBP, + HPPA_INS_IDTLBT, + HPPA_INS_IDCOR, + HPPA_INS_IITLBA, + HPPA_INS_IITLBP, + HPPA_INS_IITLBT, + HPPA_INS_LCI, + HPPA_INS_LDB, + HPPA_INS_LDBS, + HPPA_INS_LDBX, + HPPA_INS_LDCD, + HPPA_INS_LDCW, + HPPA_INS_LDCWS, + HPPA_INS_LDCWX, + HPPA_INS_LDD, + HPPA_INS_LDDA, + HPPA_INS_LDH, + HPPA_INS_LDHS, + HPPA_INS_LDHX, + HPPA_INS_LDI, + HPPA_INS_LDIL, + HPPA_INS_LDO, + HPPA_INS_LDSID, + HPPA_INS_LDW, + HPPA_INS_LDWA, + HPPA_INS_LDWAS, + HPPA_INS_LDWAX, + HPPA_INS_LDWM, + HPPA_INS_LDWS, + HPPA_INS_LDWX, + HPPA_INS_LPA, + HPPA_INS_MFCPU, + HPPA_INS_MFCTL, + HPPA_INS_MFIA, + HPPA_INS_MFSP, + HPPA_INS_MIXH, + HPPA_INS_MIXW, + HPPA_INS_MOVB, + HPPA_INS_MOVIB, + HPPA_INS_MTCPU, + HPPA_INS_MTCTL, + HPPA_INS_MTSAR, + HPPA_INS_MTSARCM, + HPPA_INS_MTSM, + HPPA_INS_MTSP, + HPPA_INS_NOP, + HPPA_INS_OR, + HPPA_INS_PDC, + HPPA_INS_PDTLB, + HPPA_INS_PDTLBE, + HPPA_INS_PERMH, + HPPA_INS_PITLB, + HPPA_INS_PITLBE, + HPPA_INS_PMDIS, + HPPA_INS_PMENB, + HPPA_INS_POPBTS, + HPPA_INS_PROBE, + HPPA_INS_PROBEI, + HPPA_INS_PROBER, + HPPA_INS_PROBERI, + HPPA_INS_PROBEW, + HPPA_INS_PROBEWI, + HPPA_INS_PUSHBTS, + HPPA_INS_PUSHNOM, + HPPA_INS_RET, + HPPA_INS_RFI, + HPPA_INS_RFIR, + HPPA_INS_RSM, + HPPA_INS_SHDWGR, + HPPA_INS_SHLADD, + HPPA_INS_SH1ADD, + HPPA_INS_SH1ADDL, + HPPA_INS_SH1ADDO, + HPPA_INS_SH2ADD, + HPPA_INS_SH2ADDL, + HPPA_INS_SH2ADDO, + HPPA_INS_SH3ADD, + HPPA_INS_SH3ADDL, + HPPA_INS_SH3ADDO, + HPPA_INS_SHD, + HPPA_INS_SHRPD, + HPPA_INS_SHRPW, + HPPA_INS_SPOP0, + HPPA_INS_SPOP1, + HPPA_INS_SPOP2, + HPPA_INS_SPOP3, + HPPA_INS_SSM, + HPPA_INS_STB, + HPPA_INS_STBS, + HPPA_INS_STBY, + HPPA_INS_STBYS, + HPPA_INS_STD, + HPPA_INS_STDA, + HPPA_INS_STDBY, + HPPA_INS_STH, + HPPA_INS_STHS, + HPPA_INS_STW, + HPPA_INS_STWA, + HPPA_INS_STWAS, + HPPA_INS_STWS, + HPPA_INS_STWM, + HPPA_INS_SUB, + HPPA_INS_SUBB, + HPPA_INS_SUBBO, + HPPA_INS_SUBI, + HPPA_INS_SUBIO, + HPPA_INS_SUBO, + HPPA_INS_SUBT, + HPPA_INS_SUBTO, + HPPA_INS_SYNC, + HPPA_INS_SYNCDMA, + HPPA_INS_TOCDIS, + HPPA_INS_TOCEN, + HPPA_INS_UADDCM, + HPPA_INS_UADDCMT, + HPPA_INS_UXOR, + HPPA_INS_VDEP, + HPPA_INS_VDEPI, + HPPA_INS_VEXTRS, + HPPA_INS_VEXTRU, + HPPA_INS_VSHD, + HPPA_INS_XMPYU, + HPPA_INS_XOR, + HPPA_INS_ZDEP, + HPPA_INS_ZDEPI, + HPPA_INS_ZVDEP, + HPPA_INS_ZVDEPI, + + HPPA_INS_ENDING +} hppa_insn; + +/// HPPA space select operand +typedef struct hppa_mem { + hppa_reg base; + hppa_reg space; + cs_ac_type base_access; +} hppa_mem; + +// Instruction operand +typedef struct cs_hppa_op { + hppa_op_type type; ///< operand type + union { + hppa_reg reg; ///< register value for REG operand + int64_t imm; ///< immediate value for IMM operand + hppa_mem mem; + }; + cs_ac_type access; +} cs_hppa_op; + +// Instruction structure +typedef struct cs_hppa { + // Number of operands of this instruction, + // or 0 when instruction has no operand. + uint8_t op_count; + cs_hppa_op operands[HPPA_MAX_OPS]; ///< operands for hppa instruction. +} cs_hppa; + +/// HPPA modifiers type. Can be string (most of them) or int (uid, sop) +typedef enum hppa_modifier_type { + HPPA_MOD_STR = 0, + HPPA_MOD_INT = 1 +} hppa_modifier_type; + +/// hppa string/integer modifier +typedef struct hppa_modifier { + hppa_modifier_type type; + union { + char str_mod[HPPA_STR_MODIFIER_LEN]; + uint32_t int_mod; + }; + +} hppa_modifier; + +// Additional instruction info +typedef struct hppa_ext { + hppa_modifier modifiers[HPPA_MAX_MODIFIERS_LEN]; ///< instruction modifiers array + uint8_t mod_num; ///< number of modifiers of current instruction + bool b_writeble; ///< true if some load/store modifier has modify base register bit + bool is_alternative; ///< true if some modifier affects instruction format +} hppa_ext; + +// Group of HPPA instructions +typedef enum hppa_insn_group { + HPPA_GRP_INVALID = 0, ///< = CS_GRP_INVALID + + HPPA_GRP_COMPUTATION = 128, + HPPA_GRP_MULTIMEDIA, + HPPA_GRP_MEM_REF, + HPPA_GRP_LONG_IMM, + HPPA_GRP_BRANCH, + HPPA_GRP_SYSCTRL, + HPPA_GRP_ASSIST, + HPPA_GRP_FLOAT, + HPPA_GRP_PERFMON, + + HPPA_GRP_ENDING, +} hppa_insn_group; + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/nmake.bat b/nmake.bat index 0f03bce883..42d64158d9 100644 --- a/nmake.bat +++ b/nmake.bat @@ -23,6 +23,7 @@ if "%1"=="WASM" set %arch%=WASM if "%1"=="BPF" set %arch%=BPF if "%1"=="RISCV" set %arch%=RISCV if "%1"=="ALPHA" set %arch%=ALPHA +if "%1"=="HPPA" set %arch%=HPPA if not "%arch%"=="" set flags=%flags% and " -DCAPSTONE_ARCHITECTURE_DEFAULT=OFF -DCAPSTONE_%arch%_SUPPORT=ON" diff --git a/suite/MC/HPPA/alu11.s.cs b/suite/MC/HPPA/alu11.s.cs new file mode 100644 index 0000000000..2eee717ec6 --- /dev/null +++ b/suite/MC/HPPA/alu11.s.cs @@ -0,0 +1,433 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x08,0x41,0x06,0x03 = add r1,rp,r3 +0x08,0x41,0x26,0x03 = add,= r1,rp,r3 +0x08,0x41,0x46,0x03 = add,< r1,rp,r3 +0x08,0x41,0x66,0x03 = add,<= r1,rp,r3 +0x08,0x41,0x86,0x03 = add,nuv r1,rp,r3 +0x08,0x41,0xa6,0x03 = add,znv r1,rp,r3 +0x08,0x41,0xc6,0x03 = add,sv r1,rp,r3 +0x08,0x41,0xe6,0x03 = add,od r1,rp,r3 +0x08,0x41,0x16,0x03 = add,tr r1,rp,r3 +0x08,0x41,0x36,0x03 = add,<> r1,rp,r3 +0x08,0x41,0x56,0x03 = add,>= r1,rp,r3 +0x08,0x41,0x76,0x03 = add,> r1,rp,r3 +0x08,0x41,0x96,0x03 = add,uv r1,rp,r3 +0x08,0x41,0xb6,0x03 = add,vnz r1,rp,r3 +0x08,0x41,0xd6,0x03 = add,nsv r1,rp,r3 +0x08,0x41,0xf6,0x03 = add,ev r1,rp,r3 +0x08,0x41,0x0e,0x03 = addo r1,rp,r3 +0x08,0x41,0x2e,0x03 = addo,= r1,rp,r3 +0x08,0x41,0x4e,0x03 = addo,< r1,rp,r3 +0x08,0x41,0x6e,0x03 = addo,<= r1,rp,r3 +0x08,0x41,0x8e,0x03 = addo,nuv r1,rp,r3 +0x08,0x41,0xae,0x03 = addo,znv r1,rp,r3 +0x08,0x41,0xce,0x03 = addo,sv r1,rp,r3 +0x08,0x41,0xee,0x03 = addo,od r1,rp,r3 +0x08,0x41,0x1e,0x03 = addo,tr r1,rp,r3 +0x08,0x41,0x3e,0x03 = addo,<> r1,rp,r3 +0x08,0x41,0x5e,0x03 = addo,>= r1,rp,r3 +0x08,0x41,0x7e,0x03 = addo,> r1,rp,r3 +0x08,0x41,0x9e,0x03 = addo,uv r1,rp,r3 +0x08,0x41,0xbe,0x03 = addo,vnz r1,rp,r3 +0x08,0x41,0xde,0x03 = addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0x03 = addo,ev r1,rp,r3 +0x08,0x41,0x07,0x03 = addc r1,rp,r3 +0x08,0x41,0x27,0x03 = addc,= r1,rp,r3 +0x08,0x41,0x47,0x03 = addc,< r1,rp,r3 +0x08,0x41,0x67,0x03 = addc,<= r1,rp,r3 +0x08,0x41,0x87,0x03 = addc,nuv r1,rp,r3 +0x08,0x41,0xa7,0x03 = addc,znv r1,rp,r3 +0x08,0x41,0xc7,0x03 = addc,sv r1,rp,r3 +0x08,0x41,0xe7,0x03 = addc,od r1,rp,r3 +0x08,0x41,0x17,0x03 = addc,tr r1,rp,r3 +0x08,0x41,0x37,0x03 = addc,<> r1,rp,r3 +0x08,0x41,0x57,0x03 = addc,>= r1,rp,r3 +0x08,0x41,0x77,0x03 = addc,> r1,rp,r3 +0x08,0x41,0x97,0x03 = addc,uv r1,rp,r3 +0x08,0x41,0xb7,0x03 = addc,vnz r1,rp,r3 +0x08,0x41,0xd7,0x03 = addc,nsv r1,rp,r3 +0x08,0x41,0xf7,0x03 = addc,ev r1,rp,r3 +0x08,0x41,0x0f,0x03 = addco r1,rp,r3 +0x08,0x41,0x2f,0x03 = addco,= r1,rp,r3 +0x08,0x41,0x4f,0x03 = addco,< r1,rp,r3 +0x08,0x41,0x6f,0x03 = addco,<= r1,rp,r3 +0x08,0x41,0x8f,0x03 = addco,nuv r1,rp,r3 +0x08,0x41,0xaf,0x03 = addco,znv r1,rp,r3 +0x08,0x41,0xcf,0x03 = addco,sv r1,rp,r3 +0x08,0x41,0xef,0x03 = addco,od r1,rp,r3 +0x08,0x41,0x1f,0x03 = addco,tr r1,rp,r3 +0x08,0x41,0x3f,0x03 = addco,<> r1,rp,r3 +0x08,0x41,0x5f,0x03 = addco,>= r1,rp,r3 +0x08,0x41,0x7f,0x03 = addco,> r1,rp,r3 +0x08,0x41,0x9f,0x03 = addco,uv r1,rp,r3 +0x08,0x41,0xbf,0x03 = addco,vnz r1,rp,r3 +0x08,0x41,0xdf,0x03 = addco,nsv r1,rp,r3 +0x08,0x41,0xff,0x03 = addco,ev r1,rp,r3 +0x08,0x41,0x06,0x43 = sh1add r1,rp,r3 +0x08,0x41,0x26,0x43 = sh1add,= r1,rp,r3 +0x08,0x41,0x46,0x43 = sh1add,< r1,rp,r3 +0x08,0x41,0x66,0x43 = sh1add,<= r1,rp,r3 +0x08,0x41,0x86,0x43 = sh1add,nuv r1,rp,r3 +0x08,0x41,0xa6,0x43 = sh1add,znv r1,rp,r3 +0x08,0x41,0xc6,0x43 = sh1add,sv r1,rp,r3 +0x08,0x41,0xe6,0x43 = sh1add,od r1,rp,r3 +0x08,0x41,0x16,0x43 = sh1add,tr r1,rp,r3 +0x08,0x41,0x36,0x43 = sh1add,<> r1,rp,r3 +0x08,0x41,0x56,0x43 = sh1add,>= r1,rp,r3 +0x08,0x41,0x76,0x43 = sh1add,> r1,rp,r3 +0x08,0x41,0x96,0x43 = sh1add,uv r1,rp,r3 +0x08,0x41,0xb6,0x43 = sh1add,vnz r1,rp,r3 +0x08,0x41,0xd6,0x43 = sh1add,nsv r1,rp,r3 +0x08,0x41,0xf6,0x43 = sh1add,ev r1,rp,r3 +0x08,0x41,0x0e,0x43 = sh1addo r1,rp,r3 +0x08,0x41,0x2e,0x43 = sh1addo,= r1,rp,r3 +0x08,0x41,0x4e,0x43 = sh1addo,< r1,rp,r3 +0x08,0x41,0x6e,0x43 = sh1addo,<= r1,rp,r3 +0x08,0x41,0x8e,0x43 = sh1addo,nuv r1,rp,r3 +0x08,0x41,0xae,0x43 = sh1addo,znv r1,rp,r3 +0x08,0x41,0xce,0x43 = sh1addo,sv r1,rp,r3 +0x08,0x41,0xee,0x43 = sh1addo,od r1,rp,r3 +0x08,0x41,0x1e,0x43 = sh1addo,tr r1,rp,r3 +0x08,0x41,0x3e,0x43 = sh1addo,<> r1,rp,r3 +0x08,0x41,0x5e,0x43 = sh1addo,>= r1,rp,r3 +0x08,0x41,0x7e,0x43 = sh1addo,> r1,rp,r3 +0x08,0x41,0x9e,0x43 = sh1addo,uv r1,rp,r3 +0x08,0x41,0xbe,0x43 = sh1addo,vnz r1,rp,r3 +0x08,0x41,0xde,0x43 = sh1addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0x43 = sh1addo,ev r1,rp,r3 +0x08,0x41,0x06,0x83 = sh2add r1,rp,r3 +0x08,0x41,0x26,0x83 = sh2add,= r1,rp,r3 +0x08,0x41,0x46,0x83 = sh2add,< r1,rp,r3 +0x08,0x41,0x66,0x83 = sh2add,<= r1,rp,r3 +0x08,0x41,0x86,0x83 = sh2add,nuv r1,rp,r3 +0x08,0x41,0xa6,0x83 = sh2add,znv r1,rp,r3 +0x08,0x41,0xc6,0x83 = sh2add,sv r1,rp,r3 +0x08,0x41,0xe6,0x83 = sh2add,od r1,rp,r3 +0x08,0x41,0x16,0x83 = sh2add,tr r1,rp,r3 +0x08,0x41,0x36,0x83 = sh2add,<> r1,rp,r3 +0x08,0x41,0x56,0x83 = sh2add,>= r1,rp,r3 +0x08,0x41,0x76,0x83 = sh2add,> r1,rp,r3 +0x08,0x41,0x96,0x83 = sh2add,uv r1,rp,r3 +0x08,0x41,0xb6,0x83 = sh2add,vnz r1,rp,r3 +0x08,0x41,0xd6,0x83 = sh2add,nsv r1,rp,r3 +0x08,0x41,0xf6,0x83 = sh2add,ev r1,rp,r3 +0x08,0x41,0x0e,0x83 = sh2addo r1,rp,r3 +0x08,0x41,0x2e,0x83 = sh2addo,= r1,rp,r3 +0x08,0x41,0x4e,0x83 = sh2addo,< r1,rp,r3 +0x08,0x41,0x6e,0x83 = sh2addo,<= r1,rp,r3 +0x08,0x41,0x8e,0x83 = sh2addo,nuv r1,rp,r3 +0x08,0x41,0xae,0x83 = sh2addo,znv r1,rp,r3 +0x08,0x41,0xce,0x83 = sh2addo,sv r1,rp,r3 +0x08,0x41,0xee,0x83 = sh2addo,od r1,rp,r3 +0x08,0x41,0x1e,0x83 = sh2addo,tr r1,rp,r3 +0x08,0x41,0x3e,0x83 = sh2addo,<> r1,rp,r3 +0x08,0x41,0x5e,0x83 = sh2addo,>= r1,rp,r3 +0x08,0x41,0x7e,0x83 = sh2addo,> r1,rp,r3 +0x08,0x41,0x9e,0x83 = sh2addo,uv r1,rp,r3 +0x08,0x41,0xbe,0x83 = sh2addo,vnz r1,rp,r3 +0x08,0x41,0xde,0x83 = sh2addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0x83 = sh2addo,ev r1,rp,r3 +0x08,0x41,0x06,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x26,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x46,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x66,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x86,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xa6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xc6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xe6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x16,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x36,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x56,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x76,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x96,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xb6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xd6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0xf6,0xc3 = sh3add r1,rp,r3 +0x08,0x41,0x0e,0xc3 = sh3addo r1,rp,r3 +0x08,0x41,0x2e,0xc3 = sh3addo,= r1,rp,r3 +0x08,0x41,0x4e,0xc3 = sh3addo,< r1,rp,r3 +0x08,0x41,0x6e,0xc3 = sh3addo,<= r1,rp,r3 +0x08,0x41,0x8e,0xc3 = sh3addo,nuv r1,rp,r3 +0x08,0x41,0xae,0xc3 = sh3addo,znv r1,rp,r3 +0x08,0x41,0xce,0xc3 = sh3addo,sv r1,rp,r3 +0x08,0x41,0xee,0xc3 = sh3addo,od r1,rp,r3 +0x08,0x41,0x1e,0xc3 = sh3addo,tr r1,rp,r3 +0x08,0x41,0x3e,0xc3 = sh3addo,<> r1,rp,r3 +0x08,0x41,0x5e,0xc3 = sh3addo,>= r1,rp,r3 +0x08,0x41,0x7e,0xc3 = sh3addo,> r1,rp,r3 +0x08,0x41,0x9e,0xc3 = sh3addo,uv r1,rp,r3 +0x08,0x41,0xbe,0xc3 = sh3addo,vnz r1,rp,r3 +0x08,0x41,0xde,0xc3 = sh3addo,nsv r1,rp,r3 +0x08,0x41,0xfe,0xc3 = sh3addo,ev r1,rp,r3 +0x08,0x41,0x04,0x03 = sub r1,rp,r3 +0x08,0x41,0x24,0x03 = sub,= r1,rp,r3 +0x08,0x41,0x44,0x03 = sub,< r1,rp,r3 +0x08,0x41,0x64,0x03 = sub,<= r1,rp,r3 +0x08,0x41,0x84,0x03 = sub,<< r1,rp,r3 +0x08,0x41,0xa4,0x03 = sub,<<= r1,rp,r3 +0x08,0x41,0xc4,0x03 = sub,sv r1,rp,r3 +0x08,0x41,0xe4,0x03 = sub,od r1,rp,r3 +0x08,0x41,0x14,0x03 = sub,tr r1,rp,r3 +0x08,0x41,0x34,0x03 = sub,<> r1,rp,r3 +0x08,0x41,0x54,0x03 = sub,>= r1,rp,r3 +0x08,0x41,0x74,0x03 = sub,> r1,rp,r3 +0x08,0x41,0x94,0x03 = sub,>>= r1,rp,r3 +0x08,0x41,0xb4,0x03 = sub,>> r1,rp,r3 +0x08,0x41,0xd4,0x03 = sub,nsv r1,rp,r3 +0x08,0x41,0xf4,0x03 = sub,ev r1,rp,r3 +0x08,0x41,0x0c,0x03 = subo r1,rp,r3 +0x08,0x41,0x2c,0x03 = subo,= r1,rp,r3 +0x08,0x41,0x4c,0x03 = subo,< r1,rp,r3 +0x08,0x41,0x6c,0x03 = subo,<= r1,rp,r3 +0x08,0x41,0x8c,0x03 = subo,<< r1,rp,r3 +0x08,0x41,0xac,0x03 = subo,<<= r1,rp,r3 +0x08,0x41,0xcc,0x03 = subo,sv r1,rp,r3 +0x08,0x41,0xec,0x03 = subo,od r1,rp,r3 +0x08,0x41,0x1c,0x03 = subo,tr r1,rp,r3 +0x08,0x41,0x3c,0x03 = subo,<> r1,rp,r3 +0x08,0x41,0x5c,0x03 = subo,>= r1,rp,r3 +0x08,0x41,0x7c,0x03 = subo,> r1,rp,r3 +0x08,0x41,0x9c,0x03 = subo,>>= r1,rp,r3 +0x08,0x41,0xbc,0x03 = subo,>> r1,rp,r3 +0x08,0x41,0xdc,0x03 = subo,nsv r1,rp,r3 +0x08,0x41,0xfc,0x03 = subo,ev r1,rp,r3 +0x08,0x41,0x04,0xc3 = subt r1,rp,r3 +0x08,0x41,0x24,0xc3 = subt,= r1,rp,r3 +0x08,0x41,0x44,0xc3 = subt,< r1,rp,r3 +0x08,0x41,0x64,0xc3 = subt,<= r1,rp,r3 +0x08,0x41,0x84,0xc3 = subt,<< r1,rp,r3 +0x08,0x41,0xa4,0xc3 = subt,<<= r1,rp,r3 +0x08,0x41,0xc4,0xc3 = subt,sv r1,rp,r3 +0x08,0x41,0xe4,0xc3 = subt,od r1,rp,r3 +0x08,0x41,0x14,0xc3 = subt,tr r1,rp,r3 +0x08,0x41,0x34,0xc3 = subt,<> r1,rp,r3 +0x08,0x41,0x54,0xc3 = subt,>= r1,rp,r3 +0x08,0x41,0x74,0xc3 = subt,> r1,rp,r3 +0x08,0x41,0x94,0xc3 = subt,>>= r1,rp,r3 +0x08,0x41,0xb4,0xc3 = subt,>> r1,rp,r3 +0x08,0x41,0xd4,0xc3 = subt,nsv r1,rp,r3 +0x08,0x41,0xf4,0xc3 = subt,ev r1,rp,r3 +0x08,0x41,0x0c,0xc3 = subto r1,rp,r3 +0x08,0x41,0x2c,0xc3 = subto,= r1,rp,r3 +0x08,0x41,0x4c,0xc3 = subto,< r1,rp,r3 +0x08,0x41,0x6c,0xc3 = subto,<= r1,rp,r3 +0x08,0x41,0x8c,0xc3 = subto,<< r1,rp,r3 +0x08,0x41,0xac,0xc3 = subto,<<= r1,rp,r3 +0x08,0x41,0xcc,0xc3 = subto,sv r1,rp,r3 +0x08,0x41,0xec,0xc3 = subto,od r1,rp,r3 +0x08,0x41,0x1c,0xc3 = subto,tr r1,rp,r3 +0x08,0x41,0x3c,0xc3 = subto,<> r1,rp,r3 +0x08,0x41,0x5c,0xc3 = subto,>= r1,rp,r3 +0x08,0x41,0x7c,0xc3 = subto,> r1,rp,r3 +0x08,0x41,0x9c,0xc3 = subto,>>= r1,rp,r3 +0x08,0x41,0xbc,0xc3 = subto,>> r1,rp,r3 +0x08,0x41,0xdc,0xc3 = subto,nsv r1,rp,r3 +0x08,0x41,0xfc,0xc3 = subto,ev r1,rp,r3 +0x08,0x41,0x05,0x03 = subb r1,rp,r3 +0x08,0x41,0x25,0x03 = subb,= r1,rp,r3 +0x08,0x41,0x45,0x03 = subb,< r1,rp,r3 +0x08,0x41,0x65,0x03 = subb,<= r1,rp,r3 +0x08,0x41,0x85,0x03 = subb,<< r1,rp,r3 +0x08,0x41,0xa5,0x03 = subb,<<= r1,rp,r3 +0x08,0x41,0xc5,0x03 = subb,sv r1,rp,r3 +0x08,0x41,0xe5,0x03 = subb,od r1,rp,r3 +0x08,0x41,0x15,0x03 = subb,tr r1,rp,r3 +0x08,0x41,0x35,0x03 = subb,<> r1,rp,r3 +0x08,0x41,0x55,0x03 = subb,>= r1,rp,r3 +0x08,0x41,0x75,0x03 = subb,> r1,rp,r3 +0x08,0x41,0x95,0x03 = subb,>>= r1,rp,r3 +0x08,0x41,0xb5,0x03 = subb,>> r1,rp,r3 +0x08,0x41,0xd5,0x03 = subb,nsv r1,rp,r3 +0x08,0x41,0xf5,0x03 = subb,ev r1,rp,r3 +0x08,0x41,0x0d,0x03 = subbo r1,rp,r3 +0x08,0x41,0x2d,0x03 = subbo,= r1,rp,r3 +0x08,0x41,0x4d,0x03 = subbo,< r1,rp,r3 +0x08,0x41,0x6d,0x03 = subbo,<= r1,rp,r3 +0x08,0x41,0x8d,0x03 = subbo,<< r1,rp,r3 +0x08,0x41,0xad,0x03 = subbo,<<= r1,rp,r3 +0x08,0x41,0xcd,0x03 = subbo,sv r1,rp,r3 +0x08,0x41,0xed,0x03 = subbo,od r1,rp,r3 +0x08,0x41,0x1d,0x03 = subbo,tr r1,rp,r3 +0x08,0x41,0x3d,0x03 = subbo,<> r1,rp,r3 +0x08,0x41,0x5d,0x03 = subbo,>= r1,rp,r3 +0x08,0x41,0x7d,0x03 = subbo,> r1,rp,r3 +0x08,0x41,0x9d,0x03 = subbo,>>= r1,rp,r3 +0x08,0x41,0xbd,0x03 = subbo,>> r1,rp,r3 +0x08,0x41,0xdd,0x03 = subbo,nsv r1,rp,r3 +0x08,0x41,0xfd,0x03 = subbo,ev r1,rp,r3 +0x08,0x41,0x04,0x43 = ds r1,rp,r3 +0x08,0x41,0x24,0x43 = ds,= r1,rp,r3 +0x08,0x41,0x44,0x43 = ds,< r1,rp,r3 +0x08,0x41,0x64,0x43 = ds,<= r1,rp,r3 +0x08,0x41,0x84,0x43 = ds,<< r1,rp,r3 +0x08,0x41,0xa4,0x43 = ds,<<= r1,rp,r3 +0x08,0x41,0xc4,0x43 = ds,sv r1,rp,r3 +0x08,0x41,0xe4,0x43 = ds,od r1,rp,r3 +0x08,0x41,0x14,0x43 = ds,tr r1,rp,r3 +0x08,0x41,0x34,0x43 = ds,<> r1,rp,r3 +0x08,0x41,0x54,0x43 = ds,>= r1,rp,r3 +0x08,0x41,0x74,0x43 = ds,> r1,rp,r3 +0x08,0x41,0x94,0x43 = ds,>>= r1,rp,r3 +0x08,0x41,0xb4,0x43 = ds,>> r1,rp,r3 +0x08,0x41,0xd4,0x43 = ds,nsv r1,rp,r3 +0x08,0x41,0xf4,0x43 = ds,ev r1,rp,r3 +0x08,0x41,0x00,0x03 = andcm r1,rp,r3 +0x08,0x41,0x20,0x03 = andcm,= r1,rp,r3 +0x08,0x41,0x40,0x03 = andcm,< r1,rp,r3 +0x08,0x41,0x60,0x03 = andcm,<= r1,rp,r3 +0x08,0x41,0xe0,0x03 = andcm,od r1,rp,r3 +0x08,0x41,0x10,0x03 = andcm,tr r1,rp,r3 +0x08,0x41,0x30,0x03 = andcm,<> r1,rp,r3 +0x08,0x41,0x50,0x03 = andcm,>= r1,rp,r3 +0x08,0x41,0x70,0x03 = andcm,> r1,rp,r3 +0x08,0x41,0xf0,0x03 = andcm,ev r1,rp,r3 +0x08,0x41,0x02,0x03 = and r1,rp,r3 +0x08,0x41,0x22,0x03 = and,= r1,rp,r3 +0x08,0x41,0x42,0x03 = and,< r1,rp,r3 +0x08,0x41,0x62,0x03 = and,<= r1,rp,r3 +0x08,0x41,0xe2,0x03 = and,od r1,rp,r3 +0x08,0x41,0x12,0x03 = and,tr r1,rp,r3 +0x08,0x41,0x32,0x03 = and,<> r1,rp,r3 +0x08,0x41,0x52,0x03 = and,>= r1,rp,r3 +0x08,0x41,0x72,0x03 = and,> r1,rp,r3 +0x08,0x41,0xf2,0x03 = and,ev r1,rp,r3 +0x08,0x41,0x02,0x43 = or r1,rp,r3 +0x08,0x41,0x22,0x43 = or,= r1,rp,r3 +0x08,0x41,0x42,0x43 = or,< r1,rp,r3 +0x08,0x41,0x62,0x43 = or,<= r1,rp,r3 +0x08,0x41,0xe2,0x43 = or,od r1,rp,r3 +0x08,0x41,0x12,0x43 = or,tr r1,rp,r3 +0x08,0x41,0x32,0x43 = or,<> r1,rp,r3 +0x08,0x41,0x52,0x43 = or,>= r1,rp,r3 +0x08,0x41,0x72,0x43 = or,> r1,rp,r3 +0x08,0x41,0xf2,0x43 = or,ev r1,rp,r3 +0x08,0x41,0x02,0x83 = xor r1,rp,r3 +0x08,0x41,0x22,0x83 = xor,= r1,rp,r3 +0x08,0x41,0x42,0x83 = xor,< r1,rp,r3 +0x08,0x41,0x62,0x83 = xor,<= r1,rp,r3 +0x08,0x41,0xe2,0x83 = xor,od r1,rp,r3 +0x08,0x41,0x12,0x83 = xor,tr r1,rp,r3 +0x08,0x41,0x32,0x83 = xor,<> r1,rp,r3 +0x08,0x41,0x52,0x83 = xor,>= r1,rp,r3 +0x08,0x41,0x72,0x83 = xor,> r1,rp,r3 +0x08,0x41,0xf2,0x83 = xor,ev r1,rp,r3 +0x08,0x41,0x03,0x83 = uxor r1,rp,r3 +0x08,0x41,0x23,0x83 = uxor,swz r1,rp,r3 +0x08,0x41,0x43,0x83 = uxor,sbz r1,rp,r3 +0x08,0x41,0x63,0x83 = uxor,shz r1,rp,r3 +0x08,0x41,0x13,0x83 = uxor,tr r1,rp,r3 +0x08,0x41,0x33,0x83 = uxor,nwz r1,rp,r3 +0x08,0x41,0x53,0x83 = uxor,nbz r1,rp,r3 +0x08,0x41,0x73,0x83 = uxor,nhz r1,rp,r3 +0x08,0x41,0x08,0x83 = comclr r1,rp,r3 +0x08,0x41,0x28,0x83 = comclr,= r1,rp,r3 +0x08,0x41,0x48,0x83 = comclr,< r1,rp,r3 +0x08,0x41,0x68,0x83 = comclr,<= r1,rp,r3 +0x08,0x41,0x88,0x83 = comclr,<< r1,rp,r3 +0x08,0x41,0xa8,0x83 = comclr,<<= r1,rp,r3 +0x08,0x41,0xc8,0x83 = comclr,sv r1,rp,r3 +0x08,0x41,0xe8,0x83 = comclr,od r1,rp,r3 +0x08,0x41,0x18,0x83 = comclr,tr r1,rp,r3 +0x08,0x41,0x38,0x83 = comclr,<> r1,rp,r3 +0x08,0x41,0x58,0x83 = comclr,>= r1,rp,r3 +0x08,0x41,0x78,0x83 = comclr,> r1,rp,r3 +0x08,0x41,0x98,0x83 = comclr,>>= r1,rp,r3 +0x08,0x41,0xb8,0x83 = comclr,>> r1,rp,r3 +0x08,0x41,0xd8,0x83 = comclr,nsv r1,rp,r3 +0x08,0x41,0xf8,0x83 = comclr,ev r1,rp,r3 +0x08,0x41,0x09,0x83 = uaddcm r1,rp,r3 +0x08,0x41,0x29,0x83 = uaddcm,swz r1,rp,r3 +0x08,0x41,0x49,0x83 = uaddcm,sbz r1,rp,r3 +0x08,0x41,0x69,0x83 = uaddcm,shz r1,rp,r3 +0x08,0x41,0x19,0x83 = uaddcm,tr r1,rp,r3 +0x08,0x41,0x39,0x83 = uaddcm,nwz r1,rp,r3 +0x08,0x41,0x59,0x83 = uaddcm,nbz r1,rp,r3 +0x08,0x41,0x79,0x83 = uaddcm,nhz r1,rp,r3 +0x08,0x41,0x09,0xc3 = uaddcmt r1,rp,r3 +0x08,0x41,0x29,0xc3 = uaddcmt,swz r1,rp,r3 +0x08,0x41,0x49,0xc3 = uaddcmt,sbz r1,rp,r3 +0x08,0x41,0x69,0xc3 = uaddcmt,shz r1,rp,r3 +0x08,0x41,0x19,0xc3 = uaddcmt,tr r1,rp,r3 +0x08,0x41,0x39,0xc3 = uaddcmt,nwz r1,rp,r3 +0x08,0x41,0x59,0xc3 = uaddcmt,nbz r1,rp,r3 +0x08,0x41,0x79,0xc3 = uaddcmt,nhz r1,rp,r3 +0x08,0x41,0x0a,0x03 = addl r1,rp,r3 +0x08,0x41,0x2a,0x03 = addl,= r1,rp,r3 +0x08,0x41,0x4a,0x03 = addl,< r1,rp,r3 +0x08,0x41,0x6a,0x03 = addl,<= r1,rp,r3 +0x08,0x41,0x8a,0x03 = addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0x03 = addl,znv r1,rp,r3 +0x08,0x41,0xca,0x03 = addl,sv r1,rp,r3 +0x08,0x41,0xea,0x03 = addl,od r1,rp,r3 +0x08,0x41,0x1a,0x03 = addl,tr r1,rp,r3 +0x08,0x41,0x3a,0x03 = addl,<> r1,rp,r3 +0x08,0x41,0x5a,0x03 = addl,>= r1,rp,r3 +0x08,0x41,0x7a,0x03 = addl,> r1,rp,r3 +0x08,0x41,0x9a,0x03 = addl,uv r1,rp,r3 +0x08,0x41,0xba,0x03 = addl,vnz r1,rp,r3 +0x08,0x41,0xda,0x03 = addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0x03 = addl,ev r1,rp,r3 +0x08,0x41,0x0a,0x43 = sh1addl r1,rp,r3 +0x08,0x41,0x2a,0x43 = sh1addl,= r1,rp,r3 +0x08,0x41,0x4a,0x43 = sh1addl,< r1,rp,r3 +0x08,0x41,0x6a,0x43 = sh1addl,<= r1,rp,r3 +0x08,0x41,0x8a,0x43 = sh1addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0x43 = sh1addl,znv r1,rp,r3 +0x08,0x41,0xca,0x43 = sh1addl,sv r1,rp,r3 +0x08,0x41,0xea,0x43 = sh1addl,od r1,rp,r3 +0x08,0x41,0x1a,0x43 = sh1addl,tr r1,rp,r3 +0x08,0x41,0x3a,0x43 = sh1addl,<> r1,rp,r3 +0x08,0x41,0x5a,0x43 = sh1addl,>= r1,rp,r3 +0x08,0x41,0x7a,0x43 = sh1addl,> r1,rp,r3 +0x08,0x41,0x9a,0x43 = sh1addl,uv r1,rp,r3 +0x08,0x41,0xba,0x43 = sh1addl,vnz r1,rp,r3 +0x08,0x41,0xda,0x43 = sh1addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0x43 = sh1addl,ev r1,rp,r3 +0x08,0x41,0x0a,0x83 = sh2addl r1,rp,r3 +0x08,0x41,0x2a,0x83 = sh2addl,= r1,rp,r3 +0x08,0x41,0x4a,0x83 = sh2addl,< r1,rp,r3 +0x08,0x41,0x6a,0x83 = sh2addl,<= r1,rp,r3 +0x08,0x41,0x8a,0x83 = sh2addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0x83 = sh2addl,znv r1,rp,r3 +0x08,0x41,0xca,0x83 = sh2addl,sv r1,rp,r3 +0x08,0x41,0xea,0x83 = sh2addl,od r1,rp,r3 +0x08,0x41,0x1a,0x83 = sh2addl,tr r1,rp,r3 +0x08,0x41,0x3a,0x83 = sh2addl,<> r1,rp,r3 +0x08,0x41,0x5a,0x83 = sh2addl,>= r1,rp,r3 +0x08,0x41,0x7a,0x83 = sh2addl,> r1,rp,r3 +0x08,0x41,0x9a,0x83 = sh2addl,uv r1,rp,r3 +0x08,0x41,0xba,0x83 = sh2addl,vnz r1,rp,r3 +0x08,0x41,0xda,0x83 = sh2addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0x83 = sh2addl,ev r1,rp,r3 +0x08,0x41,0x0a,0xc3 = sh3addl r1,rp,r3 +0x08,0x41,0x2a,0xc3 = sh3addl,= r1,rp,r3 +0x08,0x41,0x4a,0xc3 = sh3addl,< r1,rp,r3 +0x08,0x41,0x6a,0xc3 = sh3addl,<= r1,rp,r3 +0x08,0x41,0x8a,0xc3 = sh3addl,nuv r1,rp,r3 +0x08,0x41,0xaa,0xc3 = sh3addl,znv r1,rp,r3 +0x08,0x41,0xca,0xc3 = sh3addl,sv r1,rp,r3 +0x08,0x41,0xea,0xc3 = sh3addl,od r1,rp,r3 +0x08,0x41,0x1a,0xc3 = sh3addl,tr r1,rp,r3 +0x08,0x41,0x3a,0xc3 = sh3addl,<> r1,rp,r3 +0x08,0x41,0x5a,0xc3 = sh3addl,>= r1,rp,r3 +0x08,0x41,0x7a,0xc3 = sh3addl,> r1,rp,r3 +0x08,0x41,0x9a,0xc3 = sh3addl,uv r1,rp,r3 +0x08,0x41,0xba,0xc3 = sh3addl,vnz r1,rp,r3 +0x08,0x41,0xda,0xc3 = sh3addl,nsv r1,rp,r3 +0x08,0x41,0xfa,0xc3 = sh3addl,ev r1,rp,r3 +0x08,0x20,0x0b,0x82 = dcor r1,rp +0x08,0x20,0x2b,0x82 = dcor,swz r1,rp +0x08,0x20,0x4b,0x82 = dcor,sbz r1,rp +0x08,0x20,0x6b,0x82 = dcor,shz r1,rp +0x08,0x20,0x1b,0x82 = dcor,tr r1,rp +0x08,0x20,0x3b,0x82 = dcor,nwz r1,rp +0x08,0x20,0x5b,0x82 = dcor,nbz r1,rp +0x08,0x20,0x7b,0x82 = dcor,nhz r1,rp +0x08,0x20,0x0b,0xc2 = idcor r1,rp +0x08,0x20,0x2b,0xc2 = idcor,swz r1,rp +0x08,0x20,0x4b,0xc2 = idcor,sbz r1,rp +0x08,0x20,0x6b,0xc2 = idcor,shz r1,rp +0x08,0x20,0x1b,0xc2 = idcor,tr r1,rp +0x08,0x20,0x3b,0xc2 = idcor,nwz r1,rp +0x08,0x20,0x5b,0xc2 = idcor,nbz r1,rp +0x08,0x20,0x7b,0xc2 = idcor,nhz r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/arith_imm11.s.cs b/suite/MC/HPPA/arith_imm11.s.cs new file mode 100644 index 0000000000..e2721e87df --- /dev/null +++ b/suite/MC/HPPA/arith_imm11.s.cs @@ -0,0 +1,97 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0xb4,0x22,0x00,0x1e = addi 0xf,r1,rp +0xb4,0x22,0x20,0x1e = addi,= 0xf,r1,rp +0xb4,0x22,0x40,0x1e = addi,< 0xf,r1,rp +0xb4,0x22,0x60,0x1e = addi,<= 0xf,r1,rp +0xb4,0x22,0x80,0x1e = addi,nuv 0xf,r1,rp +0xb4,0x22,0xa0,0x1e = addi,znv 0xf,r1,rp +0xb4,0x22,0xc0,0x1e = addi,sv 0xf,r1,rp +0xb4,0x22,0xe0,0x1e = addi,od 0xf,r1,rp +0xb4,0x22,0x10,0x1e = addi,tr 0xf,r1,rp +0xb4,0x22,0x30,0x1e = addi,<> 0xf,r1,rp +0xb4,0x22,0x50,0x1e = addi,>= 0xf,r1,rp +0xb4,0x22,0x70,0x1e = addi,> 0xf,r1,rp +0xb4,0x22,0x90,0x1e = addi,uv 0xf,r1,rp +0xb4,0x22,0xb0,0x1e = addi,vnz 0xf,r1,rp +0xb4,0x22,0xd0,0x1e = addi,nsv 0xf,r1,rp +0xb4,0x22,0xf0,0x1e = addi,ev 0xf,r1,rp +0xb0,0x22,0x00,0x1e = addit 0xf,r1,rp +0xb0,0x22,0x20,0x1e = addit,= 0xf,r1,rp +0xb0,0x22,0x40,0x1e = addit,< 0xf,r1,rp +0xb0,0x22,0x60,0x1e = addit,<= 0xf,r1,rp +0xb0,0x22,0x80,0x1e = addit,nuv 0xf,r1,rp +0xb0,0x22,0xa0,0x1e = addit,znv 0xf,r1,rp +0xb0,0x22,0xc0,0x1e = addit,sv 0xf,r1,rp +0xb0,0x22,0xe0,0x1e = addit,od 0xf,r1,rp +0xb0,0x22,0x10,0x1e = addit,tr 0xf,r1,rp +0xb0,0x22,0x30,0x1e = addit,<> 0xf,r1,rp +0xb0,0x22,0x50,0x1e = addit,>= 0xf,r1,rp +0xb0,0x22,0x70,0x1e = addit,> 0xf,r1,rp +0xb0,0x22,0x90,0x1e = addit,uv 0xf,r1,rp +0xb0,0x22,0xb0,0x1e = addit,vnz 0xf,r1,rp +0xb0,0x22,0xd0,0x1e = addit,nsv 0xf,r1,rp +0xb0,0x22,0xf0,0x1e = addit,ev 0xf,r1,rp +0x94,0x22,0x00,0x1e = subi 0xf,r1,rp +0x94,0x22,0x20,0x1e = subi,= 0xf,r1,rp +0x94,0x22,0x40,0x1e = subi,< 0xf,r1,rp +0x94,0x22,0x60,0x1e = subi,<= 0xf,r1,rp +0x94,0x22,0x80,0x1e = subi,<< 0xf,r1,rp +0x94,0x22,0xa0,0x1e = subi,<<= 0xf,r1,rp +0x94,0x22,0xc0,0x1e = subi,sv 0xf,r1,rp +0x94,0x22,0xe0,0x1e = subi,od 0xf,r1,rp +0x94,0x22,0x10,0x1e = subi,tr 0xf,r1,rp +0x94,0x22,0x30,0x1e = subi,<> 0xf,r1,rp +0x94,0x22,0x50,0x1e = subi,>= 0xf,r1,rp +0x94,0x22,0x70,0x1e = subi,> 0xf,r1,rp +0x94,0x22,0x90,0x1e = subi,>>= 0xf,r1,rp +0x94,0x22,0xb0,0x1e = subi,>> 0xf,r1,rp +0x94,0x22,0xd0,0x1e = subi,nsv 0xf,r1,rp +0x94,0x22,0xf0,0x1e = subi,ev 0xf,r1,rp +0xb4,0x22,0x08,0x1e = addio 0xf,r1,rp +0xb4,0x22,0x28,0x1e = addio,= 0xf,r1,rp +0xb4,0x22,0x48,0x1e = addio,< 0xf,r1,rp +0xb4,0x22,0x68,0x1e = addio,<= 0xf,r1,rp +0xb4,0x22,0x88,0x1e = addio,nuv 0xf,r1,rp +0xb4,0x22,0xa8,0x1e = addio,znv 0xf,r1,rp +0xb4,0x22,0xc8,0x1e = addio,sv 0xf,r1,rp +0xb4,0x22,0xe8,0x1e = addio,od 0xf,r1,rp +0xb4,0x22,0x18,0x1e = addio,tr 0xf,r1,rp +0xb4,0x22,0x38,0x1e = addio,<> 0xf,r1,rp +0xb4,0x22,0x58,0x1e = addio,>= 0xf,r1,rp +0xb4,0x22,0x78,0x1e = addio,> 0xf,r1,rp +0xb4,0x22,0x98,0x1e = addio,uv 0xf,r1,rp +0xb4,0x22,0xb8,0x1e = addio,vnz 0xf,r1,rp +0xb4,0x22,0xd8,0x1e = addio,nsv 0xf,r1,rp +0xb4,0x22,0xf8,0x1e = addio,ev 0xf,r1,rp +0xb0,0x22,0x08,0x1e = addito 0xf,r1,rp +0xb0,0x22,0x28,0x1e = addito,= 0xf,r1,rp +0xb0,0x22,0x48,0x1e = addito,< 0xf,r1,rp +0xb0,0x22,0x68,0x1e = addito,<= 0xf,r1,rp +0xb0,0x22,0x88,0x1e = addito,nuv 0xf,r1,rp +0xb0,0x22,0xa8,0x1e = addito,znv 0xf,r1,rp +0xb0,0x22,0xc8,0x1e = addito,sv 0xf,r1,rp +0xb0,0x22,0xe8,0x1e = addito,od 0xf,r1,rp +0xb0,0x22,0x18,0x1e = addito,tr 0xf,r1,rp +0xb0,0x22,0x38,0x1e = addito,<> 0xf,r1,rp +0xb0,0x22,0x58,0x1e = addito,>= 0xf,r1,rp +0xb0,0x22,0x78,0x1e = addito,> 0xf,r1,rp +0xb0,0x22,0x98,0x1e = addito,uv 0xf,r1,rp +0xb0,0x22,0xb8,0x1e = addito,vnz 0xf,r1,rp +0xb0,0x22,0xd8,0x1e = addito,nsv 0xf,r1,rp +0xb0,0x22,0xf8,0x1e = addito,ev 0xf,r1,rp +0x94,0x22,0x08,0x1e = subio 0xf,r1,rp +0x94,0x22,0x28,0x1e = subio,= 0xf,r1,rp +0x94,0x22,0x48,0x1e = subio,< 0xf,r1,rp +0x94,0x22,0x68,0x1e = subio,<= 0xf,r1,rp +0x94,0x22,0x88,0x1e = subio,<< 0xf,r1,rp +0x94,0x22,0xa8,0x1e = subio,<<= 0xf,r1,rp +0x94,0x22,0xc8,0x1e = subio,sv 0xf,r1,rp +0x94,0x22,0xe8,0x1e = subio,od 0xf,r1,rp +0x94,0x22,0x18,0x1e = subio,tr 0xf,r1,rp +0x94,0x22,0x38,0x1e = subio,<> 0xf,r1,rp +0x94,0x22,0x58,0x1e = subio,>= 0xf,r1,rp +0x94,0x22,0x78,0x1e = subio,> 0xf,r1,rp +0x94,0x22,0x98,0x1e = subio,>>= 0xf,r1,rp +0x94,0x22,0xb8,0x1e = subio,>> 0xf,r1,rp +0x94,0x22,0xd8,0x1e = subio,nsv 0xf,r1,rp +0x94,0x22,0xf8,0x1e = subio,ev 0xf,r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/assist20.s.cs b/suite/MC/HPPA/assist20.s.cs new file mode 100644 index 0000000000..e19fc2783f --- /dev/null +++ b/suite/MC/HPPA/assist20.s.cs @@ -0,0 +1,32 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x10,0x00,0x00,0x61 = spop0,1,1,n +0x10,0x00,0x0a,0x61 = spop1,1,1,n r1 +0x10,0x20,0x04,0x61 = spop2,1,1,n r1 +0x10,0x41,0x06,0x61 = spop3,1,1,n r1,rp +0x30,0x00,0x01,0x61 = copr,5,1,n +0x2c,0x5e,0x59,0x41 = cldd,5,sl 0xf(sr1,rp),r1 +0x2c,0x5e,0x79,0x61 = cldd,5,mb,sl 0xf(sr1,rp),r1 +0x2c,0x5e,0x59,0x61 = cldd,5,ma,sl 0xf(sr1,rp),r1 +0x2c,0x41,0x49,0x43 = cldd,5,sl 2(sr1,rp),r3 +0x2c,0x41,0x69,0x43 = cldd,5,s,sl 2(sr1,rp),r3 +0x2c,0x41,0x69,0x63 = cldd,5,sm,sl 2(sr1,rp),r3 +0x2c,0x41,0x49,0x63 = cldd,5,m,sl 2(sr1,rp),r3 +0x24,0x5e,0x59,0x41 = cldw,5,sl 0xf(sr1,rp),r1 +0x24,0x5e,0x79,0x61 = cldw,5,mb,sl 0xf(sr1,rp),r1 +0x24,0x5e,0x59,0x61 = cldw,5,ma,sl 0xf(sr1,rp),r1 +0x24,0x41,0x49,0x43 = cldw,5,sl r1(sr1,rp),r3 +0x24,0x41,0x69,0x43 = cldw,5,s,sl r1(sr1,rp),r3 +0x24,0x41,0x69,0x63 = cldw,5,sm,sl r1(sr1,rp),r3 +0x24,0x41,0x49,0x63 = cldw,5,m,sl r1(sr1,rp),r3 +0x2c,0x5e,0x17,0x41 = cstd,5,bc r1,0xf(rp) +0x2c,0x5e,0x37,0x61 = cstd,5,mb,bc r1,0xf(rp) +0x2c,0x5e,0x17,0x61 = cstd,5,ma,bc r1,0xf(rp) +0x2c,0x43,0x07,0x41 = cstd,5,bc r1,r3(rp) +0x2c,0x43,0x27,0x41 = cstd,5,s,bc r1,r3(rp) +0x2c,0x43,0x27,0x61 = cstd,5,sm,bc r1,r3(rp) +0x24,0x5e,0x17,0x41 = cstw,5,bc r1,0xf(rp) +0x24,0x5e,0x37,0x61 = cstw,5,mb,bc r1,0xf(rp) +0x24,0x5e,0x17,0x61 = cstw,5,ma,bc r1,0xf(rp) +0x24,0x43,0x07,0x41 = cstw,5,bc r1,r3(rp) +0x24,0x43,0x27,0x41 = cstw,5,s,bc r1,r3(rp) +0x24,0x43,0x27,0x61 = cstw,5,sm,bc r1,r3(rp) \ No newline at end of file diff --git a/suite/MC/HPPA/branch11.s.cs b/suite/MC/HPPA/branch11.s.cs new file mode 100644 index 0000000000..af58e2bcfb --- /dev/null +++ b/suite/MC/HPPA/branch11.s.cs @@ -0,0 +1,9 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0xe8,0x3f,0x1f,0x75 = bl 0xffffffffffffffc0,r1 +0xe8,0x3f,0x1f,0x6f = bl,n 0xffffffffffffffbc,r1 +0xe8,0x41,0x40,0x00 = blr r1,rp +0xe8,0x41,0x40,0x02 = blr,n r1,rp +0xe8,0x41,0xc0,0x00 = bv r1(rp) +0xe8,0x41,0xc0,0x02 = bv,n r1(rp) +0xe8,0x5f,0x3f,0x45 = gate 0xffffffffffffffa8,rp +0xe8,0x5f,0x3f,0x3f = gate,n 0xffffffffffffffa4,rp \ No newline at end of file diff --git a/suite/MC/HPPA/branch20.s.cs b/suite/MC/HPPA/branch20.s.cs new file mode 100644 index 0000000000..3127b00489 --- /dev/null +++ b/suite/MC/HPPA/branch20.s.cs @@ -0,0 +1,43 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0xeb,0xff,0xb8,0x9d = b,l 0xfffffffffffffc54,r31 +0xeb,0xff,0xb8,0x97 = b,l,n 0xfffffffffffffc50,r31 +0xeb,0x9f,0x38,0x8d = b,gate 0xfffffffffffffc4c,ret0 +0xeb,0x9f,0x38,0x87 = b,gate,n 0xfffffffffffffc48,ret0 +0xeb,0xff,0x98,0x7d = b,l,push 0xfffffffffffffc44,r31 +0xeb,0xff,0x98,0x77 = b,l,push,n 0xfffffffffffffc40,r31 +0xe8,0x41,0x40,0x00 = blr r1,rp +0xe8,0x41,0x40,0x02 = blr,n r1,rp +0xe8,0x41,0xc0,0x00 = bv r1(rp) +0xe8,0x41,0xc0,0x02 = bv,n r1(rp) +0xe0,0x20,0x40,0x00 = be 0(sr1,r1) +0xe0,0x20,0x40,0x02 = be,n 0(sr1,r1) +0xe4,0x20,0x40,0x00 = be,l 0(sr1,r1),sr0,r31 +0xe4,0x20,0x40,0x02 = be,l,n 0(sr1,r1),sr0,r31 +0xe8,0x40,0xd0,0x00 = bve (rp) +0xe8,0x40,0xd0,0x02 = bve,n (rp) +0xe8,0x40,0xd0,0x01 = bve,pop (rp) +0xe8,0x40,0xd0,0x03 = bve,pop,n (rp) +0xe8,0x20,0xf0,0x00 = bve,l (r1),rp +0xe8,0x20,0xf0,0x02 = bve,l,n (r1),rp +0xe8,0x20,0xf0,0x01 = bve,l,push (r1),rp +0xe8,0x20,0xf0,0x03 = bve,l,push,n (r1),rp +0xa0,0x41,0x17,0xed = addb r1,rp,0xfffffffffffffbfc +0xa0,0x41,0x37,0xe5 = addb,= r1,rp,0xfffffffffffffbf8 +0xa0,0x41,0x37,0xdf = addb,=,n r1,rp,0xfffffffffffffbf4 +0xa4,0x5e,0x17,0xd5 = addib 0xf,rp,0xfffffffffffffbf0 +0xa4,0x5e,0x37,0xcd = addib,= 0xf,rp,0xfffffffffffffbec +0xa4,0x5e,0x37,0xc7 = addib,=,n 0xf,rp,0xfffffffffffffbe8 +0xc5,0xe1,0xd7,0xbd = bb,>= r1,0xf,0xfffffffffffffbe4 +0xc5,0xe1,0xd7,0xb7 = bb,>=,n r1,0xf,0xfffffffffffffbe0 +0x80,0x41,0x17,0xad = cmpb r1,rp,0xfffffffffffffbdc +0x80,0x41,0x37,0xa5 = cmpb,= r1,rp,0xfffffffffffffbd8 +0x80,0x41,0x37,0x9f = cmpb,=,n r1,rp,0xfffffffffffffbd4 +0x84,0x5e,0x17,0x95 = cmpib 0xf,rp,0xfffffffffffffbd0 +0x84,0x5e,0x37,0x8d = cmpib,= 0xf,rp,0xfffffffffffffbcc +0x84,0x5e,0x37,0x87 = cmpib,=,n 0xf,rp,0xfffffffffffffbc8 +0xc8,0x41,0x17,0x7d = movb r1,rp,0xfffffffffffffbc4 +0xc8,0x41,0x37,0x75 = movb,= r1,rp,0xfffffffffffffbc0 +0xc8,0x41,0x37,0x6f = movb,=,n r1,rp,0xfffffffffffffbbc +0xcc,0x5e,0x17,0x65 = movib 0xf,rp,0xfffffffffffffbb8 +0xcc,0x5e,0x37,0x5d = movib,= 0xf,rp,0xfffffffffffffbb4 +0xcc,0x5e,0x37,0x57 = movib,=,n 0xf,rp,0xfffffffffffffbb0 \ No newline at end of file diff --git a/suite/MC/HPPA/computation20.s.cs b/suite/MC/HPPA/computation20.s.cs new file mode 100644 index 0000000000..e1cf5a8f7c --- /dev/null +++ b/suite/MC/HPPA/computation20.s.cs @@ -0,0 +1,63 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x08,0x41,0x66,0x03 = add,<= r1,rp,r3 +0x08,0x41,0x07,0x03 = add,c r1,rp,r3 +0x08,0x41,0x57,0x03 = add,c,>= r1,rp,r3 +0x08,0x41,0x07,0x23 = add,dc,* r1,rp,r3 +0x08,0x41,0x27,0x23 = add,dc,*= r1,rp,r3 +0x08,0x41,0x0a,0x03 = add,l r1,rp,r3 +0x08,0x41,0x4a,0x03 = add,l,< r1,rp,r3 +0x08,0x41,0x0e,0x03 = add,tsv r1,rp,r3 +0x08,0x41,0x7e,0x03 = add,tsv,> r1,rp,r3 +0x08,0x41,0x0f,0x03 = add,c,tsv r1,rp,r3 +0x08,0x41,0x3f,0x03 = add,c,tsv,<> r1,rp,r3 +0x08,0x41,0x0f,0x23 = add,dc,tsv,* r1,rp,r3 +0x08,0x41,0x5f,0x23 = add,dc,tsv,*>= r1,rp,r3 +0x08,0x41,0x06,0xc3 = shladd r1,3,rp,r3 +0x08,0x41,0x0a,0xc3 = shladd,l r1,3,rp,r3 +0x08,0x41,0x0e,0xc3 = shladd,tsv r1,3,rp,r3 +0x08,0x41,0xce,0xc3 = shladd,tsv,sv r1,3,rp,r3 +0x08,0x41,0x04,0x03 = sub r1,rp,r3 +0x08,0x41,0x04,0xc3 = sub,tc r1,rp,r3 +0x08,0x41,0x05,0x03 = sub,b r1,rp,r3 +0x08,0x41,0x0c,0x03 = sub,tsv r1,rp,r3 +0x08,0x41,0x0c,0xc3 = sub,tsv,tc r1,rp,r3 +0x08,0x41,0x0d,0x03 = sub,b,tsv r1,rp,r3 +0x08,0x41,0x6d,0x23 = sub,db,tsv,*<= r1,rp,r3 +0x08,0x41,0x02,0x43 = or r1,rp,r3 +0x08,0x41,0x22,0x43 = or,= r1,rp,r3 +0x08,0x41,0x02,0x83 = xor r1,rp,r3 +0x08,0x41,0x62,0x83 = xor,<= r1,rp,r3 +0x08,0x41,0x02,0x03 = and r1,rp,r3 +0x08,0x41,0x62,0x03 = and,<= r1,rp,r3 +0x08,0x41,0x00,0x03 = andcm r1,rp,r3 +0x08,0x41,0x60,0x03 = andcm,<= r1,rp,r3 +0x08,0x41,0x09,0x83 = uaddcm r1,rp,r3 +0x08,0x41,0x49,0x83 = uaddcm,sbz r1,rp,r3 +0x08,0x41,0x09,0xc3 = uaddcm,tc r1,rp,r3 +0x08,0x41,0x03,0x83 = uxor r1,rp,r3 +0x08,0x41,0x43,0x83 = uxor,sbz r1,rp,r3 +0x08,0x41,0x04,0x43 = ds r1,rp,r3 +0x08,0x41,0xa4,0x43 = ds,<<= r1,rp,r3 +0x08,0x41,0x08,0x83 = cmpclr r1,rp,r3 +0x08,0x41,0x98,0x83 = cmpclr,>>= r1,rp,r3 +0x08,0x20,0x0b,0x82 = dcor r1,rp +0x08,0x20,0x0b,0xc2 = dcor,i r1,rp +0x08,0x20,0x4b,0xc2 = dcor,i,sbz r1,rp +0xb4,0x22,0x01,0xbc = addi 0xde,r1,rp +0xb4,0x22,0x09,0xbc = addi,tsv 0xde,r1,rp +0xb0,0x22,0x01,0xbc = addi,tc 0xde,r1,rp +0xb0,0x22,0x09,0xbc = addi,tsv,tc 0xde,r1,rp +0xb0,0x22,0x69,0xbc = addi,tsv,tc,<= 0xde,r1,rp +0x94,0x22,0x01,0xbc = subi 0xde,r1,rp +0x94,0x22,0x09,0xbc = subi,tsv 0xde,r1,rp +0x94,0x22,0x29,0xbc = subi,tsv,= 0xde,r1,rp +0x90,0x43,0x01,0xbc = cmpiclr 0xde,rp,r3 +0x90,0x43,0x91,0xbc = cmpiclr,>>= 0xde,rp,r3 +0xd0,0x41,0x0f,0x83 = shrpd,* r1,rp,3,r3 +0xd0,0x41,0x4f,0x83 = shrpd,*< r1,rp,3,r3 +0xd0,0x41,0x0b,0x83 = shrpw r1,rp,3,r3 +0xd0,0x41,0x4b,0x83 = shrpw,< r1,rp,3,r3 +0xd0,0x22,0x16,0x1c = extrd,s,* r1,sar,4,rp +0xd8,0x22,0x07,0xdc = extrd,s,* r1,0x1e,4,rp +0xd8,0x22,0x03,0xdc = extrd,u,* r1,0x1e,4,rp +0xd8,0x22,0xc3,0xdc = extrd,u,*>= r1,0x1e,4,rp \ No newline at end of file diff --git a/suite/MC/HPPA/copr_dw11.s.cs b/suite/MC/HPPA/copr_dw11.s.cs new file mode 100644 index 0000000000..5187667a50 --- /dev/null +++ b/suite/MC/HPPA/copr_dw11.s.cs @@ -0,0 +1,41 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x24,0x41,0x40,0xc3 = cldwx,3 r1(sr1,rp),r3 +0x24,0x41,0x60,0xc3 = cldwx,3,s r1(sr1,rp),r3 +0x24,0x41,0x40,0xe3 = cldwx,3,m r1(sr1,rp),r3 +0x24,0x41,0x60,0xe3 = cldwx,3,sm r1(sr1,rp),r3 +0x24,0x41,0x68,0xe3 = cldwx,3,sm,sl r1(sr1,rp),r3 +0x2c,0x41,0x40,0xc3 = clddx,3 r1(sr1,rp),r3 +0x2c,0x41,0x60,0xc3 = clddx,3,s r1(sr1,rp),r3 +0x2c,0x41,0x40,0xe3 = clddx,3,m r1(sr1,rp),r3 +0x2c,0x41,0x60,0xe3 = clddx,3,sm r1(sr1,rp),r3 +0x2c,0x41,0x68,0xe3 = clddx,3,sm,sl r1(sr1,rp),r3 +0x24,0x62,0x42,0xc1 = cstwx,3 r1,rp(sr1,r3) +0x24,0x62,0x62,0xc1 = cstwx,3,s r1,rp(sr1,r3) +0x24,0x62,0x42,0xe1 = cstwx,3,m r1,rp(sr1,r3) +0x24,0x62,0x46,0xe1 = cstwx,3,m,bc r1,rp(sr1,r3) +0x24,0x62,0x62,0xe1 = cstwx,3,sm r1,rp(sr1,r3) +0x24,0x62,0x6a,0xe1 = cstwx,3,sm,sl r1,rp(sr1,r3) +0x2c,0x62,0x42,0xc1 = cstdx,3 r1,rp(sr1,r3) +0x2c,0x62,0x62,0xc1 = cstdx,3,s r1,rp(sr1,r3) +0x2c,0x62,0x42,0xe1 = cstdx,3,m r1,rp(sr1,r3) +0x2c,0x62,0x46,0xe1 = cstdx,3,m,bc r1,rp(sr1,r3) +0x2c,0x62,0x62,0xe1 = cstdx,3,sm r1,rp(sr1,r3) +0x2c,0x62,0x6a,0xe1 = cstdx,3,sm,sl r1,rp(sr1,r3) +0x24,0x3e,0x50,0xc2 = cldws,3 0xf(sr1,r1),rp +0x24,0x3e,0x50,0xe2 = cldws,3,ma 0xf(sr1,r1),rp +0x24,0x3e,0x70,0xe2 = cldws,3,mb 0xf(sr1,r1),rp +0x24,0x3e,0x78,0xe2 = cldws,3,mb,sl 0xf(sr1,r1),rp +0x2c,0x3e,0x50,0xc2 = cldds,3 0xf(sr1,r1),rp +0x2c,0x3e,0x50,0xe2 = cldds,3,ma 0xf(sr1,r1),rp +0x2c,0x3e,0x70,0xe2 = cldds,3,mb 0xf(sr1,r1),rp +0x2c,0x3e,0x78,0xe2 = cldds,3,mb,sl 0xf(sr1,r1),rp +0x24,0x5e,0x52,0xc1 = cstws,3 r1,0xf(sr1,rp) +0x24,0x5e,0x52,0xe1 = cstws,3,ma r1,0xf(sr1,rp) +0x24,0x5e,0x56,0xe1 = cstws,3,ma,bc r1,0xf(sr1,rp) +0x24,0x5e,0x72,0xe1 = cstws,3,mb r1,0xf(sr1,rp) +0x24,0x5e,0x7a,0xe1 = cstws,3,mb,sl r1,0xf(sr1,rp) +0x2c,0x5e,0x52,0xc1 = cstds,3 r1,0xf(sr1,rp) +0x2c,0x5e,0x52,0xe1 = cstds,3,ma r1,0xf(sr1,rp) +0x2c,0x5e,0x56,0xe1 = cstds,3,ma,bc r1,0xf(sr1,rp) +0x2c,0x5e,0x72,0xe1 = cstds,3,mb r1,0xf(sr1,rp) +0x2c,0x5e,0x7a,0xe1 = cstds,3,mb,sl r1,0xf(sr1,rp) \ No newline at end of file diff --git a/suite/MC/HPPA/float11.s.cs b/suite/MC/HPPA/float11.s.cs new file mode 100644 index 0000000000..45c5e5431d --- /dev/null +++ b/suite/MC/HPPA/float11.s.cs @@ -0,0 +1,89 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x30,0x00,0x00,0x20 = copr,0,0,n +0x30,0x00,0x00,0x62 = copr,1,2,n +0x30,0x20,0x40,0x02 = fcpy,sgl fpe2,fpe4 +0x30,0x20,0x48,0x02 = fcpy,dbl fpe2,fpe4 +0x30,0x20,0x58,0x02 = fcpy,quad fpe2,fpe4 +0x30,0x20,0x60,0x02 = fabs,sgl fpe2,fpe4 +0x30,0x20,0x68,0x02 = fabs,dbl fpe2,fpe4 +0x30,0x20,0x78,0x02 = fabs,quad fpe2,fpe4 +0x30,0x20,0x80,0x02 = fsqrt,sgl fpe2,fpe4 +0x30,0x20,0x88,0x02 = fsqrt,dbl fpe2,fpe4 +0x30,0x20,0x98,0x02 = fsqrt,quad fpe2,fpe4 +0x30,0x20,0xa0,0x02 = frnd,sgl fpe2,fpe4 +0x30,0x20,0xa8,0x02 = frnd,dbl fpe2,fpe4 +0x30,0x20,0xb8,0x02 = frnd,quad fpe2,fpe4 +0x30,0x20,0x22,0x02 = fcnvff,sgl,dbl fpe2,fpe4 +0x30,0x20,0x62,0x02 = fcnvff,sgl,quad fpe2,fpe4 +0x30,0x20,0x0a,0x02 = fcnvff,dbl,sgl fpe2,fpe4 +0x30,0x20,0x6a,0x02 = fcnvff,dbl,quad fpe2,fpe4 +0x30,0x20,0x02,0x02 = fcnvff,sgl,sgl fpe2,fpe4 +0x30,0x20,0x2a,0x02 = fcnvff,dbl,dbl fpe2,fpe4 +0x30,0x20,0x7a,0x02 = fcnvff,quad,quad fpe2,fpe4 +0x30,0x20,0xa2,0x02 = fcnvxf,sgl,dbl fpe2,fpe4 +0x30,0x20,0xe2,0x02 = fcnvxf,sgl,quad fpe2,fpe4 +0x30,0x20,0x8a,0x02 = fcnvxf,dbl,sgl fpe2,fpe4 +0x30,0x20,0xea,0x02 = fcnvxf,dbl,quad fpe2,fpe4 +0x30,0x20,0x82,0x02 = fcnvxf,sgl,sgl fpe2,fpe4 +0x30,0x20,0xaa,0x02 = fcnvxf,dbl,dbl fpe2,fpe4 +0x30,0x20,0xfa,0x02 = fcnvxf,quad,quad fpe2,fpe4 +0x30,0x21,0x22,0x02 = fcnvfx,sgl,dbl fpe2,fpe4 +0x30,0x21,0x62,0x02 = fcnvfx,sgl,quad fpe2,fpe4 +0x30,0x21,0x0a,0x02 = fcnvfx,dbl,sgl fpe2,fpe4 +0x30,0x21,0x6a,0x02 = fcnvfx,dbl,quad fpe2,fpe4 +0x30,0x21,0x02,0x02 = fcnvfx,sgl,sgl fpe2,fpe4 +0x30,0x21,0x2a,0x02 = fcnvfx,dbl,dbl fpe2,fpe4 +0x30,0x21,0x7a,0x02 = fcnvfx,quad,quad fpe2,fpe4 +0x30,0x21,0xa2,0x02 = fcnvfxt,sgl,dbl fpe2,fpe4 +0x30,0x21,0xe2,0x02 = fcnvfxt,sgl,quad fpe2,fpe4 +0x30,0x21,0x8a,0x02 = fcnvfxt,dbl,sgl fpe2,fpe4 +0x30,0x21,0xea,0x02 = fcnvfxt,dbl,quad fpe2,fpe4 +0x30,0x21,0x82,0x02 = fcnvfxt,sgl,sgl fpe2,fpe4 +0x30,0x21,0xaa,0x02 = fcnvfxt,dbl,dbl fpe2,fpe4 +0x30,0x21,0xfa,0x02 = fcnvfxt,quad,quad fpe2,fpe4 +0x30,0x22,0x04,0x00 = fcmp,sgl,false? fpe2,fpe4 +0x30,0x22,0x04,0x01 = fcmp,sgl,false fpe2,fpe4 +0x30,0x22,0x04,0x02 = fcmp,sgl,? fpe2,fpe4 +0x30,0x22,0x04,0x03 = fcmp,sgl,!<=> fpe2,fpe4 +0x30,0x22,0x04,0x04 = fcmp,sgl,= fpe2,fpe4 +0x30,0x22,0x04,0x05 = fcmp,sgl,=t fpe2,fpe4 +0x30,0x22,0x04,0x06 = fcmp,sgl,?= fpe2,fpe4 +0x30,0x22,0x04,0x07 = fcmp,sgl,!<> fpe2,fpe4 +0x30,0x22,0x04,0x08 = fcmp,sgl,!?>= fpe2,fpe4 +0x30,0x22,0x04,0x09 = fcmp,sgl,< fpe2,fpe4 +0x30,0x22,0x04,0x0a = fcmp,sgl,?< fpe2,fpe4 +0x30,0x22,0x04,0x0b = fcmp,sgl,!>= fpe2,fpe4 +0x30,0x22,0x04,0x0c = fcmp,sgl,!?> fpe2,fpe4 +0x30,0x22,0x04,0x0d = fcmp,sgl,<= fpe2,fpe4 +0x30,0x22,0x04,0x0e = fcmp,sgl,?<= fpe2,fpe4 +0x30,0x22,0x04,0x0f = fcmp,sgl,!> fpe2,fpe4 +0x30,0x22,0x04,0x10 = fcmp,sgl,!?<= fpe2,fpe4 +0x30,0x22,0x04,0x11 = fcmp,sgl,> fpe2,fpe4 +0x30,0x22,0x04,0x12 = fcmp,sgl,?> fpe2,fpe4 +0x30,0x22,0x04,0x13 = fcmp,sgl,!<= fpe2,fpe4 +0x30,0x22,0x04,0x14 = fcmp,sgl,!?< fpe2,fpe4 +0x30,0x22,0x04,0x15 = fcmp,sgl,>= fpe2,fpe4 +0x30,0x22,0x04,0x16 = fcmp,sgl,?>= fpe2,fpe4 +0x30,0x22,0x04,0x17 = fcmp,sgl,!< fpe2,fpe4 +0x30,0x22,0x04,0x18 = fcmp,sgl,!?= fpe2,fpe4 +0x30,0x22,0x04,0x19 = fcmp,sgl,<> fpe2,fpe4 +0x30,0x22,0x04,0x1a = fcmp,sgl,!= fpe2,fpe4 +0x30,0x22,0x04,0x1b = fcmp,sgl,!=t fpe2,fpe4 +0x30,0x22,0x04,0x1c = fcmp,sgl,!? fpe2,fpe4 +0x30,0x22,0x04,0x1d = fcmp,sgl,<=> fpe2,fpe4 +0x30,0x22,0x04,0x1e = fcmp,sgl,true? fpe2,fpe4 +0x30,0x22,0x04,0x1f = fcmp,sgl,true fpe2,fpe4 +0x30,0x00,0x24,0x20 = ftest +0x30,0x22,0x06,0x03 = fadd,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x0e,0x03 = fadd,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x1e,0x03 = fadd,quad fpe2,fpe4,fpe6 +0x30,0x22,0x26,0x03 = fsub,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x2e,0x03 = fsub,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x3e,0x03 = fsub,quad fpe2,fpe4,fpe6 +0x30,0x22,0x46,0x03 = fmpy,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x4e,0x03 = fmpy,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x5e,0x03 = fmpy,quad fpe2,fpe4,fpe6 +0x30,0x22,0x66,0x03 = fdiv,sgl fpe2,fpe4,fpe6 +0x30,0x22,0x6e,0x03 = fdiv,dbl fpe2,fpe4,fpe6 +0x30,0x22,0x7e,0x03 = fdiv,quad fpe2,fpe4,fpe6 +0x38,0x22,0x47,0x03 = xmpyu fpe2,fpe4,fpe6 \ No newline at end of file diff --git a/suite/MC/HPPA/float20.s.cs b/suite/MC/HPPA/float20.s.cs new file mode 100644 index 0000000000..c0c7f20f81 --- /dev/null +++ b/suite/MC/HPPA/float20.s.cs @@ -0,0 +1,57 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x24,0x2a,0x10,0x14 = fldw 5(r1),fr20 +0x24,0x2a,0x30,0x34 = fldw,mb 5(r1),fr20 +0x24,0x2a,0x10,0x34 = fldw,ma 5(r1),fr20 +0x24,0x22,0x00,0x14 = fldw rp(r1),fr20 +0x24,0x22,0x20,0x14 = fldw,s rp(r1),fr20 +0x24,0x22,0x20,0x34 = fldw,sm rp(r1),fr20 +0x24,0x22,0x00,0x34 = fldw,m rp(r1),fr20 +0x2c,0x2a,0x10,0x14 = fldd 5(r1),fr20 +0x2c,0x2a,0x30,0x34 = fldd,mb 5(r1),fr20 +0x2c,0x2a,0x10,0x34 = fldd,ma 5(r1),fr20 +0x2c,0x22,0x00,0x14 = fldd rp(r1),fr20 +0x2c,0x22,0x20,0x14 = fldd,s rp(r1),fr20 +0x2c,0x22,0x20,0x34 = fldd,sm rp(r1),fr20 +0x2c,0x22,0x00,0x34 = fldd,m rp(r1),fr20 +0x24,0x5e,0x12,0x14 = fstw fr20,0xf(rp) +0x24,0x5e,0x32,0x34 = fstw,mb fr20,0xf(rp) +0x24,0x5e,0x12,0x34 = fstw,ma fr20,0xf(rp) +0x24,0x41,0x06,0x14 = fstw,bc fr20,r1(rp) +0x24,0x41,0x26,0x14 = fstw,s,bc fr20,r1(rp) +0x24,0x41,0x26,0x34 = fstw,sm,bc fr20,r1(rp) +0x24,0x41,0x06,0x34 = fstw,m,bc fr20,r1(rp) +0x2c,0x5e,0x12,0x14 = fstd fr20,0xf(rp) +0x2c,0x5e,0x32,0x34 = fstd,mb fr20,0xf(rp) +0x2c,0x5e,0x12,0x34 = fstd,ma fr20,0xf(rp) +0x2c,0x41,0x06,0x14 = fstd,bc fr20,r1(rp) +0x2c,0x41,0x26,0x14 = fstd,s,bc fr20,r1(rp) +0x2c,0x41,0x26,0x34 = fstd,sm,bc fr20,r1(rp) +0x2c,0x41,0x06,0x34 = fstd,m,bc fr20,r1(rp) +0x30,0x00,0x00,0x00 = fid +0x32,0x80,0x40,0x15 = fcpy,sgl fr20,fr21 +0x32,0x80,0x60,0x15 = fabs,sgl fr20,fr21 +0x32,0x80,0x80,0x15 = fsqrt,sgl fr20,fr21 +0x32,0x80,0xa0,0x15 = frnd,sgl fr20,fr21 +0x32,0x80,0xc0,0x15 = fneg,sgl fr20,fr21 +0x32,0x80,0xe0,0x15 = fnegabs,sgl fr20,fr21 +0x32,0x80,0x22,0x15 = fcnv,sgl,dbl fr20,fr21 +0x32,0x80,0xa2,0x15 = fcnv,w,dbl fr20,fr21 +0x32,0x95,0x04,0x04 = fcmp,sgl,= fr20,fr21 +0x32,0x95,0x44,0x04 = fcmp,sgl,= fr20,fr21,1 +0x30,0x00,0x64,0x20 = ftest 1 +0x30,0x00,0x24,0x21 = ftest,acc +0x30,0x00,0x24,0x25 = ftest,acc8 +0x30,0x00,0x24,0x29 = ftest,acc6 +0x30,0x00,0x24,0x2d = ftest,acc4 +0x30,0x00,0x24,0x31 = ftest,acc2 +0x30,0x00,0x24,0x22 = ftest,rej +0x30,0x00,0x24,0x26 = ftest,rej8 +0x32,0x95,0x06,0x16 = fadd,sgl fr20,fr21,fr22 +0x32,0x95,0x26,0x16 = fsub,sgl fr20,fr21,fr22 +0x32,0x95,0x46,0x16 = fmpy,sgl fr20,fr21,fr22 +0x32,0x95,0x66,0x16 = fdiv,sgl fr20,fr21,fr22 +0x3a,0x95,0x47,0x16 = xmpyu fr20,fr21,fr22 +0x18,0x85,0x41,0xe6 = fmpyadd,sgl fr20L,fr21L,fr22L,fr23L,fr24L +0x98,0x85,0x41,0xe6 = fmpysub,sgl fr20L,fr21L,fr22L,fr23L,fr24L +0xba,0x95,0xa4,0x17 = fmpyfadd,sgl fr20,fr21,fr22,fr23 +0xba,0x95,0xa4,0x37 = fmpynfadd,sgl fr20,fr21,fr22,fr23 \ No newline at end of file diff --git a/suite/MC/HPPA/index_mem11.s.cs b/suite/MC/HPPA/index_mem11.s.cs new file mode 100644 index 0000000000..9c6f44fa63 --- /dev/null +++ b/suite/MC/HPPA/index_mem11.s.cs @@ -0,0 +1,88 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x0c,0x20,0x40,0x02 = ldbx flags(sr1,r1),rp +0x0c,0x20,0x60,0x02 = ldbx,s flags(sr1,r1),rp +0x0c,0x20,0x40,0x22 = ldbx,m flags(sr1,r1),rp +0x0c,0x20,0x60,0x22 = ldbx,sm flags(sr1,r1),rp +0x0c,0x20,0x68,0x02 = ldbx,s,sl flags(sr1,r1),rp +0x0c,0x20,0x48,0x22 = ldbx,m,sl flags(sr1,r1),rp +0x0c,0x20,0x68,0x22 = ldbx,sm,sl flags(sr1,r1),rp +0x0c,0x20,0x40,0x42 = ldhx flags(sr1,r1),rp +0x0c,0x20,0x60,0x42 = ldhx,s flags(sr1,r1),rp +0x0c,0x20,0x40,0x62 = ldhx,m flags(sr1,r1),rp +0x0c,0x20,0x60,0x62 = ldhx,sm flags(sr1,r1),rp +0x0c,0x20,0x68,0x42 = ldhx,s,sl flags(sr1,r1),rp +0x0c,0x20,0x48,0x62 = ldhx,m,sl flags(sr1,r1),rp +0x0c,0x20,0x68,0x62 = ldhx,sm,sl flags(sr1,r1),rp +0x0c,0x20,0x40,0x82 = ldwx flags(sr1,r1),rp +0x0c,0x20,0x60,0x82 = ldwx,s flags(sr1,r1),rp +0x0c,0x20,0x40,0xa2 = ldwx,m flags(sr1,r1),rp +0x0c,0x20,0x60,0xa2 = ldwx,sm flags(sr1,r1),rp +0x0c,0x20,0x68,0x82 = ldwx,s,sl flags(sr1,r1),rp +0x0c,0x20,0x48,0xa2 = ldwx,m,sl flags(sr1,r1),rp +0x0c,0x20,0x68,0xa2 = ldwx,sm,sl flags(sr1,r1),rp +0x0c,0x20,0x01,0x82 = ldwax flags(r1),rp +0x0c,0x20,0x21,0x82 = ldwax,s flags(r1),rp +0x0c,0x20,0x01,0xa2 = ldwax,m flags(r1),rp +0x0c,0x20,0x21,0xa2 = ldwax,sm flags(r1),rp +0x0c,0x20,0x29,0x82 = ldwax,s,sl flags(r1),rp +0x0c,0x20,0x09,0xa2 = ldwax,m,sl flags(r1),rp +0x0c,0x20,0x29,0xa2 = ldwax,sm,sl flags(r1),rp +0x0c,0x20,0x41,0xc2 = ldcwx flags(sr1,r1),rp +0x0c,0x20,0x61,0xc2 = ldcwx,s flags(sr1,r1),rp +0x0c,0x20,0x41,0xe2 = ldcwx,m flags(sr1,r1),rp +0x0c,0x20,0x61,0xe2 = ldcwx,sm flags(sr1,r1),rp +0x0c,0x20,0x65,0xc2 = ldcwx,s,co flags(sr1,r1),rp +0x0c,0x20,0x45,0xe2 = ldcwx,m,co flags(sr1,r1),rp +0x0c,0x20,0x65,0xe2 = ldcwx,sm,co flags(sr1,r1),rp +0x0c,0x3e,0x50,0x02 = ldbs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x22 = ldbs,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x70,0x22 = ldbs,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x58,0x22 = ldbs,ma,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x78,0x22 = ldbs,mb,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x42 = ldhs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x62 = ldhs,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x70,0x62 = ldhs,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x58,0x62 = ldhs,ma,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x78,0x62 = ldhs,mb,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x82 = ldws 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0xa2 = ldws,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x70,0xa2 = ldws,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x58,0xa2 = ldws,ma,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x78,0xa2 = ldws,mb,sl 0xf(sr1,r1),rp +0x0c,0x3e,0x11,0x82 = ldwas 0xf(r1),rp +0x0c,0x3e,0x11,0xa2 = ldwas,ma 0xf(r1),rp +0x0c,0x3e,0x31,0xa2 = ldwas,mb 0xf(r1),rp +0x0c,0x3e,0x19,0xa2 = ldwas,ma,sl 0xf(r1),rp +0x0c,0x3e,0x39,0xa2 = ldwas,mb,sl 0xf(r1),rp +0x0c,0x3e,0x51,0xc2 = ldcws 0xf(sr1,r1),rp +0x0c,0x3e,0x51,0xe2 = ldcws,ma 0xf(sr1,r1),rp +0x0c,0x3e,0x71,0xe2 = ldcws,mb 0xf(sr1,r1),rp +0x0c,0x3e,0x55,0xe2 = ldcws,ma,co 0xf(sr1,r1),rp +0x0c,0x3e,0x75,0xe2 = ldcws,mb,co 0xf(sr1,r1),rp +0x0c,0x41,0x52,0x1e = stbs r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x3e = stbs,ma r1,0xf(sr1,rp) +0x0c,0x41,0x72,0x3e = stbs,mb r1,0xf(sr1,rp) +0x0c,0x41,0x56,0x3e = stbs,ma,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7a,0x3e = stbs,mb,sl r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x5e = sths r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x7e = sths,ma r1,0xf(sr1,rp) +0x0c,0x41,0x72,0x7e = sths,mb r1,0xf(sr1,rp) +0x0c,0x41,0x56,0x7e = sths,ma,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7a,0x7e = sths,mb,sl r1,0xf(sr1,rp) +0x0c,0x41,0x52,0x9e = stws r1,0xf(sr1,rp) +0x0c,0x41,0x52,0xbe = stws,ma r1,0xf(sr1,rp) +0x0c,0x41,0x72,0xbe = stws,mb r1,0xf(sr1,rp) +0x0c,0x41,0x56,0xbe = stws,ma,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7a,0xbe = stws,mb,sl r1,0xf(sr1,rp) +0x0c,0x41,0x53,0x1e = stbys r1,0xf(sr1,rp) +0x0c,0x41,0x53,0x1e = stbys r1,0xf(sr1,rp) +0x0c,0x41,0x73,0x1e = stbys,e r1,0xf(sr1,rp) +0x0c,0x41,0x53,0x3e = stbys,b,m r1,0xf(sr1,rp) +0x0c,0x41,0x73,0x3e = stbys,e,m r1,0xf(sr1,rp) +0x0c,0x41,0x57,0x3e = stbys,b,m,bc r1,0xf(sr1,rp) +0x0c,0x41,0x7b,0x3e = stbys,e,m,sl r1,0xf(sr1,rp) +0x0c,0x41,0x13,0x9e = stwas r1,0xf(rp) +0x0c,0x41,0x33,0xbe = stwas,mb r1,0xf(rp) +0x0c,0x41,0x13,0xbe = stwas,ma r1,0xf(rp) +0x0c,0x41,0x37,0xbe = stwas,mb,bc r1,0xf(rp) +0x0c,0x41,0x1b,0xbe = stwas,ma,sl r1,0xf(rp) \ No newline at end of file diff --git a/suite/MC/HPPA/longimm20.s.cs b/suite/MC/HPPA/longimm20.s.cs new file mode 100644 index 0000000000..b7dce2bad9 --- /dev/null +++ b/suite/MC/HPPA/longimm20.s.cs @@ -0,0 +1,4 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x34,0x22,0x3f,0xf1 = ldo -8(r1),rp +0x23,0x98,0xc5,0x4f = ldil -0x55810000,ret0 +0x2b,0x98,0xc5,0x4f = addil -0x55810000,ret0 \ No newline at end of file diff --git a/suite/MC/HPPA/mem_mgmt11.s.cs b/suite/MC/HPPA/mem_mgmt11.s.cs new file mode 100644 index 0000000000..054ea86624 --- /dev/null +++ b/suite/MC/HPPA/mem_mgmt11.s.cs @@ -0,0 +1,25 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x04,0x41,0x40,0x40 = iitlba r1,(sr1,rp) +0x04,0x41,0x40,0x00 = iitlbp r1,(sr1,rp) +0x04,0x41,0x42,0x00 = pitlb r1(sr1,rp) +0x04,0x41,0x42,0x40 = pitlbe r1(sr1,rp) +0x04,0x41,0x42,0x80 = fic r1(sr1,rp) +0x04,0x41,0x42,0xa0 = fic,m r1(sr1,rp) +0x04,0x41,0x42,0xc0 = fice r1(sr1,rp) +0x04,0x41,0x42,0xe0 = fice,m r1(sr1,rp) +0x04,0x41,0x50,0x40 = idtlba r1,(sr1,rp) +0x04,0x41,0x50,0x00 = idtlbp r1,(sr1,rp) +0x04,0x41,0x52,0x00 = pdtlb r1(sr1,rp) +0x04,0x41,0x52,0x40 = pdtlbe r1(sr1,rp) +0x04,0x41,0x52,0x80 = fdc r1(sr1,rp) +0x04,0x41,0x52,0xa0 = fdc,m r1(sr1,rp) +0x04,0x41,0x52,0xc0 = fdce r1(sr1,rp) +0x04,0x41,0x52,0xe0 = fdce,m r1(sr1,rp) +0x04,0x41,0x53,0x80 = pdc r1(sr1,rp) +0x04,0x41,0x53,0xa0 = pdc,m r1(sr1,rp) +0x04,0x22,0x51,0x83 = prober (sr1,r1),rp,r3 +0x04,0x30,0x71,0x83 = proberi (sr1,r1),0x10,r3 +0x04,0x22,0x51,0xc3 = probew (sr1,r1),rp,r3 +0x04,0x30,0x71,0xc3 = probewi (sr1,r1),0x10,r3 +0x04,0x41,0x53,0x43 = lpa r1(sr1,rp),r3 +0x04,0x41,0x53,0x03 = lci r1(sr1,rp),r3 \ No newline at end of file diff --git a/suite/MC/HPPA/memory_reference20.s.cs b/suite/MC/HPPA/memory_reference20.s.cs new file mode 100644 index 0000000000..29ebc8dfea --- /dev/null +++ b/suite/MC/HPPA/memory_reference20.s.cs @@ -0,0 +1,99 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x0c,0x41,0x40,0x03 = ldb r1(sr1,rp),r3 +0x0c,0x41,0x60,0x03 = ldb,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0x23 = ldb,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0x23 = ldb,m r1(sr1,rp),r3 +0x0c,0x51,0x50,0x03 = ldb -8(sr1,rp),r3 +0x0c,0x51,0x50,0x23 = ldb,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0x23 = ldb,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0x03 = ldb,sl 8(sr1,rp),r3 +0x0c,0x41,0x40,0x43 = ldh r1(sr1,rp),r3 +0x0c,0x41,0x60,0x43 = ldh,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0x63 = ldh,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0x63 = ldh,m r1(sr1,rp),r3 +0x44,0x43,0x41,0xbc = ldh 0xde(sr1,rp),r3 +0x0c,0x51,0x50,0x63 = ldh,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0x63 = ldh,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0x43 = ldh,sl 8(sr1,rp),r3 +0x0c,0x41,0x40,0x83 = ldw r1(sr1,rp),r3 +0x0c,0x41,0x60,0x83 = ldw,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0xa3 = ldw,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0xa3 = ldw,m r1(sr1,rp),r3 +0x48,0x43,0x41,0xbc = ldw 0xde(sr1,rp),r3 +0x0c,0x51,0x50,0xa3 = ldw,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0xa3 = ldw,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0x83 = ldw,sl 8(sr1,rp),r3 +0x0c,0x41,0x40,0xc3 = ldd r1(sr1,rp),r3 +0x0c,0x41,0x60,0xc3 = ldd,s r1(sr1,rp),r3 +0x0c,0x41,0x60,0xe3 = ldd,sm r1(sr1,rp),r3 +0x0c,0x41,0x40,0xe3 = ldd,m r1(sr1,rp),r3 +0x0c,0x51,0x50,0xc3 = ldd -8(sr1,rp),r3 +0x0c,0x51,0x50,0xe3 = ldd,ma -8(sr1,rp),r3 +0x0c,0x51,0x70,0xe3 = ldd,mb -8(sr1,rp),r3 +0x0c,0x50,0x58,0xc3 = ldd,sl 8(sr1,rp),r3 +0x60,0x21,0xbf,0xb1 = stb r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0x31 = stb,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0x31 = stb,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0x20 = stb,o r1,0(sr2,r1) +0x64,0x21,0xbf,0xb1 = sth r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0x71 = sth,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0x71 = sth,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0x60 = sth,o r1,0(sr2,r1) +0x68,0x21,0xbf,0xb1 = stw r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0xb1 = stw,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0xb1 = stw,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0xa0 = stw,o r1,0(sr2,r1) +0x70,0x21,0xbf,0xb1 = std r1,-0x28(sr2,r1) +0x0c,0x21,0x92,0xf1 = std,ma r1,-8(sr2,r1) +0x0c,0x21,0xb2,0xf1 = std,mb r1,-8(sr2,r1) +0x0c,0x21,0x92,0xe0 = std,o r1,0(sr2,r1) +0x0c,0x41,0x01,0x83 = ldwa r1(rp),r3 +0x0c,0x41,0x21,0x83 = ldwa,s r1(rp),r3 +0x0c,0x41,0x21,0xa3 = ldwa,sm r1(rp),r3 +0x0c,0x41,0x01,0xa3 = ldwa,m r1(rp),r3 +0x0c,0x51,0x11,0x83 = ldwa -8(rp),r3 +0x0c,0x51,0x11,0xa3 = ldwa,ma -8(rp),r3 +0x0c,0x51,0x31,0xa3 = ldwa,mb -8(rp),r3 +0x0c,0x50,0x19,0x83 = ldwa,sl 8(rp),r3 +0x0c,0x40,0x11,0xa3 = ldwa,o 0(rp),r3 +0x0c,0x41,0x01,0x03 = ldda r1(rp),r3 +0x0c,0x41,0x21,0x03 = ldda,s r1(rp),r3 +0x0c,0x41,0x21,0x23 = ldda,sm r1(rp),r3 +0x0c,0x41,0x01,0x23 = ldda,m r1(rp),r3 +0x0c,0x51,0x11,0x03 = ldda -8(rp),r3 +0x0c,0x51,0x11,0x23 = ldda,ma -8(rp),r3 +0x0c,0x51,0x31,0x23 = ldda,mb -8(rp),r3 +0x0c,0x50,0x19,0x03 = ldda,sl 8(rp),r3 +0x0c,0x40,0x11,0x23 = ldda,o 0(rp),r3 +0x0c,0x21,0x13,0x91 = stwa r1,-8(r1) +0x0c,0x21,0x13,0xb1 = stwa,ma r1,-8(r1) +0x0c,0x21,0x33,0xb1 = stwa,mb r1,-8(r1) +0x0c,0x21,0x13,0xa0 = stwa,o r1,0(r1) +0x0c,0x21,0x13,0xd1 = stda r1,-8(r1) +0x0c,0x21,0x13,0xf1 = stda,ma r1,-8(r1) +0x0c,0x21,0x33,0xf1 = stda,mb r1,-8(r1) +0x0c,0x21,0x13,0xe0 = stda,o r1,0(r1) +0x0c,0x41,0x41,0xc3 = ldcw r1(sr1,rp),r3 +0x0c,0x41,0x61,0xc3 = ldcw,s r1(sr1,rp),r3 +0x0c,0x41,0x61,0xe3 = ldcw,sm r1(sr1,rp),r3 +0x0c,0x41,0x41,0xe3 = ldcw,m r1(sr1,rp),r3 +0x0c,0x51,0x51,0xc3 = ldcw -8(sr1,rp),r3 +0x0c,0x51,0x51,0xe3 = ldcw,ma -8(sr1,rp),r3 +0x0c,0x51,0x71,0xe3 = ldcw,mb -8(sr1,rp),r3 +0x0c,0x40,0x55,0xc3 = ldcw,co 0(sr1,rp),r3 +0x0c,0x41,0x41,0x43 = ldcd r1(sr1,rp),r3 +0x0c,0x41,0x61,0x43 = ldcd,s r1(sr1,rp),r3 +0x0c,0x41,0x61,0x63 = ldcd,sm r1(sr1,rp),r3 +0x0c,0x41,0x41,0x63 = ldcd,m r1(sr1,rp),r3 +0x0c,0x51,0x51,0x43 = ldcd -8(sr1,rp),r3 +0x0c,0x51,0x51,0x63 = ldcd,ma -8(sr1,rp),r3 +0x0c,0x51,0x71,0x63 = ldcd,mb -8(sr1,rp),r3 +0x0c,0x40,0x55,0x43 = ldcd,co 0(sr1,rp),r3 +0x0c,0x41,0x53,0x11 = stby r1,-8(sr1,rp) +0x0c,0x41,0x53,0x31 = stby,b,m r1,-8(sr1,rp) +0x0c,0x41,0x73,0x11 = stby,e r1,-8(sr1,rp) +0x0c,0x41,0x73,0x31 = stby,e,m r1,-8(sr1,rp) +0x0c,0x41,0x53,0x51 = stdby r1,-8(sr1,rp) +0x0c,0x41,0x53,0x71 = stdby,b,m r1,-8(sr1,rp) +0x0c,0x41,0x73,0x51 = stdby,e r1,-8(sr1,rp) +0x0c,0x41,0x73,0x71 = stdby,e,m r1,-8(sr1,rp) \ No newline at end of file diff --git a/suite/MC/HPPA/multimedia20.s.cs b/suite/MC/HPPA/multimedia20.s.cs new file mode 100644 index 0000000000..e83873364d --- /dev/null +++ b/suite/MC/HPPA/multimedia20.s.cs @@ -0,0 +1,14 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x08,0x41,0x03,0xc3 = hadd r1,rp,r3 +0x08,0x41,0x03,0x43 = hadd,ss r1,rp,r3 +0x08,0x41,0x03,0x03 = hadd,us r1,rp,r3 +0x08,0x41,0x01,0xc3 = hsub r1,rp,r3 +0x08,0x41,0x01,0x43 = hsub,ss r1,rp,r3 +0x08,0x41,0x01,0x03 = hsub,us r1,rp,r3 +0x08,0x41,0x02,0xc3 = havg r1,rp,r3 +0x08,0x41,0x07,0xc3 = hshladd r1,3,rp,r3 +0x08,0x41,0x05,0xc3 = hshradd r1,3,rp,r3 +0xf8,0x01,0x88,0xc2 = hshl r1,3,rp +0xf8,0x20,0xcc,0xc2 = hshr,s r1,3,rp +0xf8,0x21,0x00,0x02 = permh,0000 r1,rp +0xf8,0x21,0x06,0xc2 = permh,0123 r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/no_grp11.s.cs b/suite/MC/HPPA/no_grp11.s.cs new file mode 100644 index 0000000000..508f271328 --- /dev/null +++ b/suite/MC/HPPA/no_grp11.s.cs @@ -0,0 +1,109 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x14,0x00,0x00,0x01 = diag 1 +0x18,0x22,0x29,0x03 = fmpyadd,dbl fpe2,fpe4,fpe6,fr4,fr5 +0x20,0x39,0x00,0x00 = ldil 0x32000,r1 +0x28,0x39,0x00,0x00 = addil 0x32000,r1 +0x34,0x22,0x00,0x1e = ldo 0xf(r1),rp +0x0c,0x3e,0x50,0x02 = ldbs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x42 = ldhs 0xf(sr1,r1),rp +0x0c,0x3e,0x50,0x82 = ldws 0xf(sr1,r1),rp +0x4c,0x22,0x40,0x1e = ldwm 0xf(sr1,r1),rp +0x0c,0x41,0x12,0x1e = stbs r1,0xf(rp) +0x0c,0x41,0x12,0x5e = sths r1,0xf(rp) +0x0c,0x41,0x12,0x9e = stws r1,0xf(rp) +0x6c,0x41,0x00,0x1e = stwm r1,0xf(rp) +0x80,0x41,0x1f,0x0d = combt r1,rp,0xffffffffffffff8c +0x80,0x41,0x3f,0x05 = combt,= r1,rp,0xffffffffffffff88 +0x80,0x41,0x5e,0xfd = combt,< r1,rp,0xffffffffffffff84 +0x80,0x41,0x7e,0xf5 = combt,<= r1,rp,0xffffffffffffff80 +0x80,0x41,0x9e,0xed = combt,<< r1,rp,0xffffffffffffff7c +0x80,0x41,0xbe,0xe5 = combt,<<= r1,rp,0xffffffffffffff78 +0x80,0x41,0xde,0xdd = combt,sv r1,rp,0xffffffffffffff74 +0x80,0x41,0xfe,0xd5 = combt,od r1,rp,0xffffffffffffff70 +0x84,0x5e,0x1e,0xcd = comibt 0xf,rp,0xffffffffffffff6c +0x84,0x5e,0x3e,0xc5 = comibt,= 0xf,rp,0xffffffffffffff68 +0x84,0x5e,0x5e,0xbd = comibt,< 0xf,rp,0xffffffffffffff64 +0x84,0x5e,0x7e,0xb5 = comibt,<= 0xf,rp,0xffffffffffffff60 +0x84,0x5e,0x9e,0xad = comibt,<< 0xf,rp,0xffffffffffffff5c +0x84,0x5e,0xbe,0xa5 = comibt,<<= 0xf,rp,0xffffffffffffff58 +0x84,0x5e,0xde,0x9d = comibt,sv 0xf,rp,0xffffffffffffff54 +0x84,0x5e,0xfe,0x95 = comibt,od 0xf,rp,0xffffffffffffff50 +0x88,0x41,0x1e,0x8d = combf r1,rp,0xffffffffffffff4c +0x88,0x41,0x3e,0x85 = combf,= r1,rp,0xffffffffffffff48 +0x88,0x41,0x5e,0x7d = combf,< r1,rp,0xffffffffffffff44 +0x88,0x41,0x7e,0x75 = combf,<= r1,rp,0xffffffffffffff40 +0x88,0x41,0x9e,0x6d = combf,<< r1,rp,0xffffffffffffff3c +0x88,0x41,0xbe,0x65 = combf,<<= r1,rp,0xffffffffffffff38 +0x88,0x41,0xde,0x5d = combf,sv r1,rp,0xffffffffffffff34 +0x88,0x41,0xfe,0x55 = combf,od r1,rp,0xffffffffffffff30 +0x8c,0x5e,0x1e,0x4d = comibf 0xf,rp,0xffffffffffffff2c +0x8c,0x5e,0x3e,0x45 = comibf,= 0xf,rp,0xffffffffffffff28 +0x8c,0x5e,0x5e,0x3d = comibf,< 0xf,rp,0xffffffffffffff24 +0x8c,0x5e,0x7e,0x35 = comibf,<= 0xf,rp,0xffffffffffffff20 +0x8c,0x5e,0x9e,0x2d = comibf,<< 0xf,rp,0xffffffffffffff1c +0x8c,0x5e,0xbe,0x25 = comibf,<<= 0xf,rp,0xffffffffffffff18 +0x8c,0x5e,0xde,0x1d = comibf,sv 0xf,rp,0xffffffffffffff14 +0x8c,0x5e,0xfe,0x15 = comibf,od 0xf,rp,0xffffffffffffff10 +0x90,0x41,0x00,0x1e = comiclr 0xf,rp,r1 +0x90,0x41,0x20,0x1e = comiclr,= 0xf,rp,r1 +0x90,0x41,0x40,0x1e = comiclr,< 0xf,rp,r1 +0x90,0x41,0x60,0x1e = comiclr,<= 0xf,rp,r1 +0x90,0x41,0x80,0x1e = comiclr,<< 0xf,rp,r1 +0x90,0x41,0xa0,0x1e = comiclr,<<= 0xf,rp,r1 +0x90,0x41,0xc0,0x1e = comiclr,sv 0xf,rp,r1 +0x90,0x41,0xe0,0x1e = comiclr,od 0xf,rp,r1 +0x98,0x22,0x29,0x03 = fmpysub,dbl fpe2,fpe4,fpe6,fr4,fr5 +0xa0,0x41,0x1d,0xc5 = addbt r1,rp,0xfffffffffffffee8 +0xa0,0x41,0x3d,0xbd = addbt,= r1,rp,0xfffffffffffffee4 +0xa0,0x41,0x5d,0xb5 = addbt,< r1,rp,0xfffffffffffffee0 +0xa0,0x41,0x7d,0xad = addbt,<= r1,rp,0xfffffffffffffedc +0xa0,0x41,0x9d,0xa7 = addbt,nuv,n r1,rp,0xfffffffffffffed8 +0xa0,0x41,0xbd,0x9f = addbt,znv,n r1,rp,0xfffffffffffffed4 +0xa0,0x41,0xdd,0x95 = addbt,sv r1,rp,0xfffffffffffffed0 +0xa0,0x41,0xfd,0x8d = addbt,od r1,rp,0xfffffffffffffecc +0xa4,0x5e,0x1d,0x85 = addibt 0xf,rp,0xfffffffffffffec8 +0xa4,0x5e,0x3d,0x7d = addibt,= 0xf,rp,0xfffffffffffffec4 +0xa4,0x5e,0x5d,0x75 = addibt,< 0xf,rp,0xfffffffffffffec0 +0xa4,0x5e,0x7d,0x6d = addibt,<= 0xf,rp,0xfffffffffffffebc +0xa4,0x5e,0x9d,0x67 = addibt,nuv,n 0xf,rp,0xfffffffffffffeb8 +0xa4,0x5e,0xbd,0x5f = addibt,znv,n 0xf,rp,0xfffffffffffffeb4 +0xa4,0x5e,0xdd,0x55 = addibt,sv 0xf,rp,0xfffffffffffffeb0 +0xa4,0x5e,0xfd,0x4d = addibt,od 0xf,rp,0xfffffffffffffeac +0xa8,0x41,0x1d,0x45 = addbf r1,rp,0xfffffffffffffea8 +0xa8,0x41,0x3d,0x3d = addbf,= r1,rp,0xfffffffffffffea4 +0xa8,0x41,0x5d,0x35 = addbf,< r1,rp,0xfffffffffffffea0 +0xa8,0x41,0x7d,0x2d = addbf,<= r1,rp,0xfffffffffffffe9c +0xa8,0x41,0x9d,0x27 = addbf,nuv,n r1,rp,0xfffffffffffffe98 +0xa8,0x41,0xbd,0x1f = addbf,znv,n r1,rp,0xfffffffffffffe94 +0xa8,0x41,0xdd,0x15 = addbf,sv r1,rp,0xfffffffffffffe90 +0xa8,0x41,0xfd,0x0d = addbf,od r1,rp,0xfffffffffffffe8c +0xac,0x5e,0x1d,0x05 = addibf 0xf,rp,0xfffffffffffffe88 +0xac,0x5e,0x3c,0xfd = addibf,= 0xf,rp,0xfffffffffffffe84 +0xac,0x5e,0x5c,0xf5 = addibf,< 0xf,rp,0xfffffffffffffe80 +0xac,0x5e,0x7c,0xed = addibf,<= 0xf,rp,0xfffffffffffffe7c +0xac,0x5e,0x9c,0xe7 = addibf,nuv,n 0xf,rp,0xfffffffffffffe78 +0xac,0x5e,0xbc,0xdf = addibf,znv,n 0xf,rp,0xfffffffffffffe74 +0xac,0x5e,0xdc,0xd5 = addibf,sv 0xf,rp,0xfffffffffffffe70 +0xac,0x5e,0xfc,0xcd = addibf,od 0xf,rp,0xfffffffffffffe6c +0xc0,0x01,0x5c,0xc7 = bvb,<,n r1,0xfffffffffffffe68 +0xc0,0x01,0xdc,0xbf = bvb,>=,n r1,0xfffffffffffffe64 +0xc4,0x61,0x5c,0xb7 = bb,<,n r1,3,0xfffffffffffffe60 +0xc4,0x61,0xdc,0xaf = bb,>=,n r1,3,0xfffffffffffffe5c +0xc8,0x41,0x1c,0xa7 = movb,n r1,rp,0xfffffffffffffe58 +0xc8,0x41,0x3c,0x9d = movb,= r1,rp,0xfffffffffffffe54 +0xc8,0x41,0x5c,0x95 = movb,< r1,rp,0xfffffffffffffe50 +0xc8,0x41,0x7c,0x8d = movb,od r1,rp,0xfffffffffffffe4c +0xc8,0x41,0x9c,0x85 = movb,tr r1,rp,0xfffffffffffffe48 +0xc8,0x41,0xbc,0x7d = movb,<> r1,rp,0xfffffffffffffe44 +0xc8,0x41,0xdc,0x75 = movb,>= r1,rp,0xfffffffffffffe40 +0xc8,0x41,0xfc,0x6d = movb,ev r1,rp,0xfffffffffffffe3c +0xcc,0x5e,0x1c,0x67 = movib,n 0xf,rp,0xfffffffffffffe38 +0xcc,0x5e,0x3c,0x5d = movib,= 0xf,rp,0xfffffffffffffe34 +0xcc,0x5e,0x5c,0x55 = movib,< 0xf,rp,0xfffffffffffffe30 +0xcc,0x5e,0x7c,0x4d = movib,od 0xf,rp,0xfffffffffffffe2c +0xcc,0x5e,0x9c,0x45 = movib,tr 0xf,rp,0xfffffffffffffe28 +0xcc,0x5e,0xbc,0x3d = movib,<> 0xf,rp,0xfffffffffffffe24 +0xcc,0x5e,0xdc,0x35 = movib,>= 0xf,rp,0xfffffffffffffe20 +0xcc,0x5e,0xfc,0x2d = movib,ev 0xf,rp,0xfffffffffffffe1c +0xe0,0x20,0x42,0x02 = be,n 0x100(sr1,r1) +0xe4,0x20,0x42,0x02 = ble,n 0x100(sr1,r1) \ No newline at end of file diff --git a/suite/MC/HPPA/sfu11.s.cs b/suite/MC/HPPA/sfu11.s.cs new file mode 100644 index 0000000000..93cd5efe05 --- /dev/null +++ b/suite/MC/HPPA/sfu11.s.cs @@ -0,0 +1,5 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x10,0x00,0x00,0xa3 = spop0,2,3,n +0x10,0x00,0x1a,0xa1 = spop1,2,3,n r1 +0x10,0x20,0x04,0xa3 = spop2,2,3,n r1 +0x10,0x41,0x06,0xa3 = spop3,2,3,n r1,rp \ No newline at end of file diff --git a/suite/MC/HPPA/shexdep11.s.cs b/suite/MC/HPPA/shexdep11.s.cs new file mode 100644 index 0000000000..f62164d49f --- /dev/null +++ b/suite/MC/HPPA/shexdep11.s.cs @@ -0,0 +1,225 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0xd0,0x41,0x00,0x03 = vshd r1,rp,r3 +0xd0,0x41,0x20,0x03 = vshd,= r1,rp,r3 +0xd0,0x41,0x40,0x03 = vshd,< r1,rp,r3 +0xd0,0x41,0x60,0x03 = vshd,od r1,rp,r3 +0xd0,0x41,0x80,0x03 = vshd,tr r1,rp,r3 +0xd0,0x41,0xa0,0x03 = vshd,<> r1,rp,r3 +0xd0,0x41,0xc0,0x03 = vshd,>= r1,rp,r3 +0xd0,0x41,0xe0,0x03 = vshd,ev r1,rp,r3 +0xd0,0x41,0x0a,0x03 = shd r1,rp,0xf,r3 +0xd0,0x41,0x2a,0x03 = shd,= r1,rp,0xf,r3 +0xd0,0x41,0x4a,0x03 = shd,< r1,rp,0xf,r3 +0xd0,0x41,0x6a,0x03 = shd,od r1,rp,0xf,r3 +0xd0,0x41,0x8a,0x03 = shd,tr r1,rp,0xf,r3 +0xd0,0x41,0xaa,0x03 = shd,<> r1,rp,0xf,r3 +0xd0,0x41,0xca,0x03 = shd,>= r1,rp,0xf,r3 +0xd0,0x41,0xea,0x03 = shd,ev r1,rp,0xf,r3 +0xd0,0x23,0x10,0x11 = vextru r1,0xf,r3 +0xd0,0x23,0x30,0x11 = vextru,= r1,0xf,r3 +0xd0,0x23,0x50,0x11 = vextru,< r1,0xf,r3 +0xd0,0x23,0x70,0x11 = vextru,od r1,0xf,r3 +0xd0,0x23,0x90,0x11 = vextru,tr r1,0xf,r3 +0xd0,0x23,0xb0,0x11 = vextru,<> r1,0xf,r3 +0xd0,0x23,0xd0,0x11 = vextru,>= r1,0xf,r3 +0xd0,0x23,0xf0,0x11 = vextru,ev r1,0xf,r3 +0xd0,0x23,0x14,0x11 = vextrs r1,0xf,r3 +0xd0,0x23,0x34,0x11 = vextrs,= r1,0xf,r3 +0xd0,0x23,0x54,0x11 = vextrs,< r1,0xf,r3 +0xd0,0x23,0x74,0x11 = vextrs,od r1,0xf,r3 +0xd0,0x23,0x94,0x11 = vextrs,tr r1,0xf,r3 +0xd0,0x23,0xb4,0x11 = vextrs,<> r1,0xf,r3 +0xd0,0x23,0xd4,0x11 = vextrs,>= r1,0xf,r3 +0xd0,0x23,0xf4,0x11 = vextrs,ev r1,0xf,r3 +0xd0,0x23,0x19,0xd1 = extru r1,0xe,0xf,r3 +0xd0,0x23,0x39,0xd1 = extru,= r1,0xe,0xf,r3 +0xd0,0x23,0x59,0xd1 = extru,< r1,0xe,0xf,r3 +0xd0,0x23,0x79,0xd1 = extru,od r1,0xe,0xf,r3 +0xd0,0x23,0x99,0xd1 = extru,tr r1,0xe,0xf,r3 +0xd0,0x23,0xb9,0xd1 = extru,<> r1,0xe,0xf,r3 +0xd0,0x23,0xd9,0xd1 = extru,>= r1,0xe,0xf,r3 +0xd0,0x23,0xf9,0xd1 = extru,ev r1,0xe,0xf,r3 +0xd0,0x23,0x1d,0xd1 = extrs r1,0xe,0xf,r3 +0xd0,0x23,0x3d,0xd1 = extrs,= r1,0xe,0xf,r3 +0xd0,0x23,0x5d,0xd1 = extrs,< r1,0xe,0xf,r3 +0xd0,0x23,0x7d,0xd1 = extrs,od r1,0xe,0xf,r3 +0xd0,0x23,0x9d,0xd1 = extrs,tr r1,0xe,0xf,r3 +0xd0,0x23,0xbd,0xd1 = extrs,<> r1,0xe,0xf,r3 +0xd0,0x23,0xdd,0xd1 = extrs,>= r1,0xe,0xf,r3 +0xd0,0x23,0xfd,0xd1 = extrs,ev r1,0xe,0xf,r3 +0xd4,0x61,0x00,0x11 = zvdep r1,0xf,r3 +0xd4,0x61,0x20,0x11 = zvdep,= r1,0xf,r3 +0xd4,0x61,0x40,0x11 = zvdep,< r1,0xf,r3 +0xd4,0x61,0x60,0x11 = zvdep,od r1,0xf,r3 +0xd4,0x61,0x80,0x11 = zvdep,tr r1,0xf,r3 +0xd4,0x61,0xa0,0x11 = zvdep,<> r1,0xf,r3 +0xd4,0x61,0xc0,0x11 = zvdep,>= r1,0xf,r3 +0xd4,0x61,0xe0,0x11 = zvdep,ev r1,0xf,r3 +0xd4,0x61,0x04,0x11 = vdep r1,0xf,r3 +0xd4,0x61,0x24,0x11 = vdep,= r1,0xf,r3 +0xd4,0x61,0x44,0x11 = vdep,< r1,0xf,r3 +0xd4,0x61,0x64,0x11 = vdep,od r1,0xf,r3 +0xd4,0x61,0x84,0x11 = vdep,tr r1,0xf,r3 +0xd4,0x61,0xa4,0x11 = vdep,<> r1,0xf,r3 +0xd4,0x61,0xc4,0x11 = vdep,>= r1,0xf,r3 +0xd4,0x61,0xe4,0x11 = vdep,ev r1,0xf,r3 +0xd4,0x61,0x0a,0x31 = zdep r1,0xe,0xf,r3 +0xd4,0x61,0x2a,0x31 = zdep,= r1,0xe,0xf,r3 +0xd4,0x61,0x4a,0x31 = zdep,< r1,0xe,0xf,r3 +0xd4,0x61,0x6a,0x31 = zdep,od r1,0xe,0xf,r3 +0xd4,0x61,0x8a,0x31 = zdep,tr r1,0xe,0xf,r3 +0xd4,0x61,0xaa,0x31 = zdep,<> r1,0xe,0xf,r3 +0xd4,0x61,0xca,0x31 = zdep,>= r1,0xe,0xf,r3 +0xd4,0x61,0xea,0x31 = zdep,ev r1,0xe,0xf,r3 +0xd4,0x61,0x0e,0x31 = dep r1,0xe,0xf,r3 +0xd4,0x61,0x2e,0x31 = dep,= r1,0xe,0xf,r3 +0xd4,0x61,0x4e,0x31 = dep,< r1,0xe,0xf,r3 +0xd4,0x61,0x6e,0x31 = dep,od r1,0xe,0xf,r3 +0xd4,0x61,0x8e,0x31 = dep,tr r1,0xe,0xf,r3 +0xd4,0x61,0xae,0x31 = dep,<> r1,0xe,0xf,r3 +0xd4,0x61,0xce,0x31 = dep,>= r1,0xe,0xf,r3 +0xd4,0x61,0xee,0x31 = dep,ev r1,0xe,0xf,r3 +0xd4,0x7c,0x10,0x11 = zvdepi 0xe,0xf,r3 +0xd4,0x7c,0x30,0x11 = zvdepi,= 0xe,0xf,r3 +0xd4,0x7c,0x50,0x11 = zvdepi,< 0xe,0xf,r3 +0xd4,0x7c,0x70,0x11 = zvdepi,od 0xe,0xf,r3 +0xd4,0x7c,0x90,0x11 = zvdepi,tr 0xe,0xf,r3 +0xd4,0x7c,0xb0,0x11 = zvdepi,<> 0xe,0xf,r3 +0xd4,0x7c,0xd0,0x11 = zvdepi,>= 0xe,0xf,r3 +0xd4,0x7c,0xf0,0x11 = zvdepi,ev 0xe,0xf,r3 +0xd4,0x7c,0x14,0x11 = vdepi 0xe,0xf,r3 +0xd4,0x7c,0x34,0x11 = vdepi,= 0xe,0xf,r3 +0xd4,0x7c,0x54,0x11 = vdepi,< 0xe,0xf,r3 +0xd4,0x7c,0x74,0x11 = vdepi,od 0xe,0xf,r3 +0xd4,0x7c,0x94,0x11 = vdepi,tr 0xe,0xf,r3 +0xd4,0x7c,0xb4,0x11 = vdepi,<> 0xe,0xf,r3 +0xd4,0x7c,0xd4,0x11 = vdepi,>= 0xe,0xf,r3 +0xd4,0x7c,0xf4,0x11 = vdepi,ev 0xe,0xf,r3 +0xd4,0x66,0x1b,0xbf = zdepi 3,2,1,r3 +0xd4,0x66,0x3b,0xbf = zdepi,= 3,2,1,r3 +0xd4,0x66,0x5b,0xbf = zdepi,< 3,2,1,r3 +0xd4,0x66,0x7b,0xbf = zdepi,od 3,2,1,r3 +0xd4,0x66,0x9b,0xbf = zdepi,tr 3,2,1,r3 +0xd4,0x66,0xbb,0xbf = zdepi,<> 3,2,1,r3 +0xd4,0x66,0xdb,0xbf = zdepi,>= 3,2,1,r3 +0xd4,0x66,0xfb,0xbf = zdepi,ev 3,2,1,r3 +0xd4,0x66,0x1f,0xbf = depi 3,2,1,r3 +0xd4,0x66,0x3f,0xbf = depi,= 3,2,1,r3 +0xd4,0x66,0x5f,0xbf = depi,< 3,2,1,r3 +0xd4,0x66,0x7f,0xbf = depi,od 3,2,1,r3 +0xd4,0x66,0x9f,0xbf = depi,tr 3,2,1,r3 +0xd4,0x66,0xbf,0xbf = depi,<> 3,2,1,r3 +0xd4,0x66,0xdf,0xbf = depi,>= 3,2,1,r3 +0xd4,0x66,0xff,0xbf = depi,ev 3,2,1,r3 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/suite/MC/HPPA/sysctrl20.s.cs b/suite/MC/HPPA/sysctrl20.s.cs new file mode 100644 index 0000000000..f6cd850e35 --- /dev/null +++ b/suite/MC/HPPA/sysctrl20.s.cs @@ -0,0 +1,49 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN, None +0x00,0x20,0x50,0xa2 = ldsid (sr1,r1),rp +0x00,0x01,0x58,0x20 = mtsp r1,sr1 +0x00,0x00,0x44,0xa1 = mfsp sr1,r1 +0x00,0x41,0x18,0x40 = mtctl r1,cr2 +0x00,0x20,0x08,0xa2 = mfctl cr1,rp +0x01,0x60,0x48,0xa1 = mfctl,w sar,r1 +0x01,0x61,0x18,0xc0 = mtsarcm r1 +0x00,0x00,0x14,0xa1 = mfia r1 +0x00,0x0f,0x0d,0x61 = ssm 0xf,r1 +0x00,0x0f,0x0e,0x61 = rsm 0xf,r1 +0x00,0x01,0x18,0x60 = mtsm r1 +0x00,0x00,0x0c,0x00 = rfi +0x00,0x00,0x0c,0xa0 = rfi,r +0x03,0xff,0xc0,0x1f = break 0x1f,0x1ffe +0x00,0x00,0x04,0x00 = sync +0x00,0x10,0x04,0x00 = syncdma +0x04,0x22,0x51,0x83 = probe,r (sr1,r1),rp,r3 +0x04,0x22,0x51,0xc3 = probe,w (sr1,r1),rp,r3 +0x04,0x22,0x51,0x83 = probe,r (sr1,r1),rp,r3 +0x04,0x2f,0x71,0x83 = probei,r (sr1,r1),0xf,r3 +0x04,0x2f,0x71,0xc3 = probei,w (sr1,r1),0xf,r3 +0x04,0x2f,0x71,0x83 = probei,r (sr1,r1),0xf,r3 +0x04,0x41,0x53,0x43 = lpa r1(sr1,rp),r3 +0x04,0x41,0x53,0x63 = lpa,m r1(sr1,rp),r3 +0x04,0x41,0x53,0x03 = lci r1(sr1,rp),r3 +0x04,0x41,0x12,0x00 = pdtlb r1(rp) +0x04,0x41,0x16,0x00 = pdtlb,l r1(rp) +0x04,0x41,0x16,0x20 = pdtlb,l,m r1(rp) +0x04,0x41,0x42,0x00 = pitlb r1(sr1,rp) +0x04,0x41,0x46,0x00 = pitlb,l r1(sr1,rp) +0x04,0x41,0x46,0x20 = pitlb,l,m r1(sr1,rp) +0x04,0x41,0x12,0x40 = pdtlbe r1(rp) +0x04,0x41,0x12,0x60 = pdtlbe,m r1(rp) +0x04,0x41,0x42,0x40 = pitlbe r1(sr1,rp) +0x04,0x41,0x42,0x60 = pitlbe,m r1(sr1,rp) +0x04,0x41,0x18,0x00 = idtlbt r1,rp +0x04,0x41,0x08,0x00 = iitlbt r1,rp +0x04,0x41,0x13,0x80 = pdc r1(rp) +0x04,0x41,0x13,0xa0 = pdc,m r1(rp) +0x04,0x41,0x52,0x80 = fdc r1(sr1,rp) +0x04,0x41,0x52,0xa0 = fdc,m r1(sr1,rp) +0x04,0x5e,0x72,0x80 = fdc 0xf(sr1,rp) +0x04,0x41,0x42,0x80 = fic r1(sr1,rp) +0x04,0x41,0x52,0xc0 = fdce r1(sr1,rp) +0x04,0x41,0x52,0xe0 = fdce,m r1(sr1,rp) +0x04,0x41,0x42,0xc0 = fice r1(sr1,rp) +0x04,0x41,0x42,0xe0 = fice,m r1(sr1,rp) +0x14,0x00,0xde,0xad = diag 0xdead \ No newline at end of file diff --git a/suite/MC/HPPA/system_op11.s.cs b/suite/MC/HPPA/system_op11.s.cs new file mode 100644 index 0000000000..99b362fa5e --- /dev/null +++ b/suite/MC/HPPA/system_op11.s.cs @@ -0,0 +1,14 @@ +# CS_ARCH_HPPA, CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN, None +0x00,0x00,0x20,0x01 = break 1,1 +0x00,0x00,0x04,0x00 = sync +0x00,0x10,0x04,0x00 = syncdma +0x00,0x00,0x0c,0x00 = rfi +0x00,0x00,0x0c,0xa0 = rfir +0x00,0x1e,0x0d,0x61 = ssm 0x1e,r1 +0x00,0x1e,0x0e,0x61 = rsm 0x1e,r1 +0x00,0x01,0x18,0x60 = mtsm r1 +0x00,0x20,0x50,0xa2 = ldsid (sr1,r1),rp +0x00,0x00,0x58,0x20 = mtsp flags,sr1 +0x00,0x00,0x44,0xa0 = mfsp sr1,flags +0x00,0x00,0x18,0x40 = mtctl flags,rctr +0x00,0x00,0x18,0x40 = mtctl flags,rctr \ No newline at end of file diff --git a/suite/capstone_get_setup.c b/suite/capstone_get_setup.c index 2d3f6a6bba..d3154ad288 100644 --- a/suite/capstone_get_setup.c +++ b/suite/capstone_get_setup.c @@ -76,6 +76,9 @@ int main() if (cs_support(CS_ARCH_ALPHA)) { printf("alpha=1 "); } + if (cs_support(CS_ARCH_HPPA)) { + printf("hppa=1 "); + } printf("\n"); return 0; diff --git a/suite/cstest/include/factory.h b/suite/cstest/include/factory.h index 09906b8c81..0752ff0774 100644 --- a/suite/cstest/include/factory.h +++ b/suite/cstest/include/factory.h @@ -25,5 +25,6 @@ char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins); char *get_detail_alpha(csh *handle, cs_mode mode, cs_insn *ins); +char *get_detail_hppa(csh *handle, cs_mode mode, cs_insn *ins); #endif /* FACTORY_H */ diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c index 16027af0d2..1cb8ae5cf9 100644 --- a/suite/cstest/src/capstone_test.c +++ b/suite/cstest/src/capstone_test.c @@ -198,6 +198,9 @@ int set_function(int arch) case CS_ARCH_ALPHA: function = get_detail_alpha; break; + case CS_ARCH_HPPA: + function = get_detail_hppa; + break; default: return -1; } diff --git a/suite/cstest/src/hppa_detail.c b/suite/cstest/src/hppa_detail.c new file mode 100644 index 0000000000..38bc762c08 --- /dev/null +++ b/suite/cstest/src/hppa_detail.c @@ -0,0 +1,96 @@ +/* Capstone testing regression */ +/* By Dmitry Sibirtsev , 2023 */ + +#include "factory.h" + +char *get_detail_hppa(csh *p_handle, cs_mode mode, cs_insn *ins) +{ + cs_hppa *hppa; + int i; + cs_regs regs_read, regs_write; + uint8_t regs_read_count, regs_write_count; + + char *result; + result = (char *)malloc(sizeof(char)); + result[0] = '\0'; + + if (ins->detail == NULL) + return result; + + csh handle = *p_handle; + + hppa = &(ins->detail->hppa); + + if (hppa->op_count) + add_str(&result, "\top_count: %u\n", hppa->op_count); + + for (i = 0; i < hppa->op_count; i++) { + cs_hppa_op *op = &(hppa->operands[i]); + switch ((int)op->type) { + default: + break; + case HPPA_OP_REG: + add_str(&result, "\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_IMM: + add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n", + i, op->imm); + break; + case HPPA_OP_IDX_REG: + add_str(&result, + "\t\toperands[%u].type: IDX_REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_DISP: + add_str(&result, "\t\toperands[%u].type: DISP = 0x%x\n", + i, op->imm); + break; + case HPPA_OP_MEM: + add_str(&result, "\t\toperands[%u].type: MEM\n", i); + if (op->mem.space != HPPA_OP_INVALID) { + add_str(&result, + "\t\t\toperands[%u].mem.space: REG = %s\n", + i, cs_reg_name(handle, op->mem.space)); + } + add_str(&result, + "\t\t\toperands[%u].mem.base: REG = %s\n", i, + cs_reg_name(handle, op->mem.base)); + break; + case HPPA_OP_TARGET: + add_str(&result, "\t\toperands[%u].type: ", i); + if (op->imm >= 0x8000000000000000) + add_str(&result, "TARGET = -0x%lx\n", -op->imm); + else + add_str(&result, "TARGET = 0x%lx\n", op->imm); + break; + } + + // Print out all registers accessed by this instruction (either implicit or + // explicit) + if (!cs_regs_access(handle, ins, regs_read, ®s_read_count, + regs_write, ®s_write_count)) { + if (regs_read_count) { + add_str(&result, "\tRegisters read:"); + for (i = 0; i < regs_read_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_read[i])); + } + add_str(&result, "\n"); + } + + if (regs_write_count) { + add_str(&result, "\tRegisters modified:"); + for (i = 0; i < regs_write_count; i++) { + add_str(&result, " %s", + cs_reg_name(handle, + regs_write[i])); + } + add_str(&result, "\n"); + } + } + } + + return result; +} diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c index a4a681f2fd..0a02449ec8 100644 --- a/suite/cstest/src/main.c +++ b/suite/cstest/src/main.c @@ -22,6 +22,7 @@ static single_dict arches[] = { {"CS_ARCH_RISCV", CS_ARCH_RISCV}, {"CS_ARCH_TRICORE", CS_ARCH_TRICORE}, {"CS_ARCH_ALPHA", CS_ARCH_ALPHA}, + {"CS_ARCH_HPPA", CS_ARCH_HPPA}, }; static single_dict modes[] = { @@ -71,6 +72,9 @@ static single_dict arches[] = { {"CS_MODE_TRICORE_160", CS_MODE_TRICORE_160}, {"CS_MODE_TRICORE_161", CS_MODE_TRICORE_161}, {"CS_MODE_TRICORE_162", CS_MODE_TRICORE_162}, + {"CS_MODE_HPPA_20", CS_MODE_HPPA_20}, + {"CS_MODE_HPPA_20W", CS_MODE_HPPA_20W}, + {"CS_MODE_HPPA_11", CS_MODE_HPPA_11}, }; static double_dict options[] = { @@ -127,6 +131,9 @@ static single_dict arches[] = { {"CS_MODE_TRICORE_161", CS_OPT_MODE, CS_MODE_TRICORE_161}, {"CS_MODE_TRICORE_162", CS_OPT_MODE, CS_MODE_TRICORE_162}, {"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON}, + {"CS_MODE_HPPA_20", CS_OPT_MODE, CS_MODE_HPPA_20}, + {"CS_MODE_HPPA_20W", CS_OPT_MODE, CS_MODE_HPPA_20W}, + {"CS_MODE_HPPA_11", CS_OPT_MODE, CS_MODE_HPPA_11}, }; static int counter; diff --git a/suite/test_c.sh b/suite/test_c.sh index eacbf3b954..3ba937650f 100755 --- a/suite/test_c.sh +++ b/suite/test_c.sh @@ -24,4 +24,5 @@ ../tests/test_winkernel > /tmp/$1 ../tests/test_x86 > /tmp/$1 ../tests/test_xcore > /tmp/$1 -../tests/test_alpha > /tmp/$1 \ No newline at end of file +../tests/test_alpha > /tmp/$1 +../tests/test_hppa > /tmp/$1 \ No newline at end of file diff --git a/suite/test_corpus.py b/suite/test_corpus.py index c74c971939..8d7daf40b9 100755 --- a/suite/test_corpus.py +++ b/suite/test_corpus.py @@ -34,6 +34,7 @@ def test_file(fname): "CS_ARCH_RISCV": CS_ARCH_RISCV, "CS_ARCH_TRICORE": CS_ARCH_TRICORE, "CS_ARCH_ALPHA": CS_ARCH_ALPHA, + "CS_ARCH_HPPA": CS_ARCH_HPPA, } modes = { @@ -71,6 +72,10 @@ def test_file(fname): "CS_MODE_TRICORE_161": CS_MODE_TRICORE_161, "CS_MODE_TRICORE_162": CS_MODE_TRICORE_162, "CS_MODE_BIG_ENDIAN+CS_MODE_QPX": CS_MODE_BIG_ENDIAN+CS_MODE_QPX, + "CS_MODE_HPPA_11": CS_MODE_HPPA_11, + "CS_MODE_HPPA_20": CS_MODE_HPPA_20, + "CS_MODE_HPPA_20W": CS_MODE_HPPA_20W, + } mc_modes = { @@ -118,6 +123,8 @@ def test_file(fname): ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54, ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55, ("CS_ARCH_ALPHA", "CS_MODE_BIG_ENDIAN"): 56, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58, } #if not option in ('', 'None'): diff --git a/suite/test_corpus3.py b/suite/test_corpus3.py index b3d10f4832..f7a2f29376 100755 --- a/suite/test_corpus3.py +++ b/suite/test_corpus3.py @@ -44,6 +44,7 @@ def test_file(fname): "CS_ARCH_RISCV": CS_ARCH_RISCV, "CS_ARCH_TRICORE": CS_ARCH_TRICORE, "CS_ARCH_ALPHA": CS_ARCH_ALPHA, + "CS_ARCH_HPPA": CS_ARCH_HPPA, } modes = { @@ -81,6 +82,9 @@ def test_file(fname): "CS_MODE_TRICORE_161": CS_MODE_TRICORE_161, "CS_MODE_TRICORE_162": CS_MODE_TRICORE_162, "CS_MODE_BIG_ENDIAN+CS_MODE_QPX": CS_MODE_BIG_ENDIAN+CS_MODE_QPX, + "CS_MODE_HPPA_11": CS_MODE_HPPA_11, + "CS_MODE_HPPA_20": CS_MODE_HPPA_20, + "CS_MODE_HPPA_20W": CS_MODE_HPPA_20W, } mc_modes = { @@ -128,6 +132,8 @@ def test_file(fname): ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN+CS_MODE_QPX"): 54, ("CS_ARCH_ALPHA", "CS_MODE_LITTLE_ENDIAN"): 55, ("CS_ARCH_ALPHA", "CS_MODE_BIG_ENDIAN"): 56, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_11+CS_MODE_BIG_ENDIAN"): 57, + ("CS_ARCH_HPPA", "CS_MODE_HPPA_20+CS_MODE_BIG_ENDIAN"): 58, } # if not option in ('', 'None'): diff --git a/suite/test_python.sh b/suite/test_python.sh index e95aa31a84..5445eb2277 100755 --- a/suite/test_python.sh +++ b/suite/test_python.sh @@ -11,4 +11,5 @@ ../bindings/python/test_ppc.py >> /tmp/$1 ../bindings/python/test_sparc.py >> /tmp/$1 ../bindings/python/test_x86.py >> /tmp/$1 -../bindings/python/test_alpha.py >> /tmp/$1 \ No newline at end of file +../bindings/python/test_alpha.py >> /tmp/$1 +../bindings/python/test_hppa.py >> /tmp/$1 \ No newline at end of file diff --git a/tests/Makefile b/tests/Makefile index f01ff6fc9d..9d44f09cbb 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -141,6 +141,10 @@ ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS))) CFLAGS += -DCAPSTONE_HAS_ALPHA SOURCES += test_alpha.c endif +ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS))) +CFLAGS += -DCAPSTONE_HAS_HPPA +SOURCES += test_hppa.c +endif OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o)) diff --git a/tests/test_all.sh b/tests/test_all.sh index 905d84e5ab..1ff49959bd 100644 --- a/tests/test_all.sh +++ b/tests/test_all.sh @@ -19,4 +19,5 @@ ./test_winkernel ./test_x86 ./test_xcore -./test_alpha \ No newline at end of file +./test_alpha +./test_hppa \ No newline at end of file diff --git a/tests/test_alpha.c b/tests/test_alpha.c index 7edc559bd0..0206f25f66 100644 --- a/tests/test_alpha.c +++ b/tests/test_alpha.c @@ -1,5 +1,5 @@ /* Capstone Disassembler Engine */ -/* By Dmitry Sibirtsev , 2013-2019 */ +/* By Dmitry Sibirtsev , 2023 */ #include diff --git a/tests/test_basic.c b/tests/test_basic.c index db57f00021..dbd37a9ffd 100644 --- a/tests/test_basic.c +++ b/tests/test_basic.c @@ -94,6 +94,12 @@ static void test() #ifdef CAPSTONE_HAS_ALPHA #define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" #define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" +#endif +#ifdef CAPSTONE_HAS_HPPA +#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" #endif struct platform { @@ -383,6 +389,36 @@ static void test() sizeof(ALPHA_CODE) - 1, "Alpha (Big-endian)" }, +#endif +#ifdef CAPSTONE_HAS_HPPA + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)" + }, #endif }; diff --git a/tests/test_detail.c b/tests/test_detail.c index 07a2ee5f87..ab8de7e1f5 100644 --- a/tests/test_detail.c +++ b/tests/test_detail.c @@ -81,6 +81,12 @@ static void test() #ifdef CAPSTONE_HAS_ALPHA #define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7" #define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" +#endif +#ifdef CAPSTONE_HAS_HPPA +#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" #endif struct platform platforms[] = { @@ -300,6 +306,36 @@ static void test() sizeof(ALPHA_CODE) - 1, "Alpha (Big-endian)" }, +#endif +#ifdef CAPSTONE_HAS_HPPA + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)" + }, #endif }; diff --git a/tests/test_hppa.c b/tests/test_hppa.c new file mode 100644 index 0000000000..15a0179043 --- /dev/null +++ b/tests/test_hppa.c @@ -0,0 +1,186 @@ +/* Capstone Disassembler Engine */ +/* By Dmitry Sibirtsev , 2023 */ + +#include + +#include +#include + +struct platform { + cs_arch arch; + cs_mode mode; + unsigned char *code; + size_t size; + char *comment; +}; + +static csh handle; + +static void print_string_hex(char *comment, unsigned char *str, size_t len) +{ + unsigned char *c; + + printf("%s", comment); + for (c = str; c < str + len; c++) { + printf("0x%02x ", *c & 0xff); + } + + printf("\n"); +} + +static void print_insn_detail(cs_insn *ins) +{ + cs_hppa *hppa; + int i; + + // detail can be NULL on "data" instruction if SKIPDATA option is turned ON + if (ins->detail == NULL) + return; + + hppa = &(ins->detail->hppa); + if (hppa->op_count) + printf("\top_count: %u\n", hppa->op_count); + + for (i = 0; i < hppa->op_count; i++) { + cs_hppa_op *op = &(hppa->operands[i]); + switch ((int)op->type) { + default: + break; + case HPPA_OP_REG: + printf("\t\toperands[%u].type: REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_IMM: + printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", + i, op->imm); + break; + case HPPA_OP_IDX_REG: + printf("\t\toperands[%u].type: IDX_REG = %s\n", i, + cs_reg_name(handle, op->reg)); + break; + case HPPA_OP_DISP: + printf("\t\toperands[%u].type: DISP = 0x%" PRIx64 "\n", + i, op->imm); + break; + case HPPA_OP_MEM: + printf("\t\toperands[%u].type: MEM\n", i); + if (op->mem.space != HPPA_OP_INVALID) { + printf("\t\t\toperands[%u].mem.space: REG = %s\n", + i, cs_reg_name(handle, op->mem.space)); + } + printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, + cs_reg_name(handle, op->mem.base)); + break; + case HPPA_OP_TARGET: + printf("\t\toperands[%u].type: ", i); + if (op->imm >= 0x8000000000000000) + printf("TARGET = -0x%" PRIx64 "\n", -op->imm); + else + printf("TARGET = 0x%" PRIx64 "\n", op->imm); + break; + } + } + + printf("\n"); +} + +static void test() +{ +#define HPPA_20_CODE_BE \ + "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE \ + "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE \ + "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE \ + "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" + + struct platform platforms[] = { + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char *)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)", + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char *)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)", + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char *)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)", + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char *)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)", + }, + }; + + uint64_t address = 0x1000; + cs_insn *insn; + int i; + size_t count; + + for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) { + cs_err err = + cs_open(platforms[i].arch, platforms[i].mode, &handle); + if (err) { + printf("Failed on cs_open() with error returned: %u\n", + err); + continue; + } + + cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON); + + count = cs_disasm(handle, platforms[i].code, platforms[i].size, + address, 0, &insn); + if (count) { + size_t j; + + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code: ", platforms[i].code, + platforms[i].size); + printf("Disasm:\n"); + + for (j = 0; j < count; j++) { + printf("0x%" PRIx64 ":\t%s\t%s\n", + insn[j].address, insn[j].mnemonic, + insn[j].op_str); + print_insn_detail(&insn[j]); + } + printf("0x%" PRIx64 ":\n", + insn[j - 1].address + insn[j - 1].size); + + // free memory allocated by cs_disasm() + cs_free(insn, count); + } else { + printf("****************\n"); + printf("Platform: %s\n", platforms[i].comment); + print_string_hex("Code:", platforms[i].code, + platforms[i].size); + printf("ERROR: Failed to disasm given code!\n"); + } + + printf("\n"); + + cs_close(&handle); + } +} + +int main() +{ + test(); + + return 0; +} diff --git a/tests/test_iter.c b/tests/test_iter.c index 0647cbffc0..172d2c6a39 100644 --- a/tests/test_iter.c +++ b/tests/test_iter.c @@ -84,6 +84,13 @@ static void test() #define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00" #endif +#ifdef CAPSTONE_HAS_HPPA +#define HPPA_20_CODE_BE "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad" +#define HPPA_20_CODE "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14" +#define HPPA_11_CODE_BE "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1" +#define HPPA_11_CODE "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c" +#endif + struct platform platforms[] = { #ifdef CAPSTONE_HAS_X86 { @@ -282,6 +289,36 @@ struct platform platforms[] = { sizeof(ALPHA_CODE) - 1, "Alpha (Big-endian)" }, +#endif +#ifdef CAPSTONE_HAS_HPPA + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE_BE, + sizeof(HPPA_20_CODE_BE) - 1, + "HPPA 2.0 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, + (unsigned char*)HPPA_20_CODE, + sizeof(HPPA_20_CODE) - 1, + "HPPA 2.0 (Little-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE_BE, + sizeof(HPPA_11_CODE_BE) - 1, + "HPPA 1.1 (Big-endian)" + }, + { + CS_ARCH_HPPA, + CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, + (unsigned char*)HPPA_11_CODE, + sizeof(HPPA_11_CODE) - 1, + "HPPA 1.1 (Little-endian)" + }, #endif }; From cda40c6537547bc722efee821e32d2f7d1db53c7 Mon Sep 17 00:00:00 2001 From: R3v0LT <87137964+R33v0LT@users.noreply.github.com> Date: Fri, 29 Mar 2024 11:46:00 +0300 Subject: [PATCH 06/26] Fix invalid comparison with HPPA_OP_INVALID (#2300) --- arch/HPPA/HPPAInstPrinter.c | 2 +- arch/HPPA/HPPAMapping.c | 2 +- bindings/python/test_hppa.py | 2 +- cstool/cstool_hppa.c | 2 +- suite/cstest/src/hppa_detail.c | 2 +- tests/test_hppa.c | 2 +- 6 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/HPPA/HPPAInstPrinter.c b/arch/HPPA/HPPAInstPrinter.c index 56a2ff6385..3cea32e1ca 100644 --- a/arch/HPPA/HPPAInstPrinter.c +++ b/arch/HPPA/HPPAInstPrinter.c @@ -609,7 +609,7 @@ static void print_operand(MCInst *MI, SStream *O, const cs_hppa_op *op) break; case HPPA_OP_MEM: SStream_concat(O, "("); - if (op->mem.space != HPPA_OP_INVALID && + if (op->mem.space != HPPA_REG_INVALID && op->mem.space != HPPA_REG_SR0) { SStream_concat(O, HPPA_reg_name((csh)MI->csh, op->mem.space)); diff --git a/arch/HPPA/HPPAMapping.c b/arch/HPPA/HPPAMapping.c index 75f03dc2d0..7922861c41 100644 --- a/arch/HPPA/HPPAMapping.c +++ b/arch/HPPA/HPPAMapping.c @@ -419,7 +419,7 @@ void HPPA_reg_access(const cs_insn *insn, cs_regs regs_read, } break; case HPPA_OP_MEM: - if (op->mem.space != HPPA_OP_INVALID) + if (op->mem.space != HPPA_REG_INVALID) regs_read[read_count++] = op->mem.space; if (op->mem.base_access & CS_AC_READ) { regs_read[read_count++] = op->mem.base; diff --git a/bindings/python/test_hppa.py b/bindings/python/test_hppa.py index 75fcd0c29d..15e0e6017e 100755 --- a/bindings/python/test_hppa.py +++ b/bindings/python/test_hppa.py @@ -42,7 +42,7 @@ def print_insn_detail(insn): print("\t\toperands[%u].type: DISP = 0x%s" % (c, to_x(i.imm))) if i.type == HPPA_OP_MEM: print("\t\toperands[%u].type: MEM" % c) - if i.mem.space != HPPA_OP_INVALID: + if i.mem.space != HPPA_REG_INVALID: print("\t\t\toperands[%u].mem.space: REG = %s" % (c, insn.reg_name(i.mem.space))) print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base))) if i.type == HPPA_OP_TARGET: diff --git a/cstool/cstool_hppa.c b/cstool/cstool_hppa.c index f41b843180..154b6ac873 100644 --- a/cstool/cstool_hppa.c +++ b/cstool/cstool_hppa.c @@ -51,7 +51,7 @@ void print_insn_detail_hppa(csh handle, cs_insn *ins) break; case HPPA_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.space != HPPA_OP_INVALID) { + if (op->mem.space != HPPA_REG_INVALID) { printf("\t\t\toperands[%u].mem.space: REG = %s\n", i, cs_reg_name(handle, op->mem.space)); } diff --git a/suite/cstest/src/hppa_detail.c b/suite/cstest/src/hppa_detail.c index 38bc762c08..213a73c4f9 100644 --- a/suite/cstest/src/hppa_detail.c +++ b/suite/cstest/src/hppa_detail.c @@ -48,7 +48,7 @@ char *get_detail_hppa(csh *p_handle, cs_mode mode, cs_insn *ins) break; case HPPA_OP_MEM: add_str(&result, "\t\toperands[%u].type: MEM\n", i); - if (op->mem.space != HPPA_OP_INVALID) { + if (op->mem.space != HPPA_REG_INVALID) { add_str(&result, "\t\t\toperands[%u].mem.space: REG = %s\n", i, cs_reg_name(handle, op->mem.space)); diff --git a/tests/test_hppa.c b/tests/test_hppa.c index 15a0179043..d96693cc76 100644 --- a/tests/test_hppa.c +++ b/tests/test_hppa.c @@ -64,7 +64,7 @@ static void print_insn_detail(cs_insn *ins) break; case HPPA_OP_MEM: printf("\t\toperands[%u].type: MEM\n", i); - if (op->mem.space != HPPA_OP_INVALID) { + if (op->mem.space != HPPA_REG_INVALID) { printf("\t\t\toperands[%u].mem.space: REG = %s\n", i, cs_reg_name(handle, op->mem.space)); } From a5cf15e556eade85e9dcb19629b0808948ba6b0c Mon Sep 17 00:00:00 2001 From: R3v0LT <87137964+R33v0LT@users.noreply.github.com> Date: Wed, 10 Apr 2024 08:49:43 +0300 Subject: [PATCH 07/26] HPPA dissassembler fix unitialized variables errors (#2309) --- arch/HPPA/HPPADisassembler.c | 6 +++--- cstool/cstool_hppa.c | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c index b962f2d521..a73c6eafe0 100644 --- a/arch/HPPA/HPPADisassembler.c +++ b/arch/HPPA/HPPADisassembler.c @@ -2503,7 +2503,7 @@ static void fill_spop_mods(uint32_t insn, uint32_t ext, hppa_ext *hppa_ext) get_insn_field(insn, 27, 31); break; default: - break; + return; } push_int_modifier(hppa_ext, sop); if (n == 1) { @@ -2833,7 +2833,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) ->is_alternative = true; } } - } else if (class == 3) { + } else { subop = get_insn_field(insn, 16, 18); if (subop >= 4) { return false; @@ -2888,7 +2888,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) default: return false; } - } else if (class == 3) { + } else { subop = get_insn_field(insn, 16, 18); switch (subop) { case 0x00: diff --git a/cstool/cstool_hppa.c b/cstool/cstool_hppa.c index 154b6ac873..b8c0508a83 100644 --- a/cstool/cstool_hppa.c +++ b/cstool/cstool_hppa.c @@ -21,6 +21,8 @@ void print_insn_detail_hppa(csh handle, cs_insn *ins) cs_hppa_op *op = &(hppa->operands[i]); uint64_t target_addr; switch (op->type) { + default: + break; case HPPA_OP_REG: printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg)); From 24d99a907b2b7676a6e522b262ba5759481e6ae5 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Thu, 18 Apr 2024 15:51:49 +0000 Subject: [PATCH 08/26] Weaken requirements to document functions. (#2324) --- .github/PULL_REQUEST_TEMPLATE.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/PULL_REQUEST_TEMPLATE.md b/.github/PULL_REQUEST_TEMPLATE.md index 40deda3ed5..e051614e8a 100644 --- a/.github/PULL_REQUEST_TEMPLATE.md +++ b/.github/PULL_REQUEST_TEMPLATE.md @@ -1,7 +1,7 @@ **Your checklist for this pull request** -- [ ] I've documented or updated the documentation of every function and struct this PR changes. If not so I've explained why. +- [ ] I've documented or updated the documentation of every API function and struct this PR changes. - [ ] I've added tests that prove my fix is effective or that my feature works (if possible) **Detailed description** @@ -12,7 +12,7 @@ **Test plan** - + ... From 7746648f0bb8cc4e162527610f80128766665840 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Mon, 22 Apr 2024 03:55:44 +0000 Subject: [PATCH 09/26] [Auto-Sync] LLVM 18 update (#2296) Refactor auto-sync updater This refactors the auto-sync updater scripts, adds multiple tests and some other smaller things: - Converts the updater in a proper Python package. - Renaming was done to fit this new package structure. - Format code with usort and black and enforce it with the CI. - Add license information to auto-sync scripts. - Update tree-sitter-cpp to v20.0.5 - Fix py-tree-sitter version to `< 0.22.0` due to https://github.com/tree-sitter/tree-sitter-cpp/issues/250 - Allow file/dir creation of non existing paths. - Add CI tests for Patch, inc gen, translation and diff persistence testing. - Implement editing of diffs with an editor. - Fix: Add Namespace id also to anonymous enumeration members. --- .github/workflows/auto-sync.yml | 66 ++ .gitignore | 3 + .reuse/dep5 | 20 + .reuse/templates/license-template.jinja2 | 9 + LICENSE.TXT => LICENSES/LICENSE.TXT | 0 LICENSES/LICENSE_BSD_3_CLAUSE.txt | 11 + LICENSE_LLVM.TXT => LICENSES/LICENSE_LLVM.TXT | 0 bindings/python/setup.py | 2 +- dev_requirements.txt | 4 - suite/auto-sync/.gitignore | 4 +- suite/auto-sync/README.md | 20 +- suite/auto-sync/Updater/.gitignore | 2 - suite/auto-sync/Updater/PathVarHandler.py | 67 --- suite/auto-sync/Updater/README.md | 7 - suite/auto-sync/Updater/path_vars.json | 22 - suite/auto-sync/Updater/requirements.txt | 2 - suite/auto-sync/format_py.sh | 4 + suite/auto-sync/pyproject.toml | 23 + .../{Updater => src/autosync}/ASUpdater.py | 65 +- .../autosync}/HeaderPatcher.py | 26 +- .../{Updater => src/autosync}/Helper.py | 26 +- .../{Updater => src/autosync}/IncGenerator.py | 34 +- .../auto-sync/src/autosync/PathVarHandler.py | 106 ++++ .../src/autosync/Tests/test_header.h | 12 + .../src/autosync/Tests/test_header_patcher.py | 47 ++ .../src/autosync/Tests/test_include.inc | 11 + .../autosync/cpptranslator}/Configurator.py | 22 +- .../autosync/cpptranslator}/CppTranslator.py | 207 ++++--- .../autosync/cpptranslator}/Differ.py | 422 ++++++++++--- .../autosync/cpptranslator}/README.md | 11 +- .../cpptranslator}/TemplateCollector.py | 84 ++- .../Tests/Differ/new_src/diff_test_file.c | 28 + .../Tests/Differ/old_src/diff_test_file.c | 29 + .../Tests/Differ/test_arch_config.json | 35 ++ .../Tests/Patches/template_src.c | 7 + .../Tests/Patches/test_arch_config.json | 16 + .../cpptranslator/Tests/test_differ.py | 106 ++++ .../cpptranslator/Tests/test_patches.py | 563 ++++++++++++++++++ .../autosync/cpptranslator}/arch_config.json | 7 +- .../cpptranslator/patches}/AddCSDetail.py | 45 +- .../cpptranslator/patches}/AddOperand.py | 7 +- .../autosync/cpptranslator/patches}/Assert.py | 6 +- .../cpptranslator/patches}/BitCastStdArray.py | 41 +- .../patches}/CheckDecoderStatus.py | 7 +- .../patches}/ClassConstructorDef.py | 6 +- .../cpptranslator/patches}/ClassesDef.py | 11 +- .../patches}/ConstMCInstParameter.py | 7 +- .../cpptranslator/patches}/ConstMCOperand.py | 7 +- .../cpptranslator/patches}/CppInitCast.py | 14 +- .../cpptranslator/patches}/CreateOperand0.py | 13 +- .../cpptranslator/patches}/CreateOperand1.py | 15 +- .../patches}/DeclarationInConditionClause.py | 7 +- .../patches}/DecodeInstruction.py | 15 +- .../cpptranslator/patches}/DecoderCast.py | 5 +- .../patches}/DecoderParameter.py | 5 +- .../cpptranslator/patches}/FallThrough.py | 6 +- .../cpptranslator/patches}/FeatureBits.py | 19 +- .../cpptranslator/patches}/FeatureBitsDecl.py | 5 +- .../cpptranslator/patches}/FieldFromInstr.py | 15 +- .../cpptranslator/patches}/GetNumOperands.py | 7 +- .../cpptranslator/patches}/GetOpcode.py | 7 +- .../cpptranslator/patches}/GetOperand.py | 7 +- .../patches}/GetOperandRegImm.py | 7 +- .../cpptranslator/patches}/GetRegClass.py | 17 +- .../cpptranslator/patches}/GetRegFromClass.py | 7 +- .../cpptranslator/patches}/GetSubReg.py | 11 +- .../autosync/cpptranslator/patches/Helper.py} | 48 +- .../cpptranslator/patches}/Includes.py | 23 +- .../patches}/InlineToStaticInline.py | 12 +- .../cpptranslator/patches}/IsOptionalDef.py | 9 +- .../cpptranslator/patches}/IsPredicate.py | 9 +- .../cpptranslator/patches}/IsRegImm.py | 7 +- .../cpptranslator/patches}/LLVMFallThrough.py | 11 +- .../cpptranslator/patches}/LLVMunreachable.py | 7 +- .../patches}/MethodToFunctions.py | 11 +- .../patches}/MethodTypeQualifier.py | 7 +- .../cpptranslator/patches}/NamespaceAnon.py | 13 +- .../cpptranslator/patches}/NamespaceArch.py | 25 +- .../cpptranslator/patches}/NamespaceLLVM.py | 9 +- .../cpptranslator/patches}/OutStreamParam.py | 13 +- .../autosync/cpptranslator/patches}/Patch.py | 6 +- .../patches}/PredicateBlockFunctions.py | 7 +- .../cpptranslator/patches}/PrintAnnotation.py | 6 +- .../patches}/PrintRegImmShift.py | 7 +- .../patches}/QualifiedIdentifier.py | 7 +- .../cpptranslator/patches}/ReferencesDecl.py | 14 +- .../patches}/RegClassContains.py | 11 +- .../cpptranslator/patches}/STIArgument.py | 7 +- .../cpptranslator/patches}/STIFeatureBits.py | 11 +- .../cpptranslator/patches}/STParameter.py | 7 +- .../cpptranslator/patches}/SetOpcode.py | 7 +- .../cpptranslator/patches}/SignExtend.py | 10 +- .../cpptranslator/patches}/SizeAssignments.py | 13 +- .../cpptranslator/patches}/StreamOperation.py | 34 +- .../patches}/TemplateDeclaration.py | 38 +- .../patches}/TemplateDefinition.py | 35 +- .../patches}/TemplateParamDecl.py | 7 +- .../cpptranslator/patches}/TemplateRefs.py | 9 +- .../cpptranslator/patches}/UseMarkup.py | 6 +- .../patches}/UsingDeclaration.py | 5 +- .../cpptranslator/patches/__init__.py | 0 .../cpptranslator}/saved_patches.json | 0 suite/auto-sync/src/autosync/path_vars.json | 42 ++ suite/auto-sync/vendor/tree-sitter-cpp | 2 +- 104 files changed, 2395 insertions(+), 549 deletions(-) create mode 100644 .github/workflows/auto-sync.yml create mode 100644 .reuse/dep5 create mode 100644 .reuse/templates/license-template.jinja2 rename LICENSE.TXT => LICENSES/LICENSE.TXT (100%) create mode 100644 LICENSES/LICENSE_BSD_3_CLAUSE.txt rename LICENSE_LLVM.TXT => LICENSES/LICENSE_LLVM.TXT (100%) delete mode 100644 dev_requirements.txt delete mode 100644 suite/auto-sync/Updater/.gitignore delete mode 100644 suite/auto-sync/Updater/PathVarHandler.py delete mode 100644 suite/auto-sync/Updater/README.md delete mode 100644 suite/auto-sync/Updater/path_vars.json delete mode 100644 suite/auto-sync/Updater/requirements.txt create mode 100755 suite/auto-sync/format_py.sh create mode 100644 suite/auto-sync/pyproject.toml rename suite/auto-sync/{Updater => src/autosync}/ASUpdater.py (79%) rename suite/auto-sync/{Updater => src/autosync}/HeaderPatcher.py (78%) rename suite/auto-sync/{Updater => src/autosync}/Helper.py (88%) rename suite/auto-sync/{Updater => src/autosync}/IncGenerator.py (87%) create mode 100644 suite/auto-sync/src/autosync/PathVarHandler.py create mode 100644 suite/auto-sync/src/autosync/Tests/test_header.h create mode 100644 suite/auto-sync/src/autosync/Tests/test_header_patcher.py create mode 100644 suite/auto-sync/src/autosync/Tests/test_include.inc rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/Configurator.py (77%) rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/CppTranslator.py (72%) rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/Differ.py (61%) rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/README.md (95%) rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/TemplateCollector.py (83%) create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file.c create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file.c create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/test_arch_config.json create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/template_src.c create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/test_differ.py create mode 100644 suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/arch_config.json (95%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/AddCSDetail.py (75%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/AddOperand.py (85%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/Assert.py (81%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/BitCastStdArray.py (64%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/CheckDecoderStatus.py (82%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/ClassConstructorDef.py (83%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/ClassesDef.py (80%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/ConstMCInstParameter.py (82%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/ConstMCOperand.py (82%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/CppInitCast.py (64%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/CreateOperand0.py (83%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/CreateOperand1.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/DeclarationInConditionClause.py (87%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/DecodeInstruction.py (75%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/DecoderCast.py (88%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/DecoderParameter.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/FallThrough.py (78%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/FeatureBits.py (66%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/FeatureBitsDecl.py (83%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/FieldFromInstr.py (82%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetNumOperands.py (83%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetOpcode.py (85%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetOperand.py (85%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetOperandRegImm.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetRegClass.py (69%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetRegFromClass.py (85%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/GetSubReg.py (79%) rename suite/auto-sync/{Updater/CppTranslator/Patches/HelperMethods.py => src/autosync/cpptranslator/patches/Helper.py} (85%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/Includes.py (93%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/InlineToStaticInline.py (70%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/IsOptionalDef.py (83%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/IsPredicate.py (78%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/IsRegImm.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/LLVMFallThrough.py (57%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/LLVMunreachable.py (80%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/MethodToFunctions.py (76%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/MethodTypeQualifier.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/NamespaceAnon.py (63%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/NamespaceArch.py (72%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/NamespaceLLVM.py (76%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/OutStreamParam.py (75%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/Patch.py (95%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/PredicateBlockFunctions.py (86%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/PrintAnnotation.py (81%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/PrintRegImmShift.py (81%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/QualifiedIdentifier.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/ReferencesDecl.py (62%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/RegClassContains.py (77%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/STIArgument.py (81%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/STIFeatureBits.py (78%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/STParameter.py (84%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/SetOpcode.py (85%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/SignExtend.py (82%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/SizeAssignments.py (70%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/StreamOperation.py (74%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/TemplateDeclaration.py (66%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/TemplateDefinition.py (71%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/TemplateParamDecl.py (86%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/TemplateRefs.py (80%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/UseMarkup.py (78%) rename suite/auto-sync/{Updater/CppTranslator/Patches => src/autosync/cpptranslator/patches}/UsingDeclaration.py (78%) create mode 100644 suite/auto-sync/src/autosync/cpptranslator/patches/__init__.py rename suite/auto-sync/{Updater/CppTranslator => src/autosync/cpptranslator}/saved_patches.json (100%) create mode 100644 suite/auto-sync/src/autosync/path_vars.json diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml new file mode 100644 index 0000000000..325d806c62 --- /dev/null +++ b/.github/workflows/auto-sync.yml @@ -0,0 +1,66 @@ +name: Auto-Sync +on: + push: + paths: + - "suite/auto-sync/**" + pull_request: + +jobs: + check: + runs-on: ubuntu-latest + defaults: + run: + working-directory: suite/auto-sync/ + steps: + - name: Set up Python + uses: actions/setup-python@v4 + with: + python-version: '3.11' + + - name: Check out repository + uses: actions/checkout@v4 + with: + submodules: true + + - name: Install auto-sync package + run: | + pip install . + + - name: Check formatting + run: | + python3.11 -m black --check src/autosync + + - name: Build llvm-tblgen + run: | + git clone https://github.com/capstone-engine/llvm-capstone.git vendor/llvm_root + cd vendor/llvm_root + mkdir build + cd build + cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm + cmake --build . --target llvm-tblgen --config Debug + cd ../../../ + + - name: Test generation of inc files + run: | + ./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen + ./src/autosync/ASUpdater.py -d -a Alpha -s IncGen + ./src/autosync/ASUpdater.py -d -a ARM -s IncGen + ./src/autosync/ASUpdater.py -d -a PPC -s IncGen + + - name: CppTranslator - Patch tests + run: | + python -m unittest src/autosync/cpptranslator/Tests/test_patches.py + + - name: CppTranslator - Differ tests + run: | + python -m unittest src/autosync/cpptranslator/Tests/test_differ.py + + - name: CppTranslator - Test translation + run: | + ./src/autosync/ASUpdater.py --ci -d -a AArch64 -s Translate + ./src/autosync/ASUpdater.py --ci -d -a ARM -s Translate + ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate + + - name: Test Header patcher + run: | + python -m unittest src/autosync/Tests/test_header_patcher.py diff --git a/.gitignore b/.gitignore index 34dbd05bb4..1fa7b654c4 100644 --- a/.gitignore +++ b/.gitignore @@ -143,3 +143,6 @@ android-ndk-* # python virtual env .venv/ + +# Auto-sync files +suite/auto-sync/src/autosync.egg-info diff --git a/.reuse/dep5 b/.reuse/dep5 new file mode 100644 index 0000000000..33b023fc42 --- /dev/null +++ b/.reuse/dep5 @@ -0,0 +1,20 @@ +Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ +Upstream-Name: CapstoneEngine +Source: https://github.com/capstone-engine/capstone + +Files: src/autosync/cpptranslator/Tests/test_config.json +Copyright: 2022 Rot127 +License: BSD-3 + +Files: src/autosync/cpptranslator/arch_config.json +Copyright: 2022 Rot127 +License: BSD-3 + +Files: src/autosync/cpptranslator/saved_patches.json +Copyright: 2022 Rot127 +License: BSD-3 + +Files: src/autosync/path_vars.json +Copyright: 2022 Rot127 +License: BSD-3 + diff --git a/.reuse/templates/license-template.jinja2 b/.reuse/templates/license-template.jinja2 new file mode 100644 index 0000000000..51a9c95680 --- /dev/null +++ b/.reuse/templates/license-template.jinja2 @@ -0,0 +1,9 @@ +{% for copyright_line in copyright_lines %} +{{ copyright_line }} +{% endfor %} +{% for contributor_line in contributor_lines %} +SPDX-FileContributor: {{ contributor_line }} +{% endfor %} +{% for expression in spdx_expressions %} +SPDX-License-Identifier: {{ expression }} +{% endfor %} diff --git a/LICENSE.TXT b/LICENSES/LICENSE.TXT similarity index 100% rename from LICENSE.TXT rename to LICENSES/LICENSE.TXT diff --git a/LICENSES/LICENSE_BSD_3_CLAUSE.txt b/LICENSES/LICENSE_BSD_3_CLAUSE.txt new file mode 100644 index 0000000000..ea890afbc7 --- /dev/null +++ b/LICENSES/LICENSE_BSD_3_CLAUSE.txt @@ -0,0 +1,11 @@ +Copyright (c) . + +Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: + +1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. + +3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/LICENSE_LLVM.TXT b/LICENSES/LICENSE_LLVM.TXT similarity index 100% rename from LICENSE_LLVM.TXT rename to LICENSES/LICENSE_LLVM.TXT diff --git a/bindings/python/setup.py b/bindings/python/setup.py index 92ebf2d337..9cbd35b8bd 100755 --- a/bindings/python/setup.py +++ b/bindings/python/setup.py @@ -96,7 +96,7 @@ def copy_sources(): src.extend(glob.glob(os.path.join(BUILD_DIR, "*.mk"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "Makefile"))) - src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSE*"))) + src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSES/*"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "README"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT"))) src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES"))) diff --git a/dev_requirements.txt b/dev_requirements.txt deleted file mode 100644 index 9904cf7c3d..0000000000 --- a/dev_requirements.txt +++ /dev/null @@ -1,4 +0,0 @@ -tree-sitter==0.20.1 -termcolor==2.2.0 -cmake==3.27.9 -ninja==1.11.1.1 diff --git a/suite/auto-sync/.gitignore b/suite/auto-sync/.gitignore index c0de2866fa..fca115d2e0 100644 --- a/suite/auto-sync/.gitignore +++ b/suite/auto-sync/.gitignore @@ -1,5 +1,7 @@ build/ vendor/llvm_root */.idea -Updater/config.json +src/auto-sync/config.json +src/autosync/cpptranslator/Tests/Differ/test_saved_patches.json +src/autosync.egg-info diff --git a/suite/auto-sync/README.md b/suite/auto-sync/README.md index 2051168dff..93d82d109e 100644 --- a/suite/auto-sync/README.md +++ b/suite/auto-sync/README.md @@ -1,3 +1,9 @@ + + # Architecture updater This is Capstones updater for some architectures. @@ -5,12 +11,6 @@ Unfortunately not all architectures are supported yet. ## Install dependencies -Install clang-format - -``` -sudo apt install clang-format-18 -``` - Setup Python environment and Tree-sitter ``` @@ -20,7 +20,6 @@ sudo apt install python3-venv # Setup virtual environment in Capstone root dir python3 -m venv ./.venv source ./.venv/bin/activate -pip3 install -r dev_requirements.txt ``` Clone C++ grammar @@ -28,6 +27,7 @@ Clone C++ grammar ``` cd suite/auto-sync/ git submodule update --init --recursive ./vendor/ +pip install -e . ``` ## Update @@ -35,13 +35,13 @@ git submodule update --init --recursive ./vendor/ Check if your architecture is supported. ``` -./Updater/ASUpdater.py -h +./src/autosync/ASUpdater.py -h ``` Clone Capstones LLVM fork and build `llvm-tblgen` ``` -git clone https://github.com/capstone-engine/llvm-capstone +git clone https://github.com/capstone-engine/llvm-capstone vendor/llvm_root/ cd llvm-capstone git checkout auto-sync mkdir build @@ -55,7 +55,7 @@ cd ../../ Run the updater ``` -./Updater/ASUpdater.py -a +./src/autosync/ASUpdater.py -a ``` ## Post-processing steps diff --git a/suite/auto-sync/Updater/.gitignore b/suite/auto-sync/Updater/.gitignore deleted file mode 100644 index 999f4888f7..0000000000 --- a/suite/auto-sync/Updater/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*/.idea/ - diff --git a/suite/auto-sync/Updater/PathVarHandler.py b/suite/auto-sync/Updater/PathVarHandler.py deleted file mode 100644 index 9e7b6128a8..0000000000 --- a/suite/auto-sync/Updater/PathVarHandler.py +++ /dev/null @@ -1,67 +0,0 @@ -import json -import logging as log -import re -import subprocess - -from pathlib import Path - - -class Singleton(type): - _instances = {} - - def __call__(cls, *args, **kwargs): - if cls not in cls._instances: - cls._instances[cls] = super(Singleton, cls).__call__(*args, **kwargs) - return cls._instances[cls] - - -class PathVarHandler(metaclass=Singleton): - paths = {} - - def __init__(self) -> None: - try: - res = subprocess.run(["git", "rev-parse", "--show-toplevel"], check=True, stdout=subprocess.PIPE) - except subprocess.CalledProcessError: - log.fatal("Could not get repository top level directory.") - exit(1) - repo_root = res.stdout.decode("utf8").strip("\n") - # The main directories - self.paths["{CS_ROOT}"] = Path(repo_root) - self.paths["{AUTO_SYNC_ROOT}"] = Path(repo_root).joinpath("suite/auto-sync/") - self.paths["{AUTO_SYNC_UPDATER_DIR}"] = self.paths["{AUTO_SYNC_ROOT}"].joinpath("Updater/") - path_config_file = self.paths["{AUTO_SYNC_UPDATER_DIR}"].joinpath("path_vars.json") - - # Load variables - with open(path_config_file) as f: - vars = json.load(f) - - missing = list() - for p_name, path in vars.items(): - resolved = path - for var_id in re.findall(r"\{.+}", resolved): - if var_id not in self.paths: - log.fatal( - f"{var_id} hasn't been added to the PathVarsHandler, yet. The var must be defined in a previous entry." - ) - exit(1) - resolved = re.sub(var_id, str(self.paths[var_id]), resolved) - log.debug(f"Set {p_name} = {resolved}") - if not Path(resolved).exists(): - missing.append(resolved) - self.paths[p_name] = resolved - if len(missing) > 0: - log.fatal(f"Some paths from config file are missing!") - for m in missing: - log.fatal(f"\t{m}") - exit(1) - - def get_path(self, name: str) -> Path: - if name not in self.paths: - raise ValueError(f"Path variable {name} has no path saved.") - return self.paths[name] - - def complete_path(self, path_str: str) -> Path: - resolved = path_str - for p_name in re.findall(r"\{.+}", path_str): - resolved = re.sub(p_name, self.get_path(p_name), resolved) - return Path(resolved) diff --git a/suite/auto-sync/Updater/README.md b/suite/auto-sync/Updater/README.md deleted file mode 100644 index c9d825851f..0000000000 --- a/suite/auto-sync/Updater/README.md +++ /dev/null @@ -1,7 +0,0 @@ -# The update scripts for auto-sync - -## Updating only the `inc` files - -```cmd -> ./IncGenerator.py ... -``` diff --git a/suite/auto-sync/Updater/path_vars.json b/suite/auto-sync/Updater/path_vars.json deleted file mode 100644 index a7ad7f81aa..0000000000 --- a/suite/auto-sync/Updater/path_vars.json +++ /dev/null @@ -1,22 +0,0 @@ -{ - "{LLVM_ROOT}": "{AUTO_SYNC_ROOT}/llvm-capstone/", - "{LLVM_TARGET_DIR}": "{AUTO_SYNC_ROOT}/llvm-capstone/llvm/lib/Target/", - "{LLVM_TBLGEN_BIN}": "{AUTO_SYNC_ROOT}/llvm-capstone/build/bin/llvm-tblgen", - "{LLVM_INCLUDE_DIR}": "{AUTO_SYNC_ROOT}/llvm-capstone/llvm/include", - - "{VENDOR_DIR}": "{AUTO_SYNC_ROOT}/vendor/", - "{AUTO_SYNC_UPDATER_DIR}": "{AUTO_SYNC_ROOT}/Updater/", - - "{CPP_TRANSLATOR_DIR}": "{AUTO_SYNC_ROOT}/Updater/CppTranslator/", - "{CPP_TRANSLATOR_CONFIG}": "{CPP_TRANSLATOR_DIR}/arch_config.json", - "{INC_PATCH_DIR}": "{AUTO_SYNC_ROOT}/inc_patches/", - - "{CS_INCLUDE_DIR}": "{CS_ROOT}/include/capstone/", - "{CS_ARCH_MODULE_DIR}": "{CS_ROOT}/arch/", - "{CS_CLANG_FORMAT_FILE}": "{CS_ROOT}/.clang-format", - - "{BUILD_DIR}": "{AUTO_SYNC_ROOT}/build/", - "{C_INC_OUT_DIR}": "{BUILD_DIR}/llvm_c_inc/", - "{CPP_INC_OUT_DIR}": "{BUILD_DIR}/llvm_cpp_inc/" -} - diff --git a/suite/auto-sync/Updater/requirements.txt b/suite/auto-sync/Updater/requirements.txt deleted file mode 100644 index a48c72c228..0000000000 --- a/suite/auto-sync/Updater/requirements.txt +++ /dev/null @@ -1,2 +0,0 @@ -termcolor>=2.3.0 -tree_sitter>=0.20.2 diff --git a/suite/auto-sync/format_py.sh b/suite/auto-sync/format_py.sh new file mode 100755 index 0000000000..5f0d5d9dc5 --- /dev/null +++ b/suite/auto-sync/format_py.sh @@ -0,0 +1,4 @@ +#!/usr/bin/bash + +python3.11 -m usort format src/autosync +python3.11 -m black src/autosync diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml new file mode 100644 index 0000000000..ffa1f5aff5 --- /dev/null +++ b/suite/auto-sync/pyproject.toml @@ -0,0 +1,23 @@ +# Copyright © 2022 Rot127 +# Copyright © 2024 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + +[project] +name = "autosync" +version = "0.1.0" +dependencies = [ + "termcolor >= 2.3.0", + "tree_sitter < 0.22.0", + "black >= 24.3.0", + "usort >= 1.0.8", + "setuptools >= 69.2.0", + "ninja >= 1.11.1.1", + "cmake >= 3.28.3", + "reuse >= 3.0.1", + "clang-format >= 18.1.1", +] +requires-python = ">= 3.11" + +[tool.setuptools] +packages = ["autosync", "autosync.cpptranslator", "autosync.cpptranslator.patches"] +package-dir = {"" = "src"} diff --git a/suite/auto-sync/Updater/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py similarity index 79% rename from suite/auto-sync/Updater/ASUpdater.py rename to suite/auto-sync/src/autosync/ASUpdater.py index 9440583f1c..3a15c9d66b 100755 --- a/suite/auto-sync/Updater/ASUpdater.py +++ b/suite/auto-sync/src/autosync/ASUpdater.py @@ -1,21 +1,25 @@ #!/usr/bin/env python3 +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import argparse + +import logging as log import os import shutil import subprocess import sys - -import logging as log from enum import StrEnum - -from CppTranslator.Configurator import Configurator -from CppTranslator.CppTranslator import Translator -from IncGenerator import IncGenerator -from Helper import get_path, convert_loglevel, check_py_version, fail_exit -from HeaderPatcher import HeaderPatcher from pathlib import Path +from autosync.cpptranslator.Configurator import Configurator +from autosync.cpptranslator.CppTranslator import Translator +from autosync.HeaderPatcher import HeaderPatcher +from autosync.Helper import check_py_version, convert_loglevel, fail_exit, get_path + +from autosync.IncGenerator import IncGenerator + class USteps(StrEnum): INC_GEN = "IncGen" @@ -38,11 +42,13 @@ def __init__( no_clean: bool, refactor: bool, differ_no_auto_apply: bool, + wait_for_user: bool = True, ) -> None: self.arch = arch self.write = write self.no_clean_build = no_clean self.inc_list = inc_list + self.wait_for_user = wait_for_user if USteps.ALL in steps: self.steps = [USteps.INC_GEN, USteps.TRANS, USteps.DIFF] else: @@ -108,20 +114,22 @@ def check_tree_sitter(self) -> None: ts_dir = get_path("{VENDOR_DIR}").joinpath("tree-sitter-cpp") if not ts_dir.exists(): log.info("tree-sitter was not fetched. Cloning it now...") - subprocess.run(["git", "submodule", "update", "--init", "--recursive"], check=True) + subprocess.run( + ["git", "submodule", "update", "--init", "--recursive"], check=True + ) def translate(self) -> None: self.check_tree_sitter() translator_config = get_path("{CPP_TRANSLATOR_CONFIG}") configurator = Configurator(self.arch, translator_config) - translator = Translator(configurator) + translator = Translator(configurator, self.wait_for_user) translator.translate() translator.remark_manual_files() def diff(self) -> None: translator_config = get_path("{CPP_TRANSLATOR_CONFIG}") configurator = Configurator(self.arch, translator_config) - from CppTranslator.Differ import Differ + from autosync.cpptranslator.Differ import Differ differ = Differ(configurator, self.differ_no_auto_apply) differ.diff() @@ -151,11 +159,23 @@ def parse_args() -> argparse.Namespace: description="Capstones architecture module updater.", ) parser.add_argument( - "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64", "Alpha"], required=True + "-a", + dest="arch", + help="Name of target architecture.", + choices=["ARM", "PPC", "AArch64", "Alpha"], + required=True, ) - parser.add_argument("-d", dest="no_clean", help="Don't clean build dir before updating.", action="store_true") parser.add_argument( - "-w", dest="write", help="Write generated/translated files to arch//", action="store_true" + "-d", + dest="no_clean", + help="Don't clean build dir before updating.", + action="store_true", + ) + parser.add_argument( + "-w", + dest="write", + help="Write generated/translated files to arch//", + action="store_true", ) parser.add_argument( "-v", @@ -205,9 +225,15 @@ def parse_args() -> argparse.Namespace: parser.add_argument( "--refactor", dest="refactor", - help="Sets change update behavior to ease refacotring and new implementations.", + help="Sets change update behavior to ease refactoring and new implementations.", action="store_true", ) + parser.add_argument( + "--ci", + dest="wait_for_user", + help="The translator will not wait for user input when printing important logs.", + action="store_false", + ) arguments = parser.parse_args() return arguments @@ -223,6 +249,13 @@ def parse_args() -> argparse.Namespace: ) Updater = ASUpdater( - args.arch, args.write, args.steps, args.inc_list, args.no_clean, args.refactor, args.no_auto_apply + args.arch, + args.write, + args.steps, + args.inc_list, + args.no_clean, + args.refactor, + args.no_auto_apply, + args.wait_for_user, ) Updater.update() diff --git a/suite/auto-sync/Updater/HeaderPatcher.py b/suite/auto-sync/src/autosync/HeaderPatcher.py similarity index 78% rename from suite/auto-sync/Updater/HeaderPatcher.py rename to suite/auto-sync/src/autosync/HeaderPatcher.py index 1243c90a0d..502e389718 100755 --- a/suite/auto-sync/Updater/HeaderPatcher.py +++ b/suite/auto-sync/src/autosync/HeaderPatcher.py @@ -1,5 +1,8 @@ #!/usr/bin/env python3 +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import argparse import logging as log import re @@ -12,8 +15,12 @@ def parse_args() -> argparse.Namespace: prog="PatchHeaders", description="Patches generated enums into the main arch header file.", ) - parser.add_argument("--header", dest="header", help="Path header file.", type=Path, required=True) - parser.add_argument("--inc", dest="inc", help="Path inc file.", type=Path, required=True) + parser.add_argument( + "--header", dest="header", help="Path header file.", type=Path, required=True + ) + parser.add_argument( + "--inc", dest="inc", help="Path inc file.", type=Path, required=True + ) arguments = parser.parse_args() return arguments @@ -24,9 +31,13 @@ def error_exit(msg: str) -> None: class HeaderPatcher: - def __init__(self, header: Path, inc: Path) -> None: + def __init__(self, header: Path, inc: Path, write_file: bool = True) -> None: self.header = header self.inc = inc + self.inc_content: str = "" + self.write_file = write_file + # Gets set to the patched file content if writing to the file is disabled. + self.patched_header_content: str = "" def patch_header(self) -> bool: if not (self.header.exists() or self.header.is_file()): @@ -69,7 +80,7 @@ def patch_header(self) -> bool: header_enum_id = f":{ev_id}" if ev_id != "NOTGIVEN" else "" regex = ( rf"\s*// generated content <{self.inc.name}{header_enum_id}> begin.*(\n)" - rf"(.*\n)+" + rf"(.*\n)*" rf"\s*// generated content <{self.inc.name}{header_enum_id}> end.*(\n)" ) if not re.search(regex, header_content): @@ -84,8 +95,11 @@ def patch_header(self) -> bool: ) header_content = re.sub(regex, new_content, header_content) - with open(self.header, "w") as f: - f.write(header_content) + if self.write_file: + with open(self.header, "w") as f: + f.write(header_content) + else: + self.patched_header_content = header_content log.info(f"Patched {self.inc.name} into {self.header.name}") return True diff --git a/suite/auto-sync/Updater/Helper.py b/suite/auto-sync/src/autosync/Helper.py similarity index 88% rename from suite/auto-sync/Updater/Helper.py rename to suite/auto-sync/src/autosync/Helper.py index dbdc5a6dc2..6f7b352877 100644 --- a/suite/auto-sync/Updater/Helper.py +++ b/suite/auto-sync/src/autosync/Helper.py @@ -1,3 +1,6 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import hashlib import logging as log import shutil @@ -6,10 +9,10 @@ from pathlib import Path import termcolor - -from PathVarHandler import PathVarHandler from tree_sitter import Node +from autosync.PathVarHandler import PathVarHandler + def convert_loglevel(level: str) -> int: if level == "debug": @@ -79,23 +82,25 @@ def find_id_by_type(node: Node, node_types: [str], type_must_match: bool) -> byt return b"" -def print_prominent_warning(msg: str) -> None: +def print_prominent_warning(msg: str, wait_for_user: bool = True) -> None: print("\n" + separator_line_1("yellow")) print(termcolor.colored("WARNING", "yellow", attrs=["bold"]) + "\n") print(msg) print(separator_line_1("yellow")) - input("Press enter to continue...\n") + if wait_for_user: + input("Press enter to continue...\n") def term_width() -> int: return shutil.get_terminal_size()[0] -def print_prominent_info(msg: str) -> None: +def print_prominent_info(msg: str, wait_for_user: bool = True) -> None: print("\n" + separator_line_1("blue")) print(msg) print(separator_line_1("blue")) - input("Press enter to continue...\n") + if wait_for_user: + input("Press enter to continue...\n") def bold(msg: str, color: str = None) -> str: @@ -140,7 +145,14 @@ def get_header() -> str: def run_clang_format(out_paths: list[Path]): for out_file in out_paths: log.info(f"Format {out_file}") - subprocess.run(["clang-format-18", f"-style=file:{get_path('{CS_CLANG_FORMAT_FILE}')}", "-i", out_file]) + subprocess.run( + [ + "clang-format", + f"-style=file:{get_path('{CS_CLANG_FORMAT_FILE}')}", + "-i", + out_file, + ] + ) def get_path(config_path: str) -> Path: diff --git a/suite/auto-sync/Updater/IncGenerator.py b/suite/auto-sync/src/autosync/IncGenerator.py similarity index 87% rename from suite/auto-sync/Updater/IncGenerator.py rename to suite/auto-sync/src/autosync/IncGenerator.py index 665e5507a1..e29c22e2d7 100644 --- a/suite/auto-sync/Updater/IncGenerator.py +++ b/suite/auto-sync/src/autosync/IncGenerator.py @@ -1,15 +1,17 @@ #!/usr/bin/env python3 +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + +import logging as log import os import re import shutil import subprocess - -import logging as log - -from Helper import fail_exit, get_path from pathlib import Path +from autosync.Helper import fail_exit, get_path + inc_tables = [ { "name": "Disassembler", @@ -71,7 +73,9 @@ def __init__(self, arch: str, inc_list: list) -> None: self.patches_dir_path: Path = get_path("{INC_PATCH_DIR}") self.llvm_include_dir: Path = get_path("{LLVM_INCLUDE_DIR}") self.output_dir: Path = get_path("{BUILD_DIR}") - self.llvm_target_dir: Path = get_path("{LLVM_TARGET_DIR}").joinpath(f"{self.arch_dir_name}") + self.llvm_target_dir: Path = get_path("{LLVM_TARGET_DIR}").joinpath( + f"{self.arch_dir_name}" + ) self.llvm_tblgen: Path = get_path("{LLVM_TBLGEN_BIN}") self.output_dir_c_inc = get_path("{C_INC_OUT_DIR}") self.output_dir_cpp_inc = get_path("{CPP_INC_OUT_DIR}") @@ -106,16 +110,26 @@ def move_mapping_files(self) -> None: for file in Path.cwd().iterdir(): if re.search(rf"{self.arch}Gen.*\.inc", file.name): log.debug(f"Move {file} to {self.output_dir_c_inc}") + if self.output_dir_c_inc.joinpath(file.name).exists(): + os.remove(self.output_dir_c_inc.joinpath(file.name)) shutil.move(file, self.output_dir_c_inc) if self.arch == "AArch64": # We have to rename the file SystemRegister -> SystemOperands - sys_ops_table_file = self.output_dir_c_inc.joinpath("AArch64GenSystemRegister.inc") - new_sys_ops_file = self.output_dir_c_inc.joinpath("AArch64GenSystemOperands.inc") + sys_ops_table_file = self.output_dir_c_inc.joinpath( + "AArch64GenSystemRegister.inc" + ) + new_sys_ops_file = self.output_dir_c_inc.joinpath( + "AArch64GenSystemOperands.inc" + ) if "SystemOperand" not in self.inc_list: return elif not sys_ops_table_file.exists(): - fail_exit(f"{sys_ops_table_file} does not exist. But it should have been generated.") + fail_exit( + f"{sys_ops_table_file} does not exist. But it should have been generated." + ) + if new_sys_ops_file.exists(): + os.remove(new_sys_ops_file) shutil.move(sys_ops_table_file, new_sys_ops_file) def gen_incs(self) -> None: @@ -178,6 +192,6 @@ def apply_patches(self) -> None: check=True, ) except subprocess.CalledProcessError as e: - log.warn(f"Patch {patch.name} did not apply correctly!") - log.warn(f"git apply returned: {e}") + log.warning(f"Patch {patch.name} did not apply correctly!") + log.warning(f"git apply returned: {e}") return diff --git a/suite/auto-sync/src/autosync/PathVarHandler.py b/suite/auto-sync/src/autosync/PathVarHandler.py new file mode 100644 index 0000000000..a973f84dcf --- /dev/null +++ b/suite/auto-sync/src/autosync/PathVarHandler.py @@ -0,0 +1,106 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + +import json +import logging as log +import re +import subprocess + +from pathlib import Path + + +class Singleton(type): + _instances = {} + + def __call__(cls, *args, **kwargs): + if cls not in cls._instances: + cls._instances[cls] = super(Singleton, cls).__call__(*args, **kwargs) + return cls._instances[cls] + + +class PathVarHandler(metaclass=Singleton): + def __init__(self) -> None: + try: + res = subprocess.run( + ["git", "rev-parse", "--show-toplevel"], + check=True, + stdout=subprocess.PIPE, + ) + except subprocess.CalledProcessError: + log.fatal("Could not get repository top level directory.") + exit(1) + repo_root = res.stdout.decode("utf8").strip("\n") + # The main directories + self.paths: dict[str:Path] = dict() + self.paths["{CS_ROOT}"] = Path(repo_root) + self.paths["{AUTO_SYNC_ROOT}"] = Path(repo_root).joinpath("suite/auto-sync/") + self.paths["{AUTO_SYNC_SRC}"] = self.paths["{AUTO_SYNC_ROOT}"].joinpath( + "src/autosync/" + ) + path_config_file = self.paths["{AUTO_SYNC_SRC}"].joinpath("path_vars.json") + + # Load variables + with open(path_config_file) as f: + vars = json.load(f) + + paths = vars["paths"] + self.create_during_runtime = vars["create_during_runtime"] + + missing = list() + for p_name, path in paths.items(): + resolved = path + for var_id in re.findall(r"\{.+}", resolved): + if var_id not in self.paths: + log.fatal( + f"{var_id} hasn't been added to the PathVarsHandler, yet. The var must be defined in a previous entry." + ) + exit(1) + resolved: str = re.sub(var_id, str(self.paths[var_id]), resolved) + log.debug(f"Set {p_name} = {resolved}") + if not Path(resolved).exists() and ( + p_name not in self.create_during_runtime + and p_name not in vars["ignore_missing"] + ): + missing.append(resolved) + elif var_id in self.create_during_runtime: + self.create_path(var_id, resolved) + self.paths[p_name] = Path(resolved) + if len(missing) > 0: + log.fatal(f"Some paths from config file are missing!") + for m in missing: + log.fatal(f"\t{m}") + exit(1) + + def get_path(self, name: str) -> Path: + if name not in self.paths: + raise ValueError(f"Path variable {name} has no path saved.") + if name in self.create_during_runtime: + self.create_path(name, self.paths[name]) + return self.paths[name] + + def complete_path(self, path_str: str) -> Path: + resolved = path_str + for p_name in re.findall(r"\{.+}", path_str): + resolved = re.sub(p_name, str(self.get_path(p_name)), resolved) + return Path(resolved) + + @staticmethod + def create_path(var_id: str, path: str): + pp = Path(path) + if pp.exists(): + return + + log.debug(f"Create path {var_id} @ {path}") + postfix = var_id.strip("}").split("_")[-1] + if postfix == "FILE": + if not pp.parent.exists(): + pp.parent.mkdir(parents=True) + pp.touch() + elif postfix == "DIR": + pp.mkdir(parents=True) + else: + from autosync.Helper import fail_exit + + fail_exit( + f"The var_id: {var_id} must end in _FILE or _DIR. It ends in '{postfix}'" + ) diff --git a/suite/auto-sync/src/autosync/Tests/test_header.h b/suite/auto-sync/src/autosync/Tests/test_header.h new file mode 100644 index 0000000000..f5cac5620a --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_header.h @@ -0,0 +1,12 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + + + // Include the whole file + // generated content begin + // generated content end + + // Include only a part of the file. + // generated content begin + // generated content end + diff --git a/suite/auto-sync/src/autosync/Tests/test_header_patcher.py b/suite/auto-sync/src/autosync/Tests/test_header_patcher.py new file mode 100644 index 0000000000..6aef639ce4 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_header_patcher.py @@ -0,0 +1,47 @@ +# SPDX-FileCopyrightText: 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import unittest + +from autosync.HeaderPatcher import HeaderPatcher +from autosync.Helper import get_path + + +class TestHeaderPatcher(unittest.TestCase): + @classmethod + def setUpClass(cls): + cls.hpatcher = HeaderPatcher( + get_path("{HEADER_PATCHER_TEST_HEADER_FILE}"), + get_path("{HEADER_PATCHER_TEST_INC_FILE}"), + write_file=False, + ) + + def test_header_patching(self): + self.hpatcher.patch_header() + self.assertEqual( + self.hpatcher.patched_header_content, + ( + "// SPDX-FileCopyrightText: 2024 Rot127 \n" + "// SPDX-License-Identifier: BSD-3\n" + "\n" + "\n" + " // Include the whole file\n" + " // generated content begin\n" + " // clang-format off\n" + "\n" + "This part should be included if the whole file is included.\n" + "\n" + " // clang-format on\n" + " // generated content end\n" + "\n" + " // Include only a part of the file.\n" + " // generated content begin\n" + " // clang-format off\n" + "\n" + " Partial include of something\n" + "\n" + " // clang-format on\n" + " // generated content end\n" + "\n" + ), + ) diff --git a/suite/auto-sync/src/autosync/Tests/test_include.inc b/suite/auto-sync/src/autosync/Tests/test_include.inc new file mode 100644 index 0000000000..a0288c9307 --- /dev/null +++ b/suite/auto-sync/src/autosync/Tests/test_include.inc @@ -0,0 +1,11 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#ifdef GUARD +#undef GUARD + +Partial include of something + +#endif + +This part should be included if the whole file is included. diff --git a/suite/auto-sync/Updater/CppTranslator/Configurator.py b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py similarity index 77% rename from suite/auto-sync/Updater/CppTranslator/Configurator.py rename to suite/auto-sync/src/autosync/cpptranslator/Configurator.py index ed781c06b5..ba19fa0de1 100644 --- a/suite/auto-sync/Updater/CppTranslator/Configurator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py @@ -1,9 +1,13 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import json +import logging as log from pathlib import Path -from Helper import get_path, fail_exit from tree_sitter import Language, Parser -import logging as log + +from autosync.Helper import fail_exit, get_path class Configurator: @@ -60,7 +64,9 @@ def load_config(self) -> None: with open(self.config_path) as f: conf = json.loads(f.read()) if self.arch not in conf: - fail_exit(f"{self.arch} has no configuration. Please add them in {self.config_path}!") + fail_exit( + f"{self.arch} has no configuration. Please add them in {self.config_path}!" + ) self.config = conf def ts_compile_cpp(self) -> None: @@ -68,13 +74,17 @@ def ts_compile_cpp(self) -> None: ts_grammar_path = get_path("{VENDOR_DIR}").joinpath("tree-sitter-cpp") if not Path.exists(ts_grammar_path): fail_exit(f"Could not load the tree-sitter grammar at '{ts_grammar_path}'") - Language.build_library(str(self.ts_shared_object), [ts_grammar_path]) + # build_library wll be deprecated in 0.22.0. But CPP tree-sitter doesn't have Python bindings. + # So we stick with it. + Language.build_library(str(self.ts_shared_object), [str(ts_grammar_path)]) def ts_set_cpp_language(self) -> None: log.info(f"Load language '{self.ts_shared_object}'") if not Path.exists(self.ts_shared_object): - fail_exit(f"Could not load the tree-sitter language shared object at '{self.ts_shared_object}'") - self.ts_cpp_lang = Language(self.ts_shared_object, "cpp") + fail_exit( + f"Could not load the tree-sitter language shared object at '{self.ts_shared_object}'" + ) + self.ts_cpp_lang = Language(str(self.ts_shared_object), "cpp") def init_parser(self) -> None: log.debug("Init parser") diff --git a/suite/auto-sync/Updater/CppTranslator/CppTranslator.py b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py similarity index 72% rename from suite/auto-sync/Updater/CppTranslator/CppTranslator.py rename to suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py index 3a2465a99a..c328295b7e 100755 --- a/suite/auto-sync/Updater/CppTranslator/CppTranslator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/CppTranslator.py @@ -1,77 +1,89 @@ #!/usr/bin/env python3 -from pathlib import Path -import termcolor -from tree_sitter import Language, Parser, Tree, Node +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import argparse import logging as log import sys +from pathlib import Path -from tree_sitter.binding import Query - -from CppTranslator.Configurator import Configurator -from Helper import convert_loglevel, print_prominent_warning, get_header, run_clang_format, get_path -from CppTranslator.Patches.GetRegFromClass import GetRegFromClass -from CppTranslator.Patches.AddCSDetail import AddCSDetail -from CppTranslator.Patches.AddOperand import AddOperand -from CppTranslator.Patches.Assert import Assert -from CppTranslator.Patches.BitCastStdArray import BitCastStdArray -from CppTranslator.Patches.CheckDecoderStatus import CheckDecoderStatus -from CppTranslator.Patches.ClassConstructorDef import ClassConstructorDef -from CppTranslator.Patches.ClassesDef import ClassesDef -from CppTranslator.Patches.ConstMCInstParameter import ConstMCInstParameter -from CppTranslator.Patches.ConstMCOperand import ConstMCOperand -from CppTranslator.Patches.CppInitCast import CppInitCast -from CppTranslator.Patches.CreateOperand0 import CreateOperand0 -from CppTranslator.Patches.CreateOperand1 import CreateOperand1 -from CppTranslator.Patches.DeclarationInConditionClause import DeclarationInConditionalClause -from CppTranslator.Patches.DecodeInstruction import DecodeInstruction -from CppTranslator.Patches.DecoderCast import DecoderCast -from CppTranslator.Patches.DecoderParameter import DecoderParameter -from CppTranslator.Patches.FallThrough import FallThrough -from CppTranslator.Patches.FeatureBits import FeatureBits -from CppTranslator.Patches.FeatureBitsDecl import FeatureBitsDecl -from CppTranslator.Patches.FieldFromInstr import FieldFromInstr -from CppTranslator.Patches.GetNumOperands import GetNumOperands -from CppTranslator.Patches.GetOpcode import GetOpcode -from CppTranslator.Patches.GetOperandRegImm import GetOperandRegImm -from CppTranslator.Patches.GetOperand import GetOperand -from CppTranslator.Patches.GetRegClass import GetRegClass -from CppTranslator.Patches.GetSubReg import GetSubReg -from CppTranslator.Patches.Includes import Includes -from CppTranslator.Patches.InlineToStaticInline import InlineToStaticInline -from CppTranslator.Patches.IsRegImm import IsOperandRegImm -from CppTranslator.Patches.IsOptionalDef import IsOptionalDef -from CppTranslator.Patches.IsPredicate import IsPredicate -from CppTranslator.Patches.LLVMFallThrough import LLVMFallThrough -from CppTranslator.Patches.LLVMunreachable import LLVMUnreachable -from CppTranslator.Patches.MethodToFunctions import MethodToFunction -from CppTranslator.Patches.MethodTypeQualifier import MethodTypeQualifier -from CppTranslator.Patches.NamespaceLLVM import NamespaceLLVM -from CppTranslator.Patches.NamespaceAnon import NamespaceAnon -from CppTranslator.Patches.NamespaceArch import NamespaceArch -from CppTranslator.Patches.OutStreamParam import OutStreamParam -from CppTranslator.Patches.PredicateBlockFunctions import PredicateBlockFunctions -from CppTranslator.Patches.PrintAnnotation import PrintAnnotation -from CppTranslator.Patches.PrintRegImmShift import PrintRegImmShift -from CppTranslator.Patches.QualifiedIdentifier import QualifiedIdentifier -from CppTranslator.Patches.Patch import Patch -from CppTranslator.Patches.ReferencesDecl import ReferencesDecl -from CppTranslator.Patches.RegClassContains import RegClassContains -from CppTranslator.Patches.STIArgument import STIArgument -from CppTranslator.Patches.STIFeatureBits import STIFeatureBits -from CppTranslator.Patches.STParameter import SubtargetInfoParam -from CppTranslator.Patches.SetOpcode import SetOpcode -from CppTranslator.Patches.SignExtend import SignExtend -from CppTranslator.Patches.SizeAssignments import SizeAssignment -from CppTranslator.Patches.StreamOperation import StreamOperations -from CppTranslator.Patches.TemplateDeclaration import TemplateDeclaration -from CppTranslator.Patches.TemplateDefinition import TemplateDefinition -from CppTranslator.Patches.TemplateParamDecl import TemplateParamDecl -from CppTranslator.Patches.TemplateRefs import TemplateRefs -from CppTranslator.Patches.UseMarkup import UseMarkup -from CppTranslator.Patches.UsingDeclaration import UsingDeclaration -from CppTranslator.TemplateCollector import TemplateCollector +import termcolor +from tree_sitter import Language, Node, Parser, Query, Tree + +from autosync.cpptranslator.Configurator import Configurator +from autosync.cpptranslator.patches.AddCSDetail import AddCSDetail +from autosync.cpptranslator.patches.AddOperand import AddOperand +from autosync.cpptranslator.patches.Assert import Assert +from autosync.cpptranslator.patches.BitCastStdArray import BitCastStdArray +from autosync.cpptranslator.patches.CheckDecoderStatus import CheckDecoderStatus +from autosync.cpptranslator.patches.ClassConstructorDef import ClassConstructorDef +from autosync.cpptranslator.patches.ClassesDef import ClassesDef +from autosync.cpptranslator.patches.ConstMCInstParameter import ConstMCInstParameter +from autosync.cpptranslator.patches.ConstMCOperand import ConstMCOperand +from autosync.cpptranslator.patches.CppInitCast import CppInitCast +from autosync.cpptranslator.patches.CreateOperand0 import CreateOperand0 +from autosync.cpptranslator.patches.CreateOperand1 import CreateOperand1 +from autosync.cpptranslator.patches.DeclarationInConditionClause import ( + DeclarationInConditionalClause, +) +from autosync.cpptranslator.patches.DecodeInstruction import DecodeInstruction +from autosync.cpptranslator.patches.DecoderCast import DecoderCast +from autosync.cpptranslator.patches.DecoderParameter import DecoderParameter +from autosync.cpptranslator.patches.FallThrough import FallThrough +from autosync.cpptranslator.patches.FeatureBits import FeatureBits +from autosync.cpptranslator.patches.FeatureBitsDecl import FeatureBitsDecl +from autosync.cpptranslator.patches.FieldFromInstr import FieldFromInstr +from autosync.cpptranslator.patches.GetNumOperands import GetNumOperands +from autosync.cpptranslator.patches.GetOpcode import GetOpcode +from autosync.cpptranslator.patches.GetOperand import GetOperand +from autosync.cpptranslator.patches.GetOperandRegImm import GetOperandRegImm +from autosync.cpptranslator.patches.GetRegClass import GetRegClass +from autosync.cpptranslator.patches.GetRegFromClass import GetRegFromClass +from autosync.cpptranslator.patches.GetSubReg import GetSubReg +from autosync.cpptranslator.patches.Includes import Includes +from autosync.cpptranslator.patches.InlineToStaticInline import InlineToStaticInline +from autosync.cpptranslator.patches.IsOptionalDef import IsOptionalDef +from autosync.cpptranslator.patches.IsPredicate import IsPredicate +from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm +from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough +from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable +from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction +from autosync.cpptranslator.patches.MethodTypeQualifier import MethodTypeQualifier +from autosync.cpptranslator.patches.NamespaceAnon import NamespaceAnon +from autosync.cpptranslator.patches.NamespaceArch import NamespaceArch +from autosync.cpptranslator.patches.NamespaceLLVM import NamespaceLLVM +from autosync.cpptranslator.patches.OutStreamParam import OutStreamParam +from autosync.cpptranslator.patches.Patch import Patch +from autosync.cpptranslator.patches.PredicateBlockFunctions import ( + PredicateBlockFunctions, +) +from autosync.cpptranslator.patches.PrintAnnotation import PrintAnnotation +from autosync.cpptranslator.patches.PrintRegImmShift import PrintRegImmShift +from autosync.cpptranslator.patches.QualifiedIdentifier import QualifiedIdentifier +from autosync.cpptranslator.patches.ReferencesDecl import ReferencesDecl +from autosync.cpptranslator.patches.RegClassContains import RegClassContains +from autosync.cpptranslator.patches.SetOpcode import SetOpcode +from autosync.cpptranslator.patches.SignExtend import SignExtend +from autosync.cpptranslator.patches.SizeAssignments import SizeAssignment +from autosync.cpptranslator.patches.STIArgument import STIArgument +from autosync.cpptranslator.patches.STIFeatureBits import STIFeatureBits +from autosync.cpptranslator.patches.STParameter import SubtargetInfoParam +from autosync.cpptranslator.patches.StreamOperation import StreamOperations +from autosync.cpptranslator.patches.TemplateDeclaration import TemplateDeclaration +from autosync.cpptranslator.patches.TemplateDefinition import TemplateDefinition +from autosync.cpptranslator.patches.TemplateParamDecl import TemplateParamDecl +from autosync.cpptranslator.patches.TemplateRefs import TemplateRefs +from autosync.cpptranslator.patches.UseMarkup import UseMarkup +from autosync.cpptranslator.patches.UsingDeclaration import UsingDeclaration +from autosync.cpptranslator.TemplateCollector import TemplateCollector +from autosync.Helper import ( + convert_loglevel, + get_header, + get_path, + print_prominent_warning, + run_clang_format, +) class Translator: @@ -162,17 +174,22 @@ class Translator: TemplateDefinition.__name__: 6, } - def __init__(self, configure: Configurator): + def __init__(self, configure: Configurator, wait_for_user: bool = False): self.configurator = configure + self.wait_for_user = wait_for_user self.arch = self.configurator.get_arch() self.conf = self.configurator.get_arch_config() self.conf_general = self.configurator.get_general_config() self.ts_cpp_lang = self.configurator.get_cpp_lang() self.parser = self.configurator.get_parser() - self.src_paths: [Path] = [get_path(sp["in"]) for sp in self.conf["files_to_translate"]] - t_out_dir: Path = get_path(self.conf_general["translation_out_dir"]) - self.out_paths: [Path] = [t_out_dir.joinpath(sp["out"]) for sp in self.conf["files_to_translate"]] + self.src_paths: [Path] = [ + get_path(sp["in"]) for sp in self.conf["files_to_translate"] + ] + t_out_dir: Path = get_path("{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}") + self.out_paths: [Path] = [ + t_out_dir.joinpath(sp["out"]) for sp in self.conf["files_to_translate"] + ] self.collect_template_instances() self.init_patches() @@ -188,7 +205,9 @@ def read_src_file(self, src_path: Path) -> None: def init_patches(self): log.debug("Init patches") - priorities = dict(sorted(self.patch_priorities.items(), key=lambda item: item[1])) + priorities = dict( + sorted(self.patch_priorities.items(), key=lambda item: item[1]) + ) for ptype, p in priorities.items(): match ptype: case RegClassContains.__name__: @@ -351,8 +370,13 @@ def patch_src(self, p_list: [(bytes, Node)]) -> None: def apply_patch(self, patch: Patch) -> bool: """Tests if the given patch should be applied for the current architecture or file.""" - has_apply_only = len(patch.apply_only_to["files"]) > 0 or len(patch.apply_only_to["archs"]) > 0 - has_do_not_apply = len(patch.do_not_apply["files"]) > 0 or len(patch.do_not_apply["archs"]) > 0 + has_apply_only = ( + len(patch.apply_only_to["files"]) > 0 + or len(patch.apply_only_to["archs"]) > 0 + ) + has_do_not_apply = ( + len(patch.do_not_apply["files"]) > 0 or len(patch.do_not_apply["archs"]) > 0 + ) if not (has_apply_only or has_do_not_apply): # Lists empty. @@ -374,7 +398,9 @@ def apply_patch(self, patch: Patch) -> bool: exit(1) def translate(self) -> None: - for self.current_src_path_in, self.current_src_path_out in zip(self.src_paths, self.out_paths): + for self.current_src_path_in, self.current_src_path_out in zip( + self.src_paths, self.out_paths + ): log.info(f"Translate '{self.current_src_path_in}'") self.parse(self.current_src_path_in) patch: Patch @@ -398,7 +424,9 @@ def translate(self) -> None: # Add it to the bundle. captures_bundle[-1].append(q) - log.debug(f"Patch {patch.__class__.__name__} (to patch: {len(captures_bundle)}).") + log.debug( + f"Patch {patch.__class__.__name__} (to patch: {len(captures_bundle)})." + ) p_list: (bytes, Node) = list() cb: [(Node, str)] @@ -420,8 +448,12 @@ def translate(self) -> None: def collect_template_instances(self): search_paths = [get_path(p) for p in self.conf["files_for_template_search"]] - temp_arg_deduction = [p.encode("utf8") for p in self.conf["templates_with_arg_deduction"]] - self.template_collector = TemplateCollector(self.parser, self.ts_cpp_lang, search_paths, temp_arg_deduction) + temp_arg_deduction = [ + p.encode("utf8") for p in self.conf["templates_with_arg_deduction"] + ] + self.template_collector = TemplateCollector( + self.parser, self.ts_cpp_lang, search_paths, temp_arg_deduction + ) self.template_collector.collect() def get_patch_kwargs(self, patch): @@ -435,7 +467,8 @@ def remark_manual_files(self) -> None: if len(manual_edited) > 0: msg += ( termcolor.colored( - "The following files are too complex to translate! Please check them by hand.", attrs=["bold"] + "The following files are too complex to translate! Please check them by hand.", + attrs=["bold"], ) + "\n" ) @@ -443,7 +476,7 @@ def remark_manual_files(self) -> None: return for f in manual_edited: msg += get_path(f).name + "\n" - print_prominent_warning(msg) + print_prominent_warning(msg, self.wait_for_user) def parse_args() -> argparse.Namespace: @@ -452,7 +485,11 @@ def parse_args() -> argparse.Namespace: description="Capstones C++ to C translator for LLVM source files", ) parser.add_argument( - "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC", "AArch64", "Alpha"], required=True + "-a", + dest="arch", + help="Name of target architecture.", + choices=["ARM", "PPC", "AArch64", "Alpha"], + required=True, ) parser.add_argument( "-v", @@ -462,7 +499,11 @@ def parse_args() -> argparse.Namespace: default="info", ) parser.add_argument( - "-c", dest="config_path", help="Config file for architectures.", default="arch_config.json", type=Path + "-c", + dest="config_path", + help="Config file for architectures.", + default="arch_config.json", + type=Path, ) arguments = parser.parse_args() return arguments diff --git a/suite/auto-sync/Updater/CppTranslator/Differ.py b/suite/auto-sync/src/autosync/cpptranslator/Differ.py similarity index 61% rename from suite/auto-sync/Updater/CppTranslator/Differ.py rename to suite/auto-sync/src/autosync/cpptranslator/Differ.py index b3dd44f778..b7f6f33090 100755 --- a/suite/auto-sync/Updater/CppTranslator/Differ.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py @@ -1,29 +1,34 @@ #!/usr/bin/env python3 -import json -from enum import StrEnum -from pathlib import Path -from typing import Iterator -from tree_sitter import Language, Parser, Tree, Node -from shutil import copy2 +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import argparse import difflib as dl +import json import logging as log +import subprocess import sys +import tempfile +from enum import StrEnum +from pathlib import Path +from shutil import copy2 + +from tree_sitter import Language, Node, Parser, Tree -from CppTranslator.Configurator import Configurator -from Helper import ( +from autosync.cpptranslator.Configurator import Configurator +from autosync.Helper import ( + bold, + colored, convert_loglevel, find_id_by_type, + get_path, + get_sha256, print_prominent_info, - bold, - colored, - separator_line_1, - separator_line_2, print_prominent_warning, - get_sha256, run_clang_format, - get_path, + separator_line_1, + separator_line_2, ) @@ -35,7 +40,13 @@ class PatchCoord: start_point: tuple[int, int] end_point: tuple[int, int] - def __init__(self, start_byte: int, end_byte: int, start_point: tuple[int, int], end_point: tuple[int, int]): + def __init__( + self, + start_byte: int, + end_byte: int, + start_point: tuple[int, int], + end_point: tuple[int, int], + ): self.start_byte = start_byte self.end_byte = end_byte self.start_point = start_point @@ -58,7 +69,9 @@ def __str__(self) -> str: @staticmethod def get_coordinates_from_node(node: Node): - return PatchCoord(node.start_byte, node.end_byte, node.start_point, node.end_point) + return PatchCoord( + node.start_byte, node.end_byte, node.start_point, node.end_point + ) class ApplyType(StrEnum): @@ -66,6 +79,7 @@ class ApplyType(StrEnum): NEW = "NEW" # Apply version from new file (leave unchanged) SAVED = "SAVED" # Use saved resolution EDIT = "EDIT" # Edit patch and apply + SHOW_EDIT = "SHOW_EDIT" # Show the saved edited text. OLD_ALL = "OLD_ALL" # Apply all versions from old file. PREVIOUS = "PREVIOUS" # Ignore diff and go to previous @@ -81,7 +95,13 @@ class Patch: new_hash: str def __init__( - self, node_id: str, old: bytes, new: bytes, coord: PatchCoord, apply: ApplyType, edit: bytes = None + self, + node_id: str, + old: bytes, + new: bytes, + coord: PatchCoord, + apply: ApplyType, + edit: bytes = None, ) -> None: if apply == ApplyType.SAVED: raise NotImplementedError("Not yet implemented.") @@ -133,6 +153,41 @@ def __str__(self) -> str: class Differ: """ Diffs the newly translated C++ files against the old version. + + The general diffing works like this: + + The old and the new file get parsed with tree sitter into an AST. + Then, we extract all nodes of a specific type out of this AST. + Which nodes specifically is defined in "arch_config.json::General::nodes_to_diff". + + These nodes (old and new separately) are than sorted descending by their coordinates. + Meaning, nodes at the end in the file come first. + The identifiers of those nodes are saved in a single list. + Now we iterate over this list of identifiers. Now we make decisions: + + The node id is present as: + old node & new node => Text matches? + yes => Continue + no => Add new node as Patch (see below) + only old node => We save all consecutive old nodes, which have _no_ equivalent new node + and add them as single patch + only new node => Add patch + + Now we have the patch. We have a persistence file which saved previous decisions, on which patch to choose. + We take the node text of the old and new node (or only from a single one) and compare them to our previous decision. + If the text of the nodes didn't change since the last run, we auto-apply the patch. + Otherwise, the user decides: + - Choose the old node text + - Choose the new node text + - Open the editor to edit the patch and apply it. + - Use the stored previous decision. + - Select always the old nodes. + - Go back and decide on node before. + + Each decision is saved to the persistence file for later. + + Last (optional) step is to write the patches to the new file. + Please note that we always write to the new file in the current version. """ ts_cpp_lang: Language = None @@ -148,11 +203,13 @@ class Differ: patches: list[Patch] current_patch: Patch - cur_old_node: Node = None - cur_new_node: Node = None + cur_old_node: Node | None = None + cur_new_node: Node | None = None cur_nid: str = None - def __init__(self, configurator: Configurator, no_auto_apply: bool): + def __init__( + self, configurator: Configurator, no_auto_apply: bool, testing: bool = False + ): self.configurator = configurator self.no_auto_apply = no_auto_apply self.arch = self.configurator.get_arch() @@ -161,18 +218,41 @@ def __init__(self, configurator: Configurator, no_auto_apply: bool): self.ts_cpp_lang = self.configurator.get_cpp_lang() self.parser = self.configurator.get_parser() self.differ = dl.Differ() - - t_out_dir: Path = get_path(self.conf_general["translation_out_dir"]) - self.translated_files = [t_out_dir.joinpath(sp["out"]) for sp in self.conf_arch["files_to_translate"]] - cs_arch_src: Path = get_path("{CS_ARCH_MODULE_DIR}") - cs_arch_src = cs_arch_src.joinpath(self.arch if self.arch != "PPC" else "PowerPC") - self.old_files = [ - cs_arch_src.joinpath(f"{cs_arch_src}/" + sp["out"]) for sp in self.conf_arch["files_to_translate"] - ] - self.load_persistence_file() + self.testing = testing + + self.diff_out_dir = get_path("{CPP_TRANSLATOR_DIFF_OUT_DIR}") + if self.testing: + t_out_dir: Path = get_path("{DIFFER_TEST_NEW_SRC_DIR}") + self.translated_files = [ + t_out_dir.joinpath(sp["out"]) + for sp in self.conf_arch["files_to_translate"] + ] + self.old_files = [ + get_path("{DIFFER_TEST_OLD_SRC_DIR}").joinpath(sp["out"]) + for sp in self.conf_arch["files_to_translate"] + ] + self.load_persistence_file() + else: + t_out_dir: Path = get_path("{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}") + self.translated_files = [ + t_out_dir.joinpath(sp["out"]) + for sp in self.conf_arch["files_to_translate"] + ] + cs_arch_src: Path = get_path("{CS_ARCH_MODULE_DIR}") + cs_arch_src = cs_arch_src.joinpath( + self.arch if self.arch != "PPC" else "PowerPC" + ) + self.old_files = [ + cs_arch_src.joinpath(f"{cs_arch_src}/" + sp["out"]) + for sp in self.conf_arch["files_to_translate"] + ] + self.load_persistence_file() def load_persistence_file(self) -> None: - self.persistence_filepath = get_path(self.conf_general["patch_persistence_file"]) + if self.testing: + self.persistence_filepath = get_path("{DIFFER_TEST_PERSISTENCE_FILE}") + else: + self.persistence_filepath = get_path("{DIFFER_PERSISTENCE_FILE}") if not self.persistence_filepath.exists(): self.saved_patches = dict() return @@ -181,7 +261,9 @@ def load_persistence_file(self) -> None: try: self.saved_patches = json.load(f) except json.decoder.JSONDecodeError as e: - log.fatal(f"Persistence file {bold(self.persistence_filepath.name)} corrupt.") + log.fatal( + f"Persistence file {bold(self.persistence_filepath.name)} corrupt." + ) log.fatal("Delete it or fix it by hand.") log.fatal(f"JSON Exception: {e}") exit(1) @@ -191,6 +273,10 @@ def save_to_persistence_file(self) -> None: json.dump(self.saved_patches, f, indent=2) def persist_patch(self, filename: Path, patch: Patch) -> None: + """ + :param filename: The filename this patch is saved for. + :param patch: The patch to apply. + """ if filename.name not in self.saved_patches: self.saved_patches[filename.name] = dict() log.debug(f"Save: {patch.get_persist_info()}") @@ -201,14 +287,19 @@ def copy_files(self) -> None: Copy translated files to diff directory for editing. """ log.info("Copy files for editing") - diff_dir: Path = get_path(self.conf_general["diff_out_dir"]) + diff_dir: Path = self.diff_out_dir for f in self.translated_files: dest = diff_dir.joinpath(f.name) copy2(f, dest) self.diff_dest_files.append(dest) def get_diff_intro_msg( - self, old_filename: Path, new_filename: Path, current: int, total: int, num_diffs: int + self, + old_filename: Path, + new_filename: Path, + current: int, + total: int, + num_diffs: int, ) -> str: color_new = self.conf_general["diff_color_new"] color_old = self.conf_general["diff_color_old"] @@ -229,7 +320,9 @@ def get_diff_node_id(self, node: Node) -> bytes: if n["node_type"] == node.type: id_types = n["identifier_node_type"] if not id_types: - log.fatal(f"Diffing: Node of type {node.type} has not identifier type specified.") + log.fatal( + f"Diffing: Node of type {node.type} has not identifier type specified." + ) exit(1) identifier = "" for id_type in id_types: @@ -241,7 +334,7 @@ def get_diff_node_id(self, node: Node) -> bytes: exit(1) return identifier - def parse_file(self, file: Path) -> dict: + def parse_file(self, file: Path) -> dict[str:Node]: """ Parse a files and return all nodes which should be diffed. Nodes are indexed by a unique identifier. @@ -251,7 +344,9 @@ def parse_file(self, file: Path) -> dict: tree: Tree = self.parser.parse(content, keep_text=True) - node_types_to_diff = [n["node_type"] for n in self.conf_general["nodes_to_diff"]] + node_types_to_diff = [ + n["node_type"] for n in self.conf_general["nodes_to_diff"] + ] content = None if file.suffix == ".h": # Header file. Get the content in between the include guard @@ -283,11 +378,13 @@ def parse_file(self, file: Path) -> dict: def print_diff(self, diff_lines: list[str], node_id: str, current: int, total: int): new_color = self.conf_general["diff_color_new"] old_color = self.conf_general["diff_color_old"] - print(separator_line_1()) + print(separator_line_2()) print(f"{bold('Patch:')} {current}/{total}\n") print(f"{bold('Node:')} {node_id}") print(f"{bold('Color:')} {colored('NEW FILE - (Just translated)', new_color)}") - print(f"{bold('Color:')} {colored('OLD FILE - (Currently in Capstone)', old_color)}\n") + print( + f"{bold('Color:')} {colored('OLD FILE - (Currently in Capstone)', old_color)}\n" + ) print(separator_line_1()) for line in diff_lines: if line[0] == "+": @@ -301,13 +398,15 @@ def print_diff(self, diff_lines: list[str], node_id: str, current: int, total: i print(separator_line_2()) @staticmethod - def no_difference(diff_lines: Iterator[str]) -> bool: + def no_difference(diff_lines: list[str]) -> bool: for line in diff_lines: if line[0] != " ": return False return True - def print_prompt(self, saved_diff_present: bool = False, saved_choice: ApplyType = None) -> str: + def print_prompt( + self, saved_diff_present: bool = False, saved_choice: ApplyType = None + ) -> str: new_color = self.conf_general["diff_color_new"] old_color = self.conf_general["diff_color_old"] edited_color = self.conf_general["diff_color_edited"] @@ -315,15 +414,19 @@ def print_prompt(self, saved_diff_present: bool = False, saved_choice: ApplyType choice = input( f"Choice: {colored('O', old_color)}, {bold('o', old_color)}, {bold('n', new_color)}, " - f"{saved_selection}, {colored('e', edited_color)}, p, q, ? > " + f"{saved_selection}, {colored('e', edited_color)}, {colored('E', edited_color)}, p, q, ? > " ) return choice - def get_saved_choice_prompt(self, saved_diff_present: bool = False, saved_choice: ApplyType = None): + def get_saved_choice_prompt( + self, saved_diff_present: bool = False, saved_choice: ApplyType = None + ): new_color = self.conf_general["diff_color_new"] old_color = self.conf_general["diff_color_old"] edited_color = self.conf_general["diff_color_edited"] - saved_color = self.conf_general["diff_color_saved"] if saved_diff_present else "dark_grey" + saved_color = ( + self.conf_general["diff_color_saved"] if saved_diff_present else "dark_grey" + ) saved_selection = f"{bold('s', saved_color)}" if saved_choice == ApplyType.OLD: saved_selection += f" ({colored('old', old_color)}) " @@ -335,7 +438,9 @@ def get_saved_choice_prompt(self, saved_diff_present: bool = False, saved_choice saved_selection += f" ({colored('none', 'dark_grey')}) " return saved_selection - def print_prompt_help(self, saved_diff_present: bool = False, saved_choice: ApplyType = None) -> None: + def print_prompt_help( + self, saved_diff_present: bool = False, saved_choice: ApplyType = None + ) -> None: new_color = self.conf_general["diff_color_new"] old_color = self.conf_general["diff_color_old"] edited_color = self.conf_general["diff_color_edited"] @@ -352,10 +457,12 @@ def print_prompt_help(self, saved_diff_present: bool = False, saved_choice: Appl f"?\t\t- Show this help\n\n" ) - def get_user_choice(self, saved_diff_present: bool, saved_choice: ApplyType) -> ApplyType: + def get_user_choice( + self, saved_diff_present: bool, saved_choice: ApplyType + ) -> ApplyType: while True: choice = self.print_prompt(saved_diff_present, saved_choice) - if choice not in ["O", "o", "n", "e", "s", "p", "q", "?", "help"]: + if choice not in ["O", "o", "n", "e", "E", "s", "p", "q", "?", "help"]: print(f"{bold(choice)} is not valid.") self.print_prompt_help(saved_diff_present, saved_choice) continue @@ -372,6 +479,8 @@ def get_user_choice(self, saved_diff_present: bool, saved_choice: ApplyType) -> return ApplyType.OLD_ALL elif choice == "e": return ApplyType.EDIT + elif choice == "E": + return ApplyType.SHOW_EDIT elif choice == "s": return ApplyType.SAVED elif choice in ["?", "help"]: @@ -391,10 +500,23 @@ def saved_patch_matches(self, saved: dict) -> bool: new_hash = "" return saved["old_hash"] == old_hash and saved["new_hash"] == new_hash - def create_patch(self, coord: PatchCoord, choice: ApplyType, saved_patch: dict = None): + def create_patch( + self, + coord: PatchCoord, + choice: ApplyType, + saved_patch: dict = None, + edited_text: bytes = None, + ): old = self.cur_old_node.text if self.cur_old_node else b"" new = self.cur_new_node.text if self.cur_new_node else b"" - return Patch(self.cur_nid, old, new, coord, saved_patch["apply_type"] if saved_patch else choice) + return Patch( + self.cur_nid, + old, + new, + coord, + saved_patch["apply_type"] if saved_patch else choice, + edit=edited_text, + ) def add_patch( self, @@ -402,8 +524,12 @@ def add_patch( consec_old: int, old_filepath: Path, patch_coord: PatchCoord, + saved_patch: dict | None = None, + edited_text: bytes | None = None, ) -> None: - self.current_patch = self.create_patch(patch_coord, apply_type) + self.current_patch = self.create_patch( + patch_coord, apply_type, saved_patch, edited_text + ) self.persist_patch(old_filepath, self.current_patch) if consec_old > 1: # Two or more old nodes are not present in the new file. @@ -412,18 +538,34 @@ def add_patch( else: self.patches.append(self.current_patch) - def diff_nodes(self, old_filepath: Path, new_nodes: dict[bytes, Node], old_nodes: dict[bytes, Node]) -> list[Patch]: + def diff_nodes( + self, + old_filepath: Path, + new_nodes: dict[bytes, Node], + old_nodes: dict[bytes, Node], + ) -> list[Patch]: """ Asks the user for each different node, which version should be written. It writes the choice to a file, so the previous choice can be applied again if nothing changed. """ # Sort list of nodes descending. # This is necessary because - # a) we need to apply the patches backwards (so the coordinates in the file don't change. + # a) we need to apply the patches backwards (starting from the end of the file, + # so the coordinates in the file don't change, when replace text). # b) If there is an old node, which is not present in the new file, we search for # a node which is adjacent (random node order wouldn't allow this). - new_nodes = {k: v for k, v in sorted(new_nodes.items(), key=lambda item: item[1].start_byte, reverse=True)} - old_nodes = {k: v for k, v in sorted(old_nodes.items(), key=lambda item: item[1].start_byte, reverse=True)} + new_nodes = { + k: v + for k, v in sorted( + new_nodes.items(), key=lambda item: item[1].start_byte, reverse=True + ) + } + old_nodes = { + k: v + for k, v in sorted( + old_nodes.items(), key=lambda item: item[1].start_byte, reverse=True + ) + } # Collect all node ids of this file node_ids = set() @@ -433,36 +575,48 @@ def diff_nodes(self, old_filepath: Path, new_nodes: dict[bytes, Node], old_nodes # The initial patch coordinates point after the last node in the file. n0 = new_nodes[list(new_nodes.keys())[0]] - patch_coord = PatchCoord(n0.end_byte, n0.end_byte, n0.end_point, n0.end_point) + PatchCoord(n0.end_byte, n0.end_byte, n0.end_point, n0.end_point) node_ids = sorted(node_ids) self.patches = list() matching_nodes_count = 0 - # Counts the number of old nodes which have no equivalent new node. + # Counts the number of _consecutive_ old nodes which have no equivalent new node. + # They will be merged to a single patch later consec_old = 0 - choice: ApplyType = None - i = 0 - while i < len(node_ids): - self.cur_nid = node_ids[i] - self.cur_new_node = None - if self.cur_nid in new_nodes: - self.cur_new_node = new_nodes[self.cur_nid] - self.cur_old_node = None - if self.cur_nid in old_nodes: - self.cur_old_node = old_nodes[self.cur_nid] - - n = self.cur_new_node.text.decode("utf8").splitlines() if self.cur_new_node else [""] - o = self.cur_old_node.text.decode("utf8").splitlines() if self.cur_old_node else [""] + choice: ApplyType | None = None + idx = 0 + while idx < len(node_ids): + self.cur_nid = node_ids[idx] + self.cur_new_node = ( + None if self.cur_nid not in new_nodes else new_nodes[self.cur_nid] + ) + self.cur_old_node = ( + None if self.cur_nid not in old_nodes else old_nodes[self.cur_nid] + ) + + n = ( + self.cur_new_node.text.decode("utf8").splitlines() + if self.cur_new_node + else [""] + ) + o = ( + self.cur_old_node.text.decode("utf8").splitlines() + if self.cur_old_node + else [""] + ) diff_lines = list(self.differ.compare(o, n)) if self.no_difference(diff_lines): - log.debug(f"Nodes {bold(self.cur_nid)} match.") + log.info( + f"{bold('Patch:')} {idx + 1}/{len(node_ids)} - Nodes {bold(self.cur_nid)} match." + ) matching_nodes_count += 1 - i += 1 + idx += 1 continue if self.cur_new_node: consec_old = 0 + # We always write to the new file. So we always take he coordinates form it. patch_coord = PatchCoord.get_coordinates_from_node(self.cur_new_node) else: consec_old += 1 @@ -473,38 +627,50 @@ def diff_nodes(self, old_filepath: Path, new_nodes: dict[bytes, Node], old_nodes j = old_node_ids.index(self.cur_nid) while j >= 0 and (old_node_ids[j] not in new_nodes.keys()): j -= 1 - ref_new: Node = new_nodes[old_node_ids[j]] if old_node_ids[j] in new_nodes.keys() else new_nodes[0] + ref_new: Node = ( + new_nodes[old_node_ids[j]] + if old_node_ids[j] in new_nodes.keys() + else new_nodes[0] + ) ref_end_byte = ref_new.start_byte + # We always write to the new file. So we always take he coordinates form it. patch_coord = PatchCoord( ref_end_byte - 1, ref_end_byte - 1, - ref_end_byte, - ref_end_byte, + ref_new.start_point, + ref_new.start_point, ) save_exists = False - saved = None - if old_filepath.name in self.saved_patches and self.cur_nid in self.saved_patches[old_filepath.name]: - saved: dict = self.saved_patches[old_filepath.name][self.cur_nid] + saved: dict | None = None + if ( + old_filepath.name in self.saved_patches + and self.cur_nid in self.saved_patches[old_filepath.name] + ): + saved = self.saved_patches[old_filepath.name][self.cur_nid] save_exists = True if self.saved_patch_matches(saved) and not self.no_auto_apply: apply_type = ApplyType(saved["apply_type"]) self.add_patch(apply_type, consec_old, old_filepath, patch_coord) - log.info(f"Auto apply patch for {bold(self.cur_nid)}") - i += 1 + log.info( + f"{bold('Patch:')} {idx + 1}/{len(node_ids)} - Auto apply patch for {bold(self.cur_nid)}" + ) + idx += 1 continue if choice == ApplyType.OLD_ALL: self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord) - i += 1 + idx += 1 continue - self.print_diff(diff_lines, self.cur_nid, i + 1, len(node_ids)) - choice = self.get_user_choice(save_exists, None if not saved else saved["apply_type"]) + self.print_diff(diff_lines, self.cur_nid, idx + 1, len(node_ids)) + choice = self.get_user_choice( + save_exists, None if not saved else saved["apply_type"] + ) if choice == ApplyType.OLD: if not self.cur_old_node: # No data in old node. Skip - i += 1 + idx += 1 continue self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord) elif choice == ApplyType.NEW: @@ -514,20 +680,43 @@ def diff_nodes(self, old_filepath: Path, new_nodes: dict[bytes, Node], old_nodes if not save_exists: print(bold("Save does not exist.")) continue - self.add_patch(saved["apply_type"], consec_old, old_filepath, patch_coord) + self.add_patch( + saved["apply_type"], + consec_old, + old_filepath, + patch_coord, + saved_patch=saved, + edited_text=saved["edit"].encode(), + ) + elif choice == ApplyType.SHOW_EDIT: + if not saved or not saved["edit"]: + print(bold("No edited text was saved before.")) + input("Press enter to continue...\n") + continue + saved_edited_text = colored( + f'\n{saved["edit"]}\n', self.conf_general["diff_color_edited"] + ) + print(saved_edited_text) + input("Press enter to continue...\n") + continue elif choice == ApplyType.OLD_ALL: self.add_patch(ApplyType.OLD, consec_old, old_filepath, patch_coord) elif choice == ApplyType.EDIT: - print(f"{bold('Editing not yet implemented.', 'light_red')}") - continue + edited_text = self.edit_patch(diff_lines) + if not edited_text: + continue + self.persist_patch( + old_filepath, + self.create_patch(patch_coord, choice, edited_text=edited_text), + ) elif choice == ApplyType.PREVIOUS: - if i == 0: + if idx == 0: print(bold(f"There is no previous diff for {old_filepath.name}!")) input("Press enter...") continue - i -= 1 + idx -= 1 continue - i += 1 + idx += 1 log.info(f"Number of matching nodes = {matching_nodes_count}") return self.patches @@ -558,10 +747,16 @@ def diff(self) -> None: old_filepath = old_file[k]["filepath"] new_filepath = new_file[k]["filepath"] diffs_to_process = max(len(new_file[k]["nodes"]), len(old_file[k]["nodes"])) - print_prominent_info(self.get_diff_intro_msg(old_filepath, new_filepath, k + 1, i, diffs_to_process)) + print_prominent_info( + self.get_diff_intro_msg( + old_filepath, new_filepath, k + 1, i, diffs_to_process + ) + ) if diffs_to_process == 0: continue - patches[new_filepath] = self.diff_nodes(old_filepath, new_file[k]["nodes"], old_file[k]["nodes"]) + patches[new_filepath] = self.diff_nodes( + old_filepath, new_file[k]["nodes"], old_file[k]["nodes"] + ) self.patch_files(patches) log.info("Done") @@ -590,6 +785,38 @@ def patch_files(self, file_patches: dict[Path, list[Patch]]) -> None: run_clang_format(list(file_patches.keys())) return + def edit_patch(self, diff_lines: list[str]) -> bytes | None: + tmp_file = tempfile.NamedTemporaryFile(suffix="c", delete=False) + tmp_file_name = tmp_file.name + tmp_file.writelines([line.encode() + b"\n" for line in diff_lines]) + tmp_file.write(self.get_edit_explanation()) + tmp_file.close() + editor = self.conf_general["patch_editor"] + try: + subprocess.run([editor, tmp_file_name]) + except FileNotFoundError: + log.error(f"Could not find editor '{editor}'") + return None + edited_text = b"" + with open(tmp_file_name, "rb") as tmp_file: + for line in tmp_file.readlines(): + if self.get_separator_line() in line: + break + edited_text += line + tmp_file.close() + return edited_text + + @staticmethod + def get_separator_line() -> bytes: + return f"// {'=' * 50}".encode() + + def get_edit_explanation(self) -> bytes: + return ( + f"{self.get_separator_line().decode('utf8')}\n" + "// Everything below this line will be deleted\n" + "// Edit the file to your liking. The result will be written 'as is' to the source file.\n" + ).encode() + def parse_args() -> argparse.Namespace: parser = argparse.ArgumentParser( @@ -603,7 +830,11 @@ def parse_args() -> argparse.Namespace: action="store_true", ) parser.add_argument( - "-a", dest="arch", help="Name of target architecture.", choices=["ARM", "PPC, AArch64", "Alpha"], required=True + "-a", + dest="arch", + help="Name of target architecture (ignored with -t option)", + choices=["ARM", "PPC, AArch64", "Alpha"], + required=True, ) parser.add_argument( "-v", @@ -613,7 +844,7 @@ def parse_args() -> argparse.Namespace: default="info", ) parser.add_argument( - "-c", dest="config_path", help="Config file for architectures.", default="arch_config.json", type=Path + "-t", dest="testing", help="Run with test configuration.", action="store_true" ) arguments = parser.parse_args() return arguments @@ -629,9 +860,12 @@ def parse_args() -> argparse.Namespace: stream=sys.stdout, format="%(levelname)-5s - %(message)s", ) - cfg = Configurator(args.arch, args.config_path) + if args.testing: + cfg = Configurator("ARCH", get_path("{DIFFER_TEST_CONFIG_FILE}")) + else: + cfg = Configurator(args.arch, get_path("{CPP_TRANSLATOR_CONFIG}")) - differ = Differ(cfg, args.no_auto_apply) + differ = Differ(cfg, args.no_auto_apply, testing=args.testing) try: differ.diff() except Exception as e: diff --git a/suite/auto-sync/Updater/CppTranslator/README.md b/suite/auto-sync/src/autosync/cpptranslator/README.md similarity index 95% rename from suite/auto-sync/Updater/CppTranslator/README.md rename to suite/auto-sync/src/autosync/cpptranslator/README.md index 243d41b052..5d388dc962 100644 --- a/suite/auto-sync/Updater/CppTranslator/README.md +++ b/suite/auto-sync/src/autosync/cpptranslator/README.md @@ -1,3 +1,8 @@ + + # C++ Translator Capstone uses source files from LLVM to disassemble opcodes. @@ -13,16 +18,14 @@ The configuration for each architecture is set in `arch_config.json`. The config values have the following meaning: - `General`: Settings valid for all architectures. - - `patch_persistent_file`: Path to the file which saves the selections from the `Differ`. - - `translation_out_dir`: Path to the directory where the `CppTranslator` stores its files. - - `diff_out_dir`: Path to the directory where the `Differ` stores its files. - `diff_color_new`: Color in the `Differ` for translated content. - `diff_color_old`: Color in the `Differ` for old/current Capstone content. - `diff_color_saved`: Color in the `Differ` for saved content. - `diff_color_edited`: Color in the `Differ` for edited content. + - `patch_editor`: Editor to open for patch editing. - `nodes_to_diff`: List of parse tree nodes which get diffed - *Mind the note below*. - `node_type`: The `type` of the node to be diffed. - - `identifier_node_type`: Types of child nodes which identify the node during diffing (the identifier must be the same in the translated and the old file!). + - `identifier_node_type`: Types of child nodes which identify the node during diffing (the identifier must be the same in the translated and the old file!). Types can be of the form `/`. - ``: Settings valid for a specific architecture - `files_to_translate`: A list of file paths to translate. - `in`: *Path* to a specific source file. diff --git a/suite/auto-sync/Updater/CppTranslator/TemplateCollector.py b/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py similarity index 83% rename from suite/auto-sync/Updater/CppTranslator/TemplateCollector.py rename to suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py index 5f8451b572..abab53dc5c 100644 --- a/suite/auto-sync/Updater/CppTranslator/TemplateCollector.py +++ b/suite/auto-sync/src/autosync/cpptranslator/TemplateCollector.py @@ -1,11 +1,13 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + +import logging as log import re from pathlib import Path -from tree_sitter import Language, Parser -import logging as log +from tree_sitter import Language, Node, Parser, Query -from tree_sitter.binding import Query, Node -from CppTranslator.Patches.HelperMethods import get_text +from autosync.cpptranslator.patches.Helper import get_text class TemplateRefInstance: @@ -27,7 +29,9 @@ class TemplateRefInstance: # (parameters are set by the template parameters of the calling function). caller_param_indices: [{str: int}] = list() - def __init__(self, name: bytes, args: bytes, start_point, start_byte, end_point, end_byte): + def __init__( + self, name: bytes, args: bytes, start_point, start_byte, end_point, end_byte + ): self.name = name self.args = args self.start_point = start_point @@ -41,7 +45,14 @@ def __eq__(self, other): return ( self.name == other.name and self.args == other.args - and any([a == b for a, b in zip(self.caller_param_indices, other.caller_param_indices)]) + and any( + [ + a == b + for a, b in zip( + self.caller_param_indices, other.caller_param_indices + ) + ] + ) and self.start_byte == other.start_byte and self.start_point == other.start_point and self.end_byte == other.end_byte @@ -75,7 +86,13 @@ class TemplateCollector: incomplete_template_refs: {bytes: [TemplateRefInstance]} = dict() sources: [{str: bytes}] = list() - def __init__(self, ts_parser: Parser, ts_cpp: Language, searchable_files: [Path], temp_arg_deduction: [bytes]): + def __init__( + self, + ts_parser: Parser, + ts_cpp: Language, + searchable_files: [Path], + temp_arg_deduction: [bytes], + ): self.parser = ts_parser self.lang_cpp = ts_cpp self.searchable_files = searchable_files @@ -100,10 +117,17 @@ def collect(self): args = get_text(src, templ_args.start_byte, templ_args.end_byte) ti = TemplateRefInstance( - name, args, cb[0][0].start_point, cb[0][0].start_byte, cb[0][0].end_point, cb[0][0].end_byte + name, + args, + cb[0][0].start_point, + cb[0][0].start_byte, + cb[0][0].end_point, + cb[0][0].end_byte, ) - log.debug(f"Found new template ref: {name.decode('utf8')}{args.decode('utf8')}") + log.debug( + f"Found new template ref: {name.decode('utf8')}{args.decode('utf8')}" + ) if not self.contains_template_dependent_param(src, ti, cb[0]): if name not in self.template_refs: @@ -118,7 +142,10 @@ def collect(self): def resolve_dependencies(self): # Resolve dependencies of templates until nothing new was resolved. prev_len = 0 - while len(self.incomplete_template_refs) > 0 and len(self.incomplete_template_refs) != prev_len: + while ( + len(self.incomplete_template_refs) > 0 + and len(self.incomplete_template_refs) != prev_len + ): # Dict with new template calls which were previously incomplete # because one or more parameters were unknown. new_completed_tcs: {str: list} = dict() @@ -134,7 +161,9 @@ def resolve_dependencies(self): for caller_template in tc_instance_list: incomplete_tc: TemplateRefInstance for incomplete_tc in self.incomplete_template_refs[caller_name]: - new_tc: TemplateRefInstance = self.get_completed_tc(caller_template, incomplete_tc) + new_tc: TemplateRefInstance = self.get_completed_tc( + caller_template, incomplete_tc + ) callee_name = new_tc.name if callee_name not in new_completed_tcs: new_completed_tcs[callee_name] = list() @@ -149,11 +178,22 @@ def resolve_dependencies(self): self.template_refs[templ_name] = tc_list prev_len = len(self.incomplete_template_refs) if prev_len > 0: - log.info(f"Unresolved template calls: {self.incomplete_template_refs.keys()}. Patch them by hand!") + log.info( + f"Unresolved template calls: {self.incomplete_template_refs.keys()}. Patch them by hand!" + ) @staticmethod - def get_completed_tc(tc: TemplateRefInstance, itc: TemplateRefInstance) -> TemplateRefInstance: - new_tc = TemplateRefInstance(itc.name, itc.args, itc.start_byte, itc.start_byte, itc.end_point, itc.end_byte) + def get_completed_tc( + tc: TemplateRefInstance, itc: TemplateRefInstance + ) -> TemplateRefInstance: + new_tc = TemplateRefInstance( + itc.name, + itc.args, + itc.start_byte, + itc.start_byte, + itc.end_point, + itc.end_byte, + ) for indices in itc.caller_param_indices: if tc.name not in indices: # Index of other caller function. Skip. @@ -165,7 +205,9 @@ def get_completed_tc(tc: TemplateRefInstance, itc: TemplateRefInstance) -> Templ new_tc.templ_name = new_tc.name + new_tc.args return new_tc - def contains_template_dependent_param(self, src, ti: TemplateRefInstance, parse_tree: (Node, str)) -> bool: + def contains_template_dependent_param( + self, src, ti: TemplateRefInstance, parse_tree: (Node, str) + ) -> bool: """Here we check if one of the template parameters of the given template call, is a parameter of the callers template definition. @@ -201,14 +243,20 @@ def contains_template_dependent_param(self, src, ti: TemplateRefInstance, parse_ return False caller_fcn_id = node.named_children[2].named_children[0] - caller_fcn_name = get_text(src, caller_fcn_id.start_byte, caller_fcn_id.end_byte) - caller_templ_params = get_text(src, node.prev_sibling.start_byte, node.prev_sibling.end_byte) + caller_fcn_name = get_text( + src, caller_fcn_id.start_byte, caller_fcn_id.end_byte + ) + caller_templ_params = get_text( + src, node.prev_sibling.start_byte, node.prev_sibling.end_byte + ) pl = TemplateCollector.templ_params_to_list(caller_templ_params) has_parameter_dependency = False for i, param in enumerate(pl): if param in ti.args_list: has_parameter_dependency = True - ti.caller_param_indices.append({caller_fcn_name: i, "self_i": ti.args_list.index(param)}) + ti.caller_param_indices.append( + {caller_fcn_name: i, "self_i": ti.args_list.index(param)} + ) if not has_parameter_dependency: return False diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file.c b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file.c new file mode 100644 index 0000000000..3d56833594 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/new_src/diff_test_file.c @@ -0,0 +1,28 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "some_header_I.h" + +#include + +#define MACRO_A 0 +#define MACRO_B 0 + +#define FCN_MACRO_A(x) function_a(x) +#define FCN_MACRO_B(x) \ + function_b(x + 1) + +int main() { + int x = 10000 * 71; + return x; +} + +void function_a(int x) { + return; +} + +void function_b(unsigned x) { + return; +} + +void only_in_new() {} diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file.c b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file.c new file mode 100644 index 0000000000..2613598f69 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/old_src/diff_test_file.c @@ -0,0 +1,29 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +#include "some_header_I.h" + +#include + +#define MACRO_A 0 +#define MACRO_B 0 + +#define FCN_MACRO_A(x) function_a(x) +#define FCN_MACRO_B(x) \ + function_b(x) + +int main() { + int x = 71; + return x; +} + +void function_a(int x) { + return; +} + +void function_b(int x) { + return; +} + +void only_in_old_I() {} +void only_in_old_II() {} diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/test_arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/test_arch_config.json new file mode 100644 index 0000000000..9f9992364d --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Differ/test_arch_config.json @@ -0,0 +1,35 @@ +{ + "General": { + "diff_color_new": "green", + "diff_color_old": "light_blue", + "diff_color_saved": "yellow", + "diff_color_edited": "light_magenta", + "patch_editor": "vim", + "nodes_to_diff": [ + { + "node_type": "function_definition", + "identifier_node_type": ["function_declarator/identifier"] + },{ + "node_type": "preproc_function_def", + "identifier_node_type": ["identifier"] + },{ + "node_type": "preproc_include", + "identifier_node_type": ["string_literal", "system_lib_string"] + },{ + "node_type": "preproc_define", + "identifier_node_type": ["identifier"] + } + ] + }, + "ARCH": { + "files_to_translate": [ + { + "in": "{DIFFER_TEST_OLD_SRC_DIR}/diff_test_file.c", + "out": "diff_test_file.c" + } + ], + "files_for_template_search": [], + "templates_with_arg_deduction": [], + "manually_edited_files": [] + } +} diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/template_src.c b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/template_src.c new file mode 100644 index 0000000000..d36c96584a --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/template_src.c @@ -0,0 +1,7 @@ +// SPDX-FileCopyrightText: 2024 Rot127 +// SPDX-License-Identifier: BSD-3 + +int main() { + tfunction(); + tfunction(); +} diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json new file mode 100644 index 0000000000..6fc12a6141 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/Patches/test_arch_config.json @@ -0,0 +1,16 @@ +{ + "General": { + "diff_color_new": "green", + "diff_color_old": "light_blue", + "diff_color_saved": "yellow", + "diff_color_edited": "light_magenta", + "patch_editor": "vim", + "nodes_to_diff": [] + }, + "ARCH": { + "files_to_translate": [], + "files_for_template_search": ["{PATCHES_TEST_DIR}/template_src.c"], + "templates_with_arg_deduction": [], + "manually_edited_files": [] + } +} diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_differ.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_differ.py new file mode 100644 index 0000000000..9adc1ab122 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_differ.py @@ -0,0 +1,106 @@ +# SPDX-FileCopyrightText: 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import unittest + +from tree_sitter import Node + +from autosync.cpptranslator.Configurator import Configurator +from autosync.cpptranslator.Differ import ApplyType, Differ, Patch, PatchCoord +from autosync.cpptranslator.TemplateCollector import TemplateCollector + +from autosync.Helper import get_path + + +class TestHeaderPatcher(unittest.TestCase): + @classmethod + def setUpClass(cls): + configurator = Configurator("ARCH", get_path("{DIFFER_TEST_CONFIG_FILE}")) + cls.ts_cpp_lang = configurator.get_cpp_lang() + cls.parser = configurator.get_parser() + cls.template_collector = TemplateCollector( + configurator.get_parser(), configurator.get_cpp_lang(), [], [] + ) + cls.differ = Differ(configurator, testing=True, no_auto_apply=True) + + def check_persistence(self, nid, expected, apply_type, edited_text): + new_node: Node = self.new_nodes[nid] if nid in self.new_nodes else None + old_node: Node = self.old_nodes[nid] if nid in self.old_nodes else None + if not new_node: + before_old_node = old_node.start_byte - 1 + coord = PatchCoord( + before_old_node, + before_old_node, + (before_old_node, before_old_node), + (before_old_node, before_old_node), + ) + else: + coord = PatchCoord( + new_node.start_byte, + new_node.end_byte, + new_node.start_point, + new_node.end_point, + ) + patch = Patch( + node_id=nid, + old=old_node.text if old_node else b"", + new=new_node.text if new_node else b"", + coord=coord, + apply=apply_type, + edit=edited_text, + ) + self.assertEqual(patch.get_persist_info(), expected) + + def parse_files(self, filename: str): + self.old_nodes = self.differ.parse_file( + get_path("{DIFFER_TEST_OLD_SRC_DIR}").joinpath(filename) + ) + self.new_nodes = self.differ.parse_file( + get_path("{DIFFER_TEST_NEW_SRC_DIR}").joinpath(filename) + ) + + def test_patch_persistence(self): + self.parse_files("diff_test_file.c") + + nid = "function_b" + expected = { + f"{nid}": { + "apply_type": "OLD", + "edit": "aaaaaaa", + "new_hash": "e5b3e0e5c6fb1f5f39e5725e464e6dfa3c6a7f1a8a5d104801e1fc10b6f1cc2b", + "old_hash": "8fc2b2123209c37534bb60c8e38564ed773430b9fc5bca37a0ae73a64b2883ab", + } + } + edited_text: bytes = b"aaaaaaa" + self.check_persistence(nid, expected, ApplyType.OLD, edited_text) + + nid = "only_in_old_I" + expected = { + f"{nid}": { + "apply_type": "NEW", + "edit": "", + "new_hash": "", + "old_hash": "37431b6fe6707794a8e07902bef6510fc1d10b833db9b1dccc70b1530997b2b1", + } + } + self.check_persistence(nid, expected, ApplyType.NEW, b"") + self.assertRaises( + NotImplementedError, + self.check_persistence, + nid=nid, + expected=expected, + apply_type=ApplyType.SAVED, + edited_text=b"", + ) + + nid = "function_b" + expected = { + f"{nid}": { + "apply_type": "EDIT", + "edit": "aaaaaaa\n\n\n\n\n91928", + "new_hash": "e5b3e0e5c6fb1f5f39e5725e464e6dfa3c6a7f1a8a5d104801e1fc10b6f1cc2b", + "old_hash": "8fc2b2123209c37534bb60c8e38564ed773430b9fc5bca37a0ae73a64b2883ab", + } + } + edited_text: bytes = b"aaaaaaa\n\n\n\n\n91928" + self.check_persistence(nid, expected, ApplyType.EDIT, edited_text) diff --git a/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py new file mode 100644 index 0000000000..4696df7956 --- /dev/null +++ b/suite/auto-sync/src/autosync/cpptranslator/Tests/test_patches.py @@ -0,0 +1,563 @@ +#!/usr/bin/env python3 + +# Copyright © 2022 Rot127 +# SPDX-FileCopyrightText: 2024 Rot127 +# SPDX-License-Identifier: BSD-3 + +import unittest + +from tree_sitter import Node, Query + +from autosync.cpptranslator import CppTranslator + +from autosync.cpptranslator.Configurator import Configurator +from autosync.cpptranslator.patches.AddCSDetail import AddCSDetail +from autosync.cpptranslator.patches.AddOperand import AddOperand +from autosync.cpptranslator.patches.Assert import Assert +from autosync.cpptranslator.patches.BitCastStdArray import BitCastStdArray +from autosync.cpptranslator.patches.CheckDecoderStatus import CheckDecoderStatus +from autosync.cpptranslator.patches.ClassesDef import ClassesDef +from autosync.cpptranslator.patches.ConstMCInstParameter import ConstMCInstParameter +from autosync.cpptranslator.patches.ConstMCOperand import ConstMCOperand +from autosync.cpptranslator.patches.CppInitCast import CppInitCast +from autosync.cpptranslator.patches.CreateOperand0 import CreateOperand0 +from autosync.cpptranslator.patches.CreateOperand1 import CreateOperand1 +from autosync.cpptranslator.patches.DeclarationInConditionClause import ( + DeclarationInConditionalClause, +) +from autosync.cpptranslator.patches.DecodeInstruction import DecodeInstruction +from autosync.cpptranslator.patches.DecoderCast import DecoderCast +from autosync.cpptranslator.patches.DecoderParameter import DecoderParameter +from autosync.cpptranslator.patches.FallThrough import FallThrough +from autosync.cpptranslator.patches.FeatureBits import FeatureBits +from autosync.cpptranslator.patches.FeatureBitsDecl import FeatureBitsDecl +from autosync.cpptranslator.patches.FieldFromInstr import FieldFromInstr +from autosync.cpptranslator.patches.GetNumOperands import GetNumOperands +from autosync.cpptranslator.patches.GetOpcode import GetOpcode +from autosync.cpptranslator.patches.GetOperand import GetOperand +from autosync.cpptranslator.patches.GetOperandRegImm import GetOperandRegImm +from autosync.cpptranslator.patches.GetRegClass import GetRegClass +from autosync.cpptranslator.patches.GetRegFromClass import GetRegFromClass +from autosync.cpptranslator.patches.GetSubReg import GetSubReg +from autosync.cpptranslator.patches.Includes import Includes +from autosync.cpptranslator.patches.InlineToStaticInline import InlineToStaticInline +from autosync.cpptranslator.patches.IsOptionalDef import IsOptionalDef +from autosync.cpptranslator.patches.IsPredicate import IsPredicate +from autosync.cpptranslator.patches.IsRegImm import IsOperandRegImm +from autosync.cpptranslator.patches.LLVMFallThrough import LLVMFallThrough +from autosync.cpptranslator.patches.LLVMunreachable import LLVMUnreachable +from autosync.cpptranslator.patches.MethodToFunctions import MethodToFunction +from autosync.cpptranslator.patches.MethodTypeQualifier import MethodTypeQualifier +from autosync.cpptranslator.patches.NamespaceAnon import NamespaceAnon +from autosync.cpptranslator.patches.NamespaceArch import NamespaceArch +from autosync.cpptranslator.patches.NamespaceLLVM import NamespaceLLVM +from autosync.cpptranslator.patches.OutStreamParam import OutStreamParam +from autosync.cpptranslator.patches.PredicateBlockFunctions import ( + PredicateBlockFunctions, +) +from autosync.cpptranslator.patches.PrintAnnotation import PrintAnnotation +from autosync.cpptranslator.patches.PrintRegImmShift import PrintRegImmShift +from autosync.cpptranslator.patches.QualifiedIdentifier import QualifiedIdentifier +from autosync.cpptranslator.patches.ReferencesDecl import ReferencesDecl +from autosync.cpptranslator.patches.RegClassContains import RegClassContains +from autosync.cpptranslator.patches.SetOpcode import SetOpcode +from autosync.cpptranslator.patches.SignExtend import SignExtend +from autosync.cpptranslator.patches.SizeAssignments import SizeAssignment +from autosync.cpptranslator.patches.STIArgument import STIArgument +from autosync.cpptranslator.patches.STIFeatureBits import STIFeatureBits +from autosync.cpptranslator.patches.STParameter import SubtargetInfoParam +from autosync.cpptranslator.patches.StreamOperation import StreamOperations +from autosync.cpptranslator.patches.TemplateDeclaration import TemplateDeclaration +from autosync.cpptranslator.patches.TemplateDefinition import TemplateDefinition +from autosync.cpptranslator.patches.TemplateParamDecl import TemplateParamDecl +from autosync.cpptranslator.patches.TemplateRefs import TemplateRefs +from autosync.cpptranslator.patches.UseMarkup import UseMarkup +from autosync.cpptranslator.patches.UsingDeclaration import UsingDeclaration +from autosync.cpptranslator.TemplateCollector import TemplateCollector +from autosync.Helper import get_path + + +class TestPatches(unittest.TestCase): + @classmethod + def setUpClass(cls): + configurator = Configurator("ARCH", get_path("{PATCHES_TEST_CONFIG}")) + cls.translator = CppTranslator.Translator(configurator, False) + cls.ts_cpp_lang = configurator.get_cpp_lang() + cls.parser = configurator.get_parser() + cls.template_collector = TemplateCollector( + configurator.get_parser(), configurator.get_cpp_lang(), [], [] + ) + + def check_patching_result(self, patch, syntax, expected, filename=""): + if filename: + kwargs = {"filename": filename} + else: + kwargs = self.translator.get_patch_kwargs(patch) + query: Query = self.ts_cpp_lang.query(patch.get_search_pattern()) + captures_bundle: [[(Node, str)]] = list() + for q in query.captures(self.parser.parse(syntax, keep_text=True).root_node): + if q[1] == patch.get_main_capture_name(): + captures_bundle.append([q]) + else: + captures_bundle[-1].append(q) + + self.assertGreater(len(captures_bundle), 0) + for cb in captures_bundle: + self.assertEqual(patch.get_patch(cb, syntax, **kwargs), expected) + + def test_addcsdetail(self): + patch = AddCSDetail(0, "ARCH") + syntax = b"int i = x; void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O) { int i = OpNo; }" + self.check_patching_result( + patch, + syntax, + b"void printThumbLdrLabelOperand(MCInst *MI, unsigned OpNo, SStream *O){ " + b"add_cs_detail(MI, ARCH_OP_GROUP_ThumbLdrLabelOperand, OpNo); " + b"int i = OpNo; " + b"}", + ) + + def test_addoperand(self): + patch = AddOperand(0) + syntax = b"MI.addOperand(OPERAND)" + self.check_patching_result( + patch, + syntax, + b"MCInst_addOperand2(MI, (OPERAND))", + ) + + def test_assert(self): + patch = Assert(0) + syntax = b"assert(0 == 0)" + self.check_patching_result(patch, syntax, b"") + + def test_bitcaststdarray(self): + patch = BitCastStdArray(0) + syntax = b"auto S = bit_cast>(Imm);" + self.check_patching_result( + patch, + syntax, + b"union {\n" + b" typeof(Imm) In;\n" + b" int32_t Out[ 2];\n" + b"} U_S;\n" + b"U_S.In = Imm" + b";\n" + b"int32_t *S = U_S.Out;", + ) + + def test_checkdecoderstatus(self): + patch = CheckDecoderStatus(0) + syntax = b"Check(S, functions())" + self.check_patching_result(patch, syntax, b"Check(&S, functions())") + + def test_classesdef(self): + patch = ClassesDef(0) + syntax = b"""class AArch64Disassembler : public MCDisassembler { + std::unique_ptr const MCII; + +public: + AArch64Disassembler(const MCSubtargetInfo &STI, MCContext &Ctx, + MCInstrInfo const *MCII) + : MCDisassembler(STI, Ctx), MCII(MCII) {} + + ~AArch64Disassembler() override = default; + + MCDisassembler::DecodeStatus + getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes, + uint64_t Address, raw_ostream &CStream) const override; + + uint64_t suggestBytesToSkip(ArrayRef Bytes, + uint64_t Address) const override; +}; +""" + self.check_patching_result( + patch, + syntax, + b"MCDisassembler::DecodeStatus\n" + b" getInstruction(MCInst &Instr, uint64_t &Size, ArrayRef Bytes,\n" + b" uint64_t Address, raw_ostream &CStream) const override;\n" + b"uint64_t suggestBytesToSkip(ArrayRef Bytes,\n" + b" uint64_t Address) const override;\n", + ) + + def test_constmcinstparameter(self): + patch = ConstMCInstParameter(0) + syntax = b"void function(const MCInst *MI);" + expected = b"MCInst *MI" + self.check_patching_result(patch, syntax, expected) + + def test_constmcoperand(self): + patch = ConstMCOperand(0) + syntax = b"const MCOperand op = { 0 };" + self.check_patching_result(patch, syntax, b"MCOperand op = { 0 };") + + def test_cppinitcast(self): + patch = CppInitCast(0) + syntax = b"int(0x0000)" + self.check_patching_result(patch, syntax, b"((int)(0x0000))") + + def test_createoperand0(self): + patch = CreateOperand0(0) + syntax = b"Inst.addOperand(MCOperand::createReg(REGISTER));" + self.check_patching_result( + patch, + syntax, + b"MCOperand_CreateReg0(Inst, (REGISTER))", + ) + + def test_createoperand1(self): + patch = CreateOperand1(0) + syntax = b"MI.insert(I, MCOperand::createReg(REGISTER));" + self.check_patching_result( + patch, + syntax, + b"MCInst_insert0(MI, I, MCOperand_CreateReg1(MI, (REGISTER)))", + ) + + def test_declarationinconditionclause(self): + patch = DeclarationInConditionalClause(0) + syntax = b"if (int i = 0) {}" + self.check_patching_result(patch, syntax, b"int i = 0;\nif (i)\n{}") + + def test_decodeinstruction(self): + patch = DecodeInstruction(0) + syntax = ( + b"decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);" + ) + self.check_patching_result( + patch, + syntax, + b"decodeInstruction_2(DecoderTableThumb16, MI, Insn16, Address)", + ) + + syntax = b"decodeInstruction(Table[i], MI, Insn16, Address, this, STI);" + self.check_patching_result( + patch, + syntax, + b"decodeInstruction_2(Table[i], MI, Insn16, Address)", + ) + + def test_decodercast(self): + patch = DecoderCast(0) + syntax = ( + b"const MCDisassembler *Dis = static_cast(Decoder);" + ) + self.check_patching_result(patch, syntax, b"") + + def test_decoderparameter(self): + patch = DecoderParameter(0) + syntax = b"void function(const MCDisassembler *Decoder);" + self.check_patching_result(patch, syntax, b"const void *Decoder") + + def test_fallthrough(self): + patch = FallThrough(0) + syntax = b"[[fallthrough]]" + self.check_patching_result(patch, syntax, b"// fall through") + + def test_featurebitsdecl(self): + patch = FeatureBitsDecl(0) + syntax = b"const FeatureBitset &FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();" + self.check_patching_result(patch, syntax, b"") + + def test_featurebits(self): + patch = FeatureBits(0, b"ARCH") + syntax = b"bool hasD32 = featureBits[ARCH::HasV8Ops];" + self.check_patching_result( + patch, + syntax, + b"ARCH_getFeatureBits(Inst->csh->mode, ARCH::HasV8Ops)", + ) + + def test_fieldfrominstr(self): + patch = FieldFromInstr(0) + syntax = b"unsigned Rm = fieldFromInstruction(Inst16, 0, 4);" + self.check_patching_result( + patch, + syntax, + b"fieldFromInstruction_2(Inst16, 0, 4)", + ) + + syntax = b"void function(MCInst *MI, unsigned Val) { unsigned Rm = fieldFromInstruction(Val, 0, 4); }" + self.check_patching_result( + patch, + syntax, + b"fieldFromInstruction_4(Val, 0, 4)", + ) + + def test_getnumoperands(self): + patch = GetNumOperands(0) + syntax = b"MI.getNumOperands();" + self.check_patching_result(patch, syntax, b"MCInst_getNumOperands(MI)") + + def test_getopcode(self): + patch = GetOpcode(0) + syntax = b"Inst.getOpcode();" + self.check_patching_result(patch, syntax, b"MCInst_getOpcode(Inst)") + + def test_getoperand(self): + patch = GetOperand(0) + syntax = b"MI.getOperand(0);" + self.check_patching_result(patch, syntax, b"MCInst_getOperand(MI, (0))") + + def test_getoperandregimm(self): + patch = GetOperandRegImm(0) + syntax = b"OPERAND.getReg()" + self.check_patching_result(patch, syntax, b"MCOperand_getReg(OPERAND)") + + def test_getregclass(self): + patch = GetRegClass(0) + syntax = b"MRI.getRegClass(RegClass);" + expected = b"MCRegisterInfo_getRegClass(Inst->MRI, RegClass)" + self.check_patching_result(patch, syntax, expected) + + def test_getregfromclass(self): + patch = GetRegFromClass(0) + syntax = b"ARCHMCRegisterClasses[ARCH::FPR128RegClassID].getRegister(RegNo);" + self.check_patching_result( + patch, + syntax, + b"ARCHMCRegisterClasses[ARCH::FPR128RegClassID].RegsBegin[RegNo]", + ) + + def test_getsubreg(self): + patch = GetSubReg(0) + syntax = b"MRI.getSubReg(REGISTER);" + self.check_patching_result( + patch, + syntax, + b"MCRegisterInfo_getSubReg(Inst->MRI, REGISTER)", + ) + + def test_includes(self): + patch = Includes(0, "TEST_ARCH") + syntax = b'#include "some_llvm_header.h"' + self.check_patching_result( + patch, + syntax, + b"#include \n" + b"#include \n" + b"#include \n" + b"#include \n\n" + b"test_output", + "filename", + ) + + def test_inlinetostaticinline(self): + patch = InlineToStaticInline(0) + syntax = b"inline void FUNCTION() {}" + self.check_patching_result( + patch, + syntax, + b"static inline void FUNCTION() {}", + ) + + def test_isoptionaldef(self): + patch = IsOptionalDef(0) + syntax = b"OpInfo[i].isOptionalDef()" + self.check_patching_result( + patch, + syntax, + b"MCOperandInfo_isOptionalDef(&OpInfo[i])", + ) + + def test_ispredicate(self): + patch = IsPredicate(0) + syntax = b"OpInfo[i].isPredicate()" + self.check_patching_result( + patch, + syntax, + b"MCOperandInfo_isPredicate(&OpInfo[i])", + ) + + def test_isregimm(self): + patch = IsOperandRegImm(0) + syntax = b"OPERAND.isReg()" + self.check_patching_result(patch, syntax, b"MCOperand_isReg(OPERAND)") + + def test_llvmfallthrough(self): + patch = LLVMFallThrough(0) + syntax = b"LLVM_FALLTHROUGH;" + self.check_patching_result(patch, syntax, b"") + + def test_llvmunreachable(self): + patch = LLVMUnreachable(0) + syntax = b'llvm_unreachable("Error msg")' + self.check_patching_result(patch, syntax, b'assert(0 && "Error msg")') + + def test_methodtofunctions(self): + patch = MethodToFunction(0) + syntax = b"void CLASS::METHOD_NAME(int a) {}" + self.check_patching_result(patch, syntax, b"METHOD_NAME(int a)") + + def test_methodtypequalifier(self): + patch = MethodTypeQualifier(0) + syntax = b"void a_const_method() const {}" + self.check_patching_result(patch, syntax, b"a_const_method()") + + def test_namespaceanon(self): + patch = NamespaceAnon(0) + syntax = b"namespace { int a = 0; }" + self.check_patching_result(patch, syntax, b" int a = 0; ") + + def test_namespacearch(self): + patch = NamespaceArch(0) + syntax = b"namespace ArchSpecificNamespace { int a = 0; }" + self.check_patching_result( + patch, + syntax, + b"// CS namespace begin: ArchSpecificNamespace\n\n" + b"int a = 0;\n\n" + b"// CS namespace end: ArchSpecificNamespace\n\n", + ) + + def test_namespacellvm(self): + patch = NamespaceLLVM(0) + syntax = b"namespace llvm {int a = 0}" + self.check_patching_result(patch, syntax, b"int a = 0") + + def test_outstreamparam(self): + patch = OutStreamParam(0) + syntax = b"void function(int a, raw_ostream &OS);" + self.check_patching_result(patch, syntax, b"(int a, SStream *OS)") + + def test_predicateblockfunctions(self): + patch = PredicateBlockFunctions(0) + syntax = b"void function(MCInst *MI) { VPTBlock.instrInVPTBlock(); }" + self.check_patching_result( + patch, + syntax, + b"VPTBlock_instrInVPTBlock(&(MI->csh->VPTBlock))", + ) + + def test_predicateblockfunctions(self): + patch = PrintAnnotation(0) + syntax = b"printAnnotation();" + self.check_patching_result(patch, syntax, b"") + + def test_printregimmshift(self): + patch = PrintRegImmShift(0) + syntax = b"printRegImmShift(0)" + self.check_patching_result(patch, syntax, b"printRegImmShift(Inst, 0)") + + def test_qualifiedidentifier(self): + patch = QualifiedIdentifier(0) + syntax = b"NAMESPACE::ID" + self.check_patching_result(patch, syntax, b"NAMESPACE_ID") + + def test_referencesdecl(self): + patch = ReferencesDecl(0) + syntax = b"int &Param = 0;" + self.check_patching_result(patch, syntax, b"*Param") + + def test_regclasscontains(self): + patch = RegClassContains(0) + syntax = b"if (MRI.getRegClass(AArch64::GPR32RegClassID).contains(Reg)) {}" + self.check_patching_result( + patch, + syntax, + b"MCRegisterClass_contains(MRI.getRegClass(AArch64::GPR32RegClassID), Reg)", + ) + + def test_setopcode(self): + patch = SetOpcode(0) + syntax = b"Inst.setOpcode(0)" + self.check_patching_result(patch, syntax, b"MCInst_setOpcode(Inst, (0))") + + def test_signextend(self): + patch = SignExtend(0) + syntax = b"SignExtend32(0)" + self.check_patching_result(patch, syntax, b"SignExtend32((0), A)") + + def test_sizeassignments(self): + patch = SizeAssignment(0) + syntax = b"void function(int &Size) { Size = 0; }" + self.check_patching_result(patch, syntax, b"*Size = 0") + + def test_stiargument(self): + patch = STIArgument(0) + syntax = b"printSomeOperand(MI, NUM, STI, NUM)" + self.check_patching_result(patch, syntax, b"(MI, NUM, NUM)") + + def test_stifeaturebits(self): + patch = STIFeatureBits(0, b"ARCH") + syntax = b"STI.getFeatureBits()[ARCH::FLAG];" + self.check_patching_result( + patch, + syntax, + b"ARCH_getFeatureBits(Inst->csh->mode, ARCH::FLAG)", + ) + + def test_stifeaturebits(self): + patch = SubtargetInfoParam(0) + syntax = b"void function(MCSubtargetInfo &STI);" + self.check_patching_result(patch, syntax, b"()") + + def test_streamoperation(self): + patch = StreamOperations(0) + syntax = b"{ OS << 'a'; }" + self.check_patching_result(patch, syntax, b'SStream_concat0(OS, "a");\n') + + syntax = b'{ OS << "aaaa" << "bbbb" << "cccc"; }' + self.check_patching_result( + patch, + syntax, + b'SStream_concat(OS, "%s%s", "aaaa", "bbbb");\nSStream_concat0(OS, "cccc");', + ) + + syntax = b'{ OS << "aaaa" << \'a\' << "cccc"; }' + self.check_patching_result( + patch, + syntax, + b'SStream_concat(OS, "%s", "aaaa");\n' + b"SStream_concat1(OS, 'a');\n" + b'SStream_concat0(OS, "cccc");', + ) + + def test_templatedeclaration(self): + patch = TemplateDeclaration(0, self.template_collector) + syntax = b"template void tfunction();" + self.check_patching_result( + patch, + syntax, + b"#define DECLARE_tfunction(A, B) \\\n" + b" void CONCAT(tfunction, CONCAT(A, B))();\n" + b"DECLARE_tfunction(int, int);\n" + b"DECLARE_tfunction(int, char);\n", + ) + + def test_templatedefinition(self): + patch = TemplateDefinition(0, self.template_collector) + syntax = b"template void tfunction() {}" + self.check_patching_result( + patch, + syntax, + b"#define DEFINE_tfunction(A, B) \\\n" + b" void CONCAT(tfunction, CONCAT(A, B))(){}\n" + b"DEFINE_tfunction(int, int);\n" + b"DEFINE_tfunction(int, char);\n", + ) + + def test_templateparamdecl(self): + patch = TemplateParamDecl(0) + syntax = b"void function(ArrayRef x);" + self.check_patching_result(patch, syntax, b"const uint8_t *x") + + def test_templaterefs(self): + patch = TemplateRefs(0) + syntax = b"TemplateFunction();" + self.check_patching_result( + patch, + syntax, + b"CONCAT(TemplateFunction, CONCAT(A, B))", + ) + + def test_usemarkup(self): + patch = UseMarkup(0) + syntax = b"UseMarkup()" + self.check_patching_result(patch, syntax, b"getUseMarkup()") + + def test_usingdecl(self): + patch = UsingDeclaration(0) + syntax = b"using namespace llvm;" + self.check_patching_result(patch, syntax, b"") diff --git a/suite/auto-sync/Updater/CppTranslator/arch_config.json b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json similarity index 95% rename from suite/auto-sync/Updater/CppTranslator/arch_config.json rename to suite/auto-sync/src/autosync/cpptranslator/arch_config.json index 714c54451a..7b8680bd10 100644 --- a/suite/auto-sync/Updater/CppTranslator/arch_config.json +++ b/suite/auto-sync/src/autosync/cpptranslator/arch_config.json @@ -1,12 +1,10 @@ { "General": { - "patch_persistence_file": "{CPP_TRANSLATOR_DIR}/saved_patches.json", - "translation_out_dir": "{BUILD_DIR}/translate_out/", - "diff_out_dir": "{BUILD_DIR}/diff_out/", "diff_color_new": "green", "diff_color_old": "light_blue", "diff_color_saved": "yellow", "diff_color_edited": "light_magenta", + "patch_editor": "vim", "nodes_to_diff": [ { "node_type": "function_definition", @@ -116,7 +114,8 @@ "printImmSVE", "printAMIndexedWB", "isSVECpyImm", - "isSVEAddSubImm" + "isSVEAddSubImm", + "printVectorIndex" ], "manually_edited_files": [] }, diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/AddCSDetail.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py similarity index 75% rename from suite/auto-sync/Updater/CppTranslator/Patches/AddCSDetail.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py index 818e1e1d9e..9b3fef2f30 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/AddCSDetail.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddCSDetail.py @@ -1,10 +1,17 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_MCInst_var_name, template_param_list_to_dict -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import ( + get_MCInst_var_name, + get_text, + template_param_list_to_dict, +) +from autosync.cpptranslator.patches.Patch import Patch class AddCSDetail(Patch): @@ -33,7 +40,11 @@ def __init__(self, priority: int, arch: str): super().__init__(priority) self.arch = arch self.apply_only_to = { - "files": ["ARMInstPrinter.cpp", "PPCInstPrinter.cpp", "AArch64InstPrinter.cpp"], + "files": [ + "ARMInstPrinter.cpp", + "PPCInstPrinter.cpp", + "AArch64InstPrinter.cpp", + ], "archs": list(), } @@ -68,15 +79,31 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: comp = get_text(src, comp.start_byte, comp.end_byte) return b"void " + fcn_id + params + b"{ " + add_cs_detail + comp.strip(b"{") - def get_add_cs_detail(self, src: bytes, fcn_def: Node, fcn_id: bytes, params: bytes) -> bytes: - op_group_enum = self.arch.encode("utf8") + b"_OP_GROUP_" + fcn_id[5:] # Remove "print" from function id + def get_add_cs_detail( + self, src: bytes, fcn_def: Node, fcn_id: bytes, params: bytes + ) -> bytes: + op_group_enum = ( + self.arch.encode("utf8") + b"_OP_GROUP_" + fcn_id[5:] + ) # Remove "print" from function id is_template = fcn_def.prev_sibling.type == "template_parameter_list" - op_num_var_name = b"OpNum" if b"OpNum" in params else (b"OpNo" if b"OpNo" in params else b"-.-") + op_num_var_name = ( + b"OpNum" + if b"OpNum" in params + else (b"OpNo" if b"OpNo" in params else b"-.-") + ) if not is_template and op_num_var_name in params: # Standard printOperand() parameters mcinst_var = get_MCInst_var_name(src, fcn_def) - return b"add_cs_detail(" + mcinst_var + b", " + op_group_enum + b", " + op_num_var_name + b");" + return ( + b"add_cs_detail(" + + mcinst_var + + b", " + + op_group_enum + + b", " + + op_num_var_name + + b");" + ) elif op_group_enum == b"ARM_OP_GROUP_RegImmShift": return b"add_cs_detail(MI, " + op_group_enum + b", ShOpc, ShImm);" elif is_template and op_num_var_name in params: @@ -84,7 +111,9 @@ def get_add_cs_detail(self, src: bytes, fcn_def: Node, fcn_id: bytes, params: by templ_p = template_param_list_to_dict(fcn_def.prev_sibling) cs_args = b"" for tp in templ_p: - op_group_enum = b"CONCAT(" + op_group_enum + b", " + tp["identifier"] + b")" + op_group_enum = ( + b"CONCAT(" + op_group_enum + b", " + tp["identifier"] + b")" + ) cs_args += b", " + tp["identifier"] return ( b"add_cs_detail(" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/AddOperand.py b/suite/auto-sync/src/autosync/cpptranslator/patches/AddOperand.py similarity index 85% rename from suite/auto-sync/Updater/CppTranslator/Patches/AddOperand.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/AddOperand.py index 0ccc954e30..c0858f538f 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/AddOperand.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/AddOperand.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class AddOperand(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/Assert.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py similarity index 81% rename from suite/auto-sync/Updater/CppTranslator/Patches/Assert.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py index e8e3f68ecf..ce439dc2c8 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/Assert.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Assert.py @@ -1,5 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch + +from autosync.cpptranslator.patches.Patch import Patch class Assert(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/BitCastStdArray.py b/suite/auto-sync/src/autosync/cpptranslator/patches/BitCastStdArray.py similarity index 64% rename from suite/auto-sync/Updater/CppTranslator/Patches/BitCastStdArray.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/BitCastStdArray.py index 0a41c88227..2491de114c 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/BitCastStdArray.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/BitCastStdArray.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class BitCastStdArray(Patch): @@ -46,14 +49,36 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: arr_name: bytes = captures[1][0].text array_type: Node = captures[3][0] cast_target: bytes = captures[4][0].text.strip(b"()") - array_templ_args: bytes = array_type.named_children[0].named_children[1].named_children[1].text.strip(b"<>") + array_templ_args: bytes = ( + array_type.named_children[0] + .named_children[1] + .named_children[1] + .text.strip(b"<>") + ) arr_type = array_templ_args.split(b",")[0] arr_len = array_templ_args.split(b",")[1] return ( b"union {\n" - + b" typeof(" + cast_target + b") In;\n" - + b" " + arr_type + b" Out[" + arr_len + b"];\n" - + b"} U_" + arr_name + b";\n" - + b"U_" + arr_name + b".In = " + cast_target + b";\n" - + arr_type + b" *" + arr_name + b" = U_" + arr_name + b".Out;" + + b" typeof(" + + cast_target + + b") In;\n" + + b" " + + arr_type + + b" Out[" + + arr_len + + b"];\n" + + b"} U_" + + arr_name + + b";\n" + + b"U_" + + arr_name + + b".In = " + + cast_target + + b";\n" + + arr_type + + b" *" + + arr_name + + b" = U_" + + arr_name + + b".Out;" ) diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/CheckDecoderStatus.py b/suite/auto-sync/src/autosync/cpptranslator/patches/CheckDecoderStatus.py similarity index 82% rename from suite/auto-sync/Updater/CppTranslator/Patches/CheckDecoderStatus.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/CheckDecoderStatus.py index 07b0c12848..1b683ed79b 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/CheckDecoderStatus.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/CheckDecoderStatus.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class CheckDecoderStatus(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/ClassConstructorDef.py b/suite/auto-sync/src/autosync/cpptranslator/patches/ClassConstructorDef.py similarity index 83% rename from suite/auto-sync/Updater/CppTranslator/Patches/ClassConstructorDef.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/ClassConstructorDef.py index 9d6724a1c5..e7b69a463c 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/ClassConstructorDef.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/ClassConstructorDef.py @@ -1,5 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch + +from autosync.cpptranslator.patches.Patch import Patch class ClassConstructorDef(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/ClassesDef.py b/suite/auto-sync/src/autosync/cpptranslator/patches/ClassesDef.py similarity index 80% rename from suite/auto-sync/Updater/CppTranslator/Patches/ClassesDef.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/ClassesDef.py index 2945fe27fa..7309ea2fe9 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/ClassesDef.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/ClassesDef.py @@ -1,10 +1,13 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class ClassesDef(Patch): @@ -31,7 +34,9 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: for field_decl in field_decl_list.named_children: if ( field_decl.type in "field_declaration" - and ("function_declarator" in [t.type for t in field_decl.named_children]) + and ( + "function_declarator" in [t.type for t in field_decl.named_children] + ) ) or field_decl.type == "template_declaration": # Keep comments sibling = field_decl.prev_named_sibling diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/ConstMCInstParameter.py b/suite/auto-sync/src/autosync/cpptranslator/patches/ConstMCInstParameter.py similarity index 82% rename from suite/auto-sync/Updater/CppTranslator/Patches/ConstMCInstParameter.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/ConstMCInstParameter.py index 1e940f943f..7be334afc8 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/ConstMCInstParameter.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/ConstMCInstParameter.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class ConstMCInstParameter(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/ConstMCOperand.py b/suite/auto-sync/src/autosync/cpptranslator/patches/ConstMCOperand.py similarity index 82% rename from suite/auto-sync/Updater/CppTranslator/Patches/ConstMCOperand.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/ConstMCOperand.py index 38a8f36fd1..d679193902 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/ConstMCOperand.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/ConstMCOperand.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class ConstMCOperand(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/CppInitCast.py b/suite/auto-sync/src/autosync/cpptranslator/patches/CppInitCast.py similarity index 64% rename from suite/auto-sync/Updater/CppTranslator/Patches/CppInitCast.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/CppInitCast.py index 00a8114e05..e2c3e5c40b 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/CppInitCast.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/CppInitCast.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class CppInitCast(Patch): @@ -14,7 +17,12 @@ def __init__(self, priority: int): super().__init__(priority) def get_search_pattern(self) -> str: - return "(call_expression" " (primitive_type) @cast_type" " (argument_list) @cast_target" ") @cast" + return ( + "(call_expression" + " (primitive_type) @cast_type" + " (argument_list) @cast_target" + ") @cast" + ) def get_main_capture_name(self) -> str: return "cast" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/CreateOperand0.py b/suite/auto-sync/src/autosync/cpptranslator/patches/CreateOperand0.py similarity index 83% rename from suite/auto-sync/Updater/CppTranslator/Patches/CreateOperand0.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/CreateOperand0.py index c5c46abe80..04fb8d3212 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/CreateOperand0.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/CreateOperand0.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class CreateOperand0(Patch): @@ -44,7 +47,11 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: op_create_args: Node = captures[4][0] # Capstone spells the function with capital letter 'C' for whatever reason. - fcn = re.sub(b"create", b"Create", get_text(src, op_create_fcn.start_byte, op_create_fcn.end_byte)) + fcn = re.sub( + b"create", + b"Create", + get_text(src, op_create_fcn.start_byte, op_create_fcn.end_byte), + ) inst = get_text(src, inst_var.start_byte, inst_var.end_byte) args = get_text(src, op_create_args.start_byte, op_create_args.end_byte) if args[0] == b"(" and args[-1] == b")": diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/CreateOperand1.py b/suite/auto-sync/src/autosync/cpptranslator/patches/CreateOperand1.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/CreateOperand1.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/CreateOperand1.py index 5aec70f40a..2fbb442778 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/CreateOperand1.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/CreateOperand1.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_MCInst_var_name -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_MCInst_var_name, get_text +from autosync.cpptranslator.patches.Patch import Patch class CreateOperand1(Patch): @@ -50,7 +53,11 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: insert_arg_t = get_text(src, insert_arg.start_byte, insert_arg.end_byte) # Capstone spells the function with capital letter 'C' for whatever reason. - fcn = re.sub(b"create", b"Create", get_text(src, op_create_fcn.start_byte, op_create_fcn.end_byte)) + fcn = re.sub( + b"create", + b"Create", + get_text(src, op_create_fcn.start_byte, op_create_fcn.end_byte), + ) inst = get_text(src, inst_var.start_byte, inst_var.end_byte) args = get_text(src, op_create_args.start_byte, op_create_args.end_byte) return ( @@ -62,7 +69,7 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: + b"MCOperand_" + fcn + b"1(" - + get_MCInst_var_name(src, inst_var) + + inst + b", " + args + b"))" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/DeclarationInConditionClause.py b/suite/auto-sync/src/autosync/cpptranslator/patches/DeclarationInConditionClause.py similarity index 87% rename from suite/auto-sync/Updater/CppTranslator/Patches/DeclarationInConditionClause.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/DeclarationInConditionClause.py index fc6ecf108c..884a148a1d 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/DeclarationInConditionClause.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/DeclarationInConditionClause.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_capture_node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_capture_node, get_text +from autosync.cpptranslator.patches.Patch import Patch class DeclarationInConditionalClause(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/DecodeInstruction.py b/suite/auto-sync/src/autosync/cpptranslator/patches/DecodeInstruction.py similarity index 75% rename from suite/auto-sync/Updater/CppTranslator/Patches/DecodeInstruction.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/DecodeInstruction.py index 170514c739..2ac5637f0e 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/DecodeInstruction.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/DecodeInstruction.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class DecodeInstruction(Patch): @@ -31,8 +34,12 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: args_text = get_text(src, arg_list.start_byte, arg_list.end_byte).strip(b"()") table, mi_inst, opcode_var, address, this, sti = args_text.split(b",") - is_32bit = table[-2:].decode("utf8") == "32" or opcode_var[-2:].decode("utf8") == "32" - is_16bit = table[-2:].decode("utf8") == "16" or opcode_var[-2:].decode("utf8") == "16" + is_32bit = ( + table[-2:].decode("utf8") == "32" or opcode_var[-2:].decode("utf8") == "32" + ) + is_16bit = ( + table[-2:].decode("utf8") == "16" or opcode_var[-2:].decode("utf8") == "16" + ) args = table + b", " + mi_inst + b", " + opcode_var + b", " + address if is_16bit and not is_32bit: diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/DecoderCast.py b/suite/auto-sync/src/autosync/cpptranslator/patches/DecoderCast.py similarity index 88% rename from suite/auto-sync/Updater/CppTranslator/Patches/DecoderCast.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/DecoderCast.py index 605cccc562..097f6c9906 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/DecoderCast.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/DecoderCast.py @@ -1,6 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Patch import Patch class DecoderCast(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/DecoderParameter.py b/suite/auto-sync/src/autosync/cpptranslator/patches/DecoderParameter.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/DecoderParameter.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/DecoderParameter.py index af1af91e48..de7ac3531d 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/DecoderParameter.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/DecoderParameter.py @@ -1,6 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Patch import Patch class DecoderParameter(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/FallThrough.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FallThrough.py similarity index 78% rename from suite/auto-sync/Updater/CppTranslator/Patches/FallThrough.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/FallThrough.py index a9f8cd14c4..455b125bac 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/FallThrough.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FallThrough.py @@ -1,5 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch + +from autosync.cpptranslator.patches.Patch import Patch class FallThrough(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/FeatureBits.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FeatureBits.py similarity index 66% rename from suite/auto-sync/Updater/CppTranslator/Patches/FeatureBits.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/FeatureBits.py index 278060d6f6..2f37bd7d77 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/FeatureBits.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FeatureBits.py @@ -1,12 +1,16 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_MCInst_var_name -from CppTranslator.Patches.Patch import Patch + +from autosync.cpptranslator.patches.Helper import get_MCInst_var_name, get_text +from autosync.cpptranslator.patches.Patch import Patch class FeatureBits(Patch): """ Patch featureBits[FLAG] - to ARCH_getFeatureBits(Inst->csh->mode, ...) + to ARCH_getFeatureBits(Inst->csh->mode, FLAG) """ def __init__(self, priority: int, arch: bytes): @@ -30,4 +34,11 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: qualified_id: Node = captures[2][0] flag = get_text(src, qualified_id.start_byte, qualified_id.end_byte) mcinst_var_name = get_MCInst_var_name(src, qualified_id) - return self.arch + b"_getFeatureBits(" + mcinst_var_name + b"->csh->mode, " + flag + b")" + return ( + self.arch + + b"_getFeatureBits(" + + mcinst_var_name + + b"->csh->mode, " + + flag + + b")" + ) diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/FeatureBitsDecl.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FeatureBitsDecl.py similarity index 83% rename from suite/auto-sync/Updater/CppTranslator/Patches/FeatureBitsDecl.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/FeatureBitsDecl.py index aebc487e1b..233d2608b3 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/FeatureBitsDecl.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FeatureBitsDecl.py @@ -1,6 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Patch import Patch class FeatureBitsDecl(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/FieldFromInstr.py b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py similarity index 82% rename from suite/auto-sync/Updater/CppTranslator/Patches/FieldFromInstr.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py index 64f6616aff..8133e7b683 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/FieldFromInstr.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/FieldFromInstr.py @@ -1,16 +1,19 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_function_params_of_node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_function_params_of_node, get_text +from autosync.cpptranslator.patches.Patch import Patch class FieldFromInstr(Patch): """ - Patch fieldFromInstr(...) - to fieldFromInstr_(...) + Patch fieldFromInstruction(...) + to fieldFromInstruction_(...) """ def __init__(self, priority: int): @@ -32,7 +35,9 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: ffi_call: Node = captures[0][0] ffi_first_arg: Node = captures[2][0] param_list_caller = get_function_params_of_node(ffi_call) - ffi_first_arg_text = get_text(src, ffi_first_arg.start_byte, ffi_first_arg.end_byte).decode("utf8") + ffi_first_arg_text = get_text( + src, ffi_first_arg.start_byte, ffi_first_arg.end_byte + ).decode("utf8") # Determine width of instruction by the variable name. if ffi_first_arg_text[-2:] == "32": diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetNumOperands.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetNumOperands.py similarity index 83% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetNumOperands.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetNumOperands.py index bf85c2b90e..f7025b5a44 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetNumOperands.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetNumOperands.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class GetNumOperands(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetOpcode.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOpcode.py similarity index 85% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetOpcode.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetOpcode.py index 7d1cd946d9..c0251603ac 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetOpcode.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOpcode.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class GetOpcode(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetOperand.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperand.py similarity index 85% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetOperand.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetOperand.py index 66199d3c31..63ad395af8 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetOperand.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperand.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class GetOperand(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetOperandRegImm.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetOperandRegImm.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py index f3bda3d517..c47b390389 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetOperandRegImm.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetOperandRegImm.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_capture_node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_capture_node, get_text +from autosync.cpptranslator.patches.Patch import Patch class GetOperandRegImm(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetRegClass.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetRegClass.py similarity index 69% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetRegClass.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetRegClass.py index 9dca7ee584..7d3ff62d0e 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetRegClass.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetRegClass.py @@ -1,13 +1,20 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_capture_node, get_MCInst_var_name -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import ( + get_capture_node, + get_MCInst_var_name, + get_text, +) +from autosync.cpptranslator.patches.Patch import Patch class GetRegClass(Patch): """ Patch MRI.getRegClass(...) - to MCRegisterClass_getRegClass(MI->MRI, ...) + to MCRegisterInfo_getRegClass(Inst->MRI, ...) """ def __init__(self, priority: int): @@ -31,6 +38,8 @@ def get_main_capture_name(self) -> str: def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: arg_list: Node = get_capture_node(captures, "arg_list") args = get_text(src, arg_list.start_byte, arg_list.end_byte).strip(b"()") - mcinst_var = get_MCInst_var_name(src, get_capture_node(captures, "get_reg_class")) + mcinst_var = get_MCInst_var_name( + src, get_capture_node(captures, "get_reg_class") + ) res = b"MCRegisterInfo_getRegClass(" + mcinst_var + b"->MRI, " + args + b")" return res diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetRegFromClass.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetRegFromClass.py similarity index 85% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetRegFromClass.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetRegFromClass.py index 980981a79b..22aebfb192 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetRegFromClass.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetRegFromClass.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_capture_node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_capture_node, get_text +from autosync.cpptranslator.patches.Patch import Patch class GetRegFromClass(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/GetSubReg.py b/suite/auto-sync/src/autosync/cpptranslator/patches/GetSubReg.py similarity index 79% rename from suite/auto-sync/Updater/CppTranslator/Patches/GetSubReg.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/GetSubReg.py index 60e579404d..6b73cf3f3f 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/GetSubReg.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/GetSubReg.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_MCInst_var_name -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_MCInst_var_name, get_text +from autosync.cpptranslator.patches.Patch import Patch class GetSubReg(Patch): @@ -31,6 +34,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: # Get arg list op_create_args: Node = captures[2][0] - args = get_text(src, op_create_args.start_byte, op_create_args.end_byte).strip(b"()") + args = get_text(src, op_create_args.start_byte, op_create_args.end_byte).strip( + b"()" + ) mcinst_var_name = get_MCInst_var_name(src, op_create_args) return b"MCRegisterInfo_getSubReg(" + mcinst_var_name + b"->MRI, " + args + b")" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/HelperMethods.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Helper.py similarity index 85% rename from suite/auto-sync/Updater/CppTranslator/Patches/HelperMethods.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/Helper.py index 9232e980d9..45623d77ed 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/HelperMethods.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Helper.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + +import logging as log import re from tree_sitter import Node -import logging as log -from Helper import fail_exit +from autosync.Helper import fail_exit def get_function_params_of_node(n: Node) -> Node: @@ -33,9 +36,12 @@ def get_MCInst_var_name(src: bytes, n: Node) -> bytes: """Searches for the name of the parameter of type MCInst and returns it.""" params = get_function_params_of_node(n) mcinst_var_name = b"" - for p in params.named_children: - p_text = get_text(src, p.start_byte, p.end_byte) - if b"MCInst" in p_text: + + if params: + for p in params.named_children: + p_text = get_text(src, p.start_byte, p.end_byte) + if b"MCInst" not in p_text: + continue mcinst_var_name = p_text.split((b"&" if b"&" in p_text else b"*"))[1] break if mcinst_var_name == b"": @@ -46,7 +52,9 @@ def get_MCInst_var_name(src: bytes, n: Node) -> bytes: def template_param_list_to_dict(param_list: Node) -> [dict]: if param_list.type != "template_parameter_list": - log.fatal(f"Wrong node type '{param_list.type}'. Not 'template_parameter_list'.") + log.fatal( + f"Wrong node type '{param_list.type}'. Not 'template_parameter_list'." + ) exit(1) pl = list() for c in param_list.named_children: @@ -64,7 +72,9 @@ def template_param_list_to_dict(param_list: Node) -> [dict]: def parameter_declaration_to_dict(param_decl: Node) -> dict: if param_decl.type != "parameter_declaration": - log.fatal(f"Wrong node type '{param_decl.type}'. Should be 'parameter_declaration'.") + log.fatal( + f"Wrong node type '{param_decl.type}'. Should be 'parameter_declaration'." + ) exit(1) return { "prim_type": param_decl.children[0].type == "primitive_type", @@ -95,18 +105,21 @@ def namespace_enum(src: bytes, ns_id: bytes, enum: Node) -> bytes: type_id = c primary_tid_set = True - if not (enumerator_list and type_id): + if not enumerator_list and not type_id: log.fatal("Could not find enumerator_list or enum type_identifier.") exit(1) - tid = get_text(src, type_id.start_byte, type_id.end_byte) + tid = get_text(src, type_id.start_byte, type_id.end_byte) if type_id else None elist = get_text(src, enumerator_list.start_byte, enumerator_list.end_byte) for e in enumerator_list.named_children: if e.type == "enumerator": enum_entry_text = get_text(src, e.start_byte, e.end_byte) elist = elist.replace(enum_entry_text, ns_id + b"_" + enum_entry_text) - new_enum = b"typedef enum " + tid + b" " + elist + b"\n " + ns_id + b"_" + tid + if tid: + new_enum = b"typedef enum " + tid + b" " + elist + b"\n " + ns_id + b"_" + tid + else: + new_enum = b"enum " + b" " + elist + b"\n" return new_enum @@ -152,7 +165,9 @@ def namespace_struct(src: bytes, ns_id: bytes, struct: Node) -> bytes: tid = get_text(src, type_id.start_byte, type_id.end_byte) fields = get_text(src, field_list.start_byte, field_list.end_byte) - typed_struct = b"typedef struct " + tid + b" " + fields + b"\n " + ns_id + b"_" + tid + typed_struct = ( + b"typedef struct " + tid + b" " + fields + b"\n " + ns_id + b"_" + tid + ) return typed_struct @@ -193,9 +208,16 @@ def parse_function_capture( case _: raise NotImplementedError(f"Node type {node.type} not handled.") - from CppTranslator.TemplateCollector import TemplateCollector + from autosync.cpptranslator.TemplateCollector import TemplateCollector - return TemplateCollector.templ_params_to_list(temp_args), st_class_ids, ret_type, func_name, func_params, comp_stmt + return ( + TemplateCollector.templ_params_to_list(temp_args), + st_class_ids, + ret_type, + func_name, + func_params, + comp_stmt, + ) def get_capture_node(captures: [(Node, str)], name: str) -> Node: diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/Includes.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py similarity index 93% rename from suite/auto-sync/Updater/CppTranslator/Patches/Includes.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py index 154dd1242a..7d8da36f8b 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/Includes.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Includes.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class Includes(Patch): @@ -34,11 +37,17 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: include_text = get_text(src, captures[0][0].start_byte, captures[0][0].end_byte) # Special cases, which appear somewhere in the code. if b"GenDisassemblerTables.inc" in include_text: - return b'#include "' + bytes(self.arch, "utf8") + b'GenDisassemblerTables.inc"\n\n' + return ( + b'#include "' + + bytes(self.arch, "utf8") + + b'GenDisassemblerTables.inc"\n\n' + ) elif b"GenAsmWriter.inc" in include_text: return b'#include "' + bytes(self.arch, "utf8") + b'GenAsmWriter.inc"\n\n' elif b"GenSystemOperands.inc" in include_text: - return b'#include "' + bytes(self.arch, "utf8") + b'GenSystemOperands.inc"\n\n' + return ( + b'#include "' + bytes(self.arch, "utf8") + b'GenSystemOperands.inc"\n\n' + ) if self.include_count[filename] > 1: # Only the first include is replaced with all CS includes. @@ -53,6 +62,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: return res + get_PPC_includes(filename) + get_general_macros() case "AArch64": return res + get_AArch64_includes(filename) + get_general_macros() + case "TEST_ARCH": + return res + b"test_output" case _: log.fatal(f"Includes of {self.arch} not handled.") exit(1) @@ -245,4 +256,6 @@ def get_AArch64_includes(filename: str) -> bytes: def get_general_macros(): - return b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n" + return ( + b"#define CONCAT(a, b) CONCAT_(a, b)\n" b"#define CONCAT_(a, b) a ## _ ## b\n" + ) diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/InlineToStaticInline.py b/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py similarity index 70% rename from suite/auto-sync/Updater/CppTranslator/Patches/InlineToStaticInline.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py index ffffc811d2..8d07e8e099 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/InlineToStaticInline.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/InlineToStaticInline.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class InlineToStaticInline(Patch): @@ -20,7 +23,10 @@ def __init__(self, priority: int): def get_search_pattern(self) -> str: return ( - "(function_definition" ' ((storage_class_specifier) @scs (#eq? @scs "inline"))' " (_)+" ") @inline_def" + "(function_definition" + ' ((storage_class_specifier) @scs (#eq? @scs "inline"))' + " (_)+" + ") @inline_def" ) def get_main_capture_name(self) -> str: diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/IsOptionalDef.py b/suite/auto-sync/src/autosync/cpptranslator/patches/IsOptionalDef.py similarity index 83% rename from suite/auto-sync/Updater/CppTranslator/Patches/IsOptionalDef.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/IsOptionalDef.py index d289d2e002..51eafbc7c6 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/IsOptionalDef.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/IsOptionalDef.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class IsOptionalDef(Patch): @@ -34,4 +37,4 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: index = captures[2][0] op_info_var = get_text(src, op_info_var.start_byte, op_info_var.end_byte) index = get_text(src, index.start_byte, index.end_byte) - return b"MCOperandInfo_isOptionalDef(&" + op_info_var + b"[" + index + b"])" + return b"MCOperandInfo_isOptionalDef(&" + op_info_var + index + b")" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/IsPredicate.py b/suite/auto-sync/src/autosync/cpptranslator/patches/IsPredicate.py similarity index 78% rename from suite/auto-sync/Updater/CppTranslator/Patches/IsPredicate.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/IsPredicate.py index d2b3862d9f..a7b26641ba 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/IsPredicate.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/IsPredicate.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class IsPredicate(Patch): @@ -34,4 +37,4 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: index = captures[2][0] op_info_var = get_text(src, op_info_var.start_byte, op_info_var.end_byte) index = get_text(src, index.start_byte, index.end_byte) - return b"MCOperandInfo_isPredicate(&" + op_info_var + b"[" + index + b"])" + return b"MCOperandInfo_isPredicate(&" + op_info_var + index + b")" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/IsRegImm.py b/suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/IsRegImm.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py index 49cc5cd9cf..7fe5f14267 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/IsRegImm.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/IsRegImm.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class IsOperandRegImm(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/LLVMFallThrough.py b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMFallThrough.py similarity index 57% rename from suite/auto-sync/Updater/CppTranslator/Patches/LLVMFallThrough.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/LLVMFallThrough.py index 7e7e3c6c20..25b80a4c38 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/LLVMFallThrough.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMFallThrough.py @@ -1,6 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Patch import Patch class LLVMFallThrough(Patch): @@ -12,7 +15,11 @@ def __init__(self, priority: int): super().__init__(priority) def get_search_pattern(self) -> str: - return "(expression_statement" ' ((identifier) @id (#eq? @id "LLVM_FALLTHROUGH"))' ") @llvm_fall_through" + return ( + "(expression_statement" + ' ((identifier) @id (#eq? @id "LLVM_FALLTHROUGH"))' + ") @llvm_fall_through" + ) def get_main_capture_name(self) -> str: return "llvm_fall_through" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/LLVMunreachable.py b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py similarity index 80% rename from suite/auto-sync/Updater/CppTranslator/Patches/LLVMunreachable.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py index f4f34816b5..1bd243a66e 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/LLVMunreachable.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/LLVMunreachable.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class LLVMUnreachable(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/MethodToFunctions.py b/suite/auto-sync/src/autosync/cpptranslator/patches/MethodToFunctions.py similarity index 76% rename from suite/auto-sync/Updater/CppTranslator/Patches/MethodToFunctions.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/MethodToFunctions.py index 4f7fe98ff3..c4f2a21ede 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/MethodToFunctions.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/MethodToFunctions.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class MethodToFunction(Patch): @@ -35,6 +38,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: name = captures[1][0] parameter_list = captures[2][0] name = get_text(src, name.start_byte, name.end_byte) - parameter_list = get_text(src, parameter_list.start_byte, parameter_list.end_byte) + parameter_list = get_text( + src, parameter_list.start_byte, parameter_list.end_byte + ) res = name + parameter_list return res diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/MethodTypeQualifier.py b/suite/auto-sync/src/autosync/cpptranslator/patches/MethodTypeQualifier.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/MethodTypeQualifier.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/MethodTypeQualifier.py index 7d08adca7e..2f6010d806 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/MethodTypeQualifier.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/MethodTypeQualifier.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class MethodTypeQualifier(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/NamespaceAnon.py b/suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceAnon.py similarity index 63% rename from suite/auto-sync/Updater/CppTranslator/Patches/NamespaceAnon.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceAnon.py index 82b55575c3..460d9348eb 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/NamespaceAnon.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceAnon.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class NamespaceAnon(Patch): @@ -16,7 +19,11 @@ def __init__(self, priority: int): super().__init__(priority) def get_search_pattern(self) -> str: - return "(namespace_definition" " (declaration_list) @decl_list" ") @namespace_def" + return ( + "(namespace_definition" + " (declaration_list) @decl_list" + ") @namespace_def" + ) def get_main_capture_name(self) -> str: return "namespace_def" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/NamespaceArch.py b/suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceArch.py similarity index 72% rename from suite/auto-sync/Updater/CppTranslator/Patches/NamespaceArch.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceArch.py index 1d708a353d..14181aeebe 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/NamespaceArch.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceArch.py @@ -1,7 +1,15 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, namespace_enum, namespace_fcn_def, namespace_struct -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import ( + get_text, + namespace_enum, + namespace_fcn_def, + namespace_struct, +) +from autosync.cpptranslator.patches.Patch import Patch class NamespaceArch(Patch): @@ -16,7 +24,12 @@ def __init__(self, priority: int): super().__init__(priority) def get_search_pattern(self) -> str: - return "(namespace_definition" " (namespace_identifier)" " (declaration_list) @decl_list" ") @namespace_def" + return ( + "(namespace_definition" + " (namespace_identifier)" + " (declaration_list) @decl_list" + ") @namespace_def" + ) def get_main_capture_name(self) -> str: return "namespace_def" @@ -24,7 +37,11 @@ def get_main_capture_name(self) -> str: def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: namespace = captures[0][0] decl_list = captures[1][0] - namespace_id = get_text(src, namespace.named_children[0].start_byte, namespace.named_children[0].end_byte) + namespace_id = get_text( + src, + namespace.named_children[0].start_byte, + namespace.named_children[0].end_byte, + ) # We need to prepend the namespace id to all enum members, function declarators and struct types. # Because in the generated files they are accessed via NAMESPACE::X which becomes NAMESPACE_X. diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/NamespaceLLVM.py b/suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceLLVM.py similarity index 76% rename from suite/auto-sync/Updater/CppTranslator/Patches/NamespaceLLVM.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceLLVM.py index 5f737cbb45..16526f5ea1 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/NamespaceLLVM.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/NamespaceLLVM.py @@ -1,12 +1,15 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class NamespaceLLVM(Patch): """ - Patch namespace {CONTENT} + Patch namespace llvm {CONTENT} to CONTENT Only for anonymous or llvm namespaces diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/OutStreamParam.py b/suite/auto-sync/src/autosync/cpptranslator/patches/OutStreamParam.py similarity index 75% rename from suite/auto-sync/Updater/CppTranslator/Patches/OutStreamParam.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/OutStreamParam.py index b85261c6aa..e9473d1a2e 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/OutStreamParam.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/OutStreamParam.py @@ -1,13 +1,18 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class OutStreamParam(Patch): """ - Patch raw_ostream &OS - to SStream *OS + Patches the parameter list only: + + Patch void function(int a, raw_ostream &OS) + to void function(int a, SStream *OS) """ def __init__(self, priority: int): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/Patch.py b/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py similarity index 95% rename from suite/auto-sync/Updater/CppTranslator/Patches/Patch.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py index ed87f67967..6f82a0b494 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/Patch.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/Patch.py @@ -1,6 +1,10 @@ -from tree_sitter import Node +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log +from tree_sitter import Node + class Patch: priority: int = None diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/PredicateBlockFunctions.py b/suite/auto-sync/src/autosync/cpptranslator/patches/PredicateBlockFunctions.py similarity index 86% rename from suite/auto-sync/Updater/CppTranslator/Patches/PredicateBlockFunctions.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/PredicateBlockFunctions.py index 57ae872652..d4b4203276 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/PredicateBlockFunctions.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/PredicateBlockFunctions.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_MCInst_var_name -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_MCInst_var_name, get_text +from autosync.cpptranslator.patches.Patch import Patch class PredicateBlockFunctions(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/PrintAnnotation.py b/suite/auto-sync/src/autosync/cpptranslator/patches/PrintAnnotation.py similarity index 81% rename from suite/auto-sync/Updater/CppTranslator/Patches/PrintAnnotation.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/PrintAnnotation.py index f780754330..c01a6327f4 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/PrintAnnotation.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/PrintAnnotation.py @@ -1,5 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch + +from autosync.cpptranslator.patches.Patch import Patch class PrintAnnotation(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/PrintRegImmShift.py b/suite/auto-sync/src/autosync/cpptranslator/patches/PrintRegImmShift.py similarity index 81% rename from suite/auto-sync/Updater/CppTranslator/Patches/PrintRegImmShift.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/PrintRegImmShift.py index da0da5422f..e9057bf214 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/PrintRegImmShift.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/PrintRegImmShift.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_MCInst_var_name -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_MCInst_var_name, get_text +from autosync.cpptranslator.patches.Patch import Patch class PrintRegImmShift(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/QualifiedIdentifier.py b/suite/auto-sync/src/autosync/cpptranslator/patches/QualifiedIdentifier.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/QualifiedIdentifier.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/QualifiedIdentifier.py index 1c56797663..f0db97ed42 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/QualifiedIdentifier.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/QualifiedIdentifier.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class QualifiedIdentifier(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/ReferencesDecl.py b/suite/auto-sync/src/autosync/cpptranslator/patches/ReferencesDecl.py similarity index 62% rename from suite/auto-sync/Updater/CppTranslator/Patches/ReferencesDecl.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/ReferencesDecl.py index 1948514e0e..8435333d26 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/ReferencesDecl.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/ReferencesDecl.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class ReferencesDecl(Patch): @@ -18,7 +21,12 @@ def __init__(self, priority: int): super().__init__(priority) def get_search_pattern(self) -> str: - return "[" "(reference_declarator)" "(type_identifier) (abstract_reference_declarator)" "] @reference_decl" + return ( + "[" + "(reference_declarator)" + "(type_identifier) (abstract_reference_declarator)" + "] @reference_decl" + ) def get_main_capture_name(self) -> str: return "reference_decl" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/RegClassContains.py b/suite/auto-sync/src/autosync/cpptranslator/patches/RegClassContains.py similarity index 77% rename from suite/auto-sync/Updater/CppTranslator/Patches/RegClassContains.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/RegClassContains.py index 34816528b2..bf55563dfd 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/RegClassContains.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/RegClassContains.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_capture_node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_capture_node, get_text +from autosync.cpptranslator.patches.Patch import Patch class RegClassContains(Patch): @@ -32,6 +35,8 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: reg_class_getter: Node = get_capture_node(captures, "reg_class") arg_list: Node = get_capture_node(captures, "arg_list") args = get_text(src, arg_list.start_byte, arg_list.end_byte).strip(b"()") - reg_class = get_text(src, reg_class_getter.start_byte, reg_class_getter.end_byte) + reg_class = get_text( + src, reg_class_getter.start_byte, reg_class_getter.end_byte + ) res = b"MCRegisterClass_contains(" + reg_class + b", " + args + b")" return res diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/STIArgument.py b/suite/auto-sync/src/autosync/cpptranslator/patches/STIArgument.py similarity index 81% rename from suite/auto-sync/Updater/CppTranslator/Patches/STIArgument.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/STIArgument.py index fb8d6d6590..091b10122e 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/STIArgument.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/STIArgument.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class STIArgument(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/STIFeatureBits.py b/suite/auto-sync/src/autosync/cpptranslator/patches/STIFeatureBits.py similarity index 78% rename from suite/auto-sync/Updater/CppTranslator/Patches/STIFeatureBits.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/STIFeatureBits.py index 275a0d63e0..29e44cddb8 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/STIFeatureBits.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/STIFeatureBits.py @@ -1,13 +1,16 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class STIFeatureBits(Patch): """ - Patch STI.getFeatureBits()[FLAG] - to ARCH_getFeatureBits(Inst->csh->mode, ...) + Patch STI.getFeatureBits()[ARCH::FLAG] + to ARCH_getFeatureBits(Inst->csh->mode, ARCH::FLAG) """ def __init__(self, priority: int, arch: bytes): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/STParameter.py b/suite/auto-sync/src/autosync/cpptranslator/patches/STParameter.py similarity index 84% rename from suite/auto-sync/Updater/CppTranslator/Patches/STParameter.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/STParameter.py index d08e7c38d2..cf3fd1ed72 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/STParameter.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/STParameter.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class SubtargetInfoParam(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/SetOpcode.py b/suite/auto-sync/src/autosync/cpptranslator/patches/SetOpcode.py similarity index 85% rename from suite/auto-sync/Updater/CppTranslator/Patches/SetOpcode.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/SetOpcode.py index 1c2e94db57..ca46405ff6 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/SetOpcode.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/SetOpcode.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class SetOpcode(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/SignExtend.py b/suite/auto-sync/src/autosync/cpptranslator/patches/SignExtend.py similarity index 82% rename from suite/auto-sync/Updater/CppTranslator/Patches/SignExtend.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/SignExtend.py index aac3b46eb6..457e92e5f9 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/SignExtend.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/SignExtend.py @@ -1,7 +1,11 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch -from CppTranslator.TemplateCollector import TemplateCollector + +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch +from autosync.cpptranslator.TemplateCollector import TemplateCollector class SignExtend(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/SizeAssignments.py b/suite/auto-sync/src/autosync/cpptranslator/patches/SizeAssignments.py similarity index 70% rename from suite/auto-sync/Updater/CppTranslator/Patches/SizeAssignments.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/SizeAssignments.py index 08a5119e61..e9c8bccaa9 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/SizeAssignments.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/SizeAssignments.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text, get_function_params_of_node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_function_params_of_node, get_text +from autosync.cpptranslator.patches.Patch import Patch class SizeAssignment(Patch): @@ -18,7 +21,11 @@ def __init__(self, priority: int): super().__init__(priority) def get_search_pattern(self) -> str: - return "(assignment_expression" ' ((identifier) @id (#eq? @id "Size"))' ") @assign" + return ( + "(assignment_expression" + ' ((identifier) @id (#eq? @id "Size"))' + ") @assign" + ) def get_main_capture_name(self) -> str: return "assign" diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/StreamOperation.py b/suite/auto-sync/src/autosync/cpptranslator/patches/StreamOperation.py similarity index 74% rename from suite/auto-sync/Updater/CppTranslator/Patches/StreamOperation.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/StreamOperation.py index 405fb6c6f2..3bffe3cacc 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/StreamOperation.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/StreamOperation.py @@ -1,7 +1,10 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class StreamOperations(Patch): @@ -58,11 +61,22 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: + b', "' + b"%s" * len(string_ops) + b'", ' - + b", ".join([get_text(src, o.start_byte, o.end_byte) for o in string_ops]) + + b", ".join( + [ + get_text(src, o.start_byte, o.end_byte) + for o in string_ops + ] + ) + b");\n" ) string_ops.clear() - res += b"SStream_concat1(" + s_name + b", " + get_text(src, op.start_byte, op.end_byte) + b");\n" + res += ( + b"SStream_concat1(" + + s_name + + b", " + + get_text(src, op.start_byte, op.end_byte) + + b");\n" + ) else: string_ops.append(op) i += 1 @@ -75,14 +89,22 @@ def get_patch(self, captures: [(Node, str)], src: bytes, **kwargs) -> bytes: + b', "' + b"%s" * len(string_ops) + b'", ' - + b", ".join([get_text(src, o.start_byte, o.end_byte) for o in string_ops]) + + b", ".join( + [get_text(src, o.start_byte, o.end_byte) for o in string_ops] + ) + b");\n" ) string_ops.clear() last_op_text = get_text(src, last_op.start_byte, last_op.end_byte) if last_op.type == "char_literal": - res += b"SStream_concat0(" + s_name + b", " + last_op_text.replace(b"'", b'"') + b");\n" + res += ( + b"SStream_concat0(" + + s_name + + b", " + + last_op_text.replace(b"'", b'"') + + b");\n" + ) else: res += b"SStream_concat0(" + s_name + b", " + last_op_text + b");" stream = captures[0][0] diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateDeclaration.py b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateDeclaration.py similarity index 66% rename from suite/auto-sync/Updater/CppTranslator/Patches/TemplateDeclaration.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/TemplateDeclaration.py index 9141c32780..8842ba42cf 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateDeclaration.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateDeclaration.py @@ -1,9 +1,16 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import parse_function_capture -from CppTranslator.Patches.Patch import Patch -from CppTranslator.TemplateCollector import TemplateCollector, TemplateRefInstance +from autosync.cpptranslator.patches.Helper import parse_function_capture +from autosync.cpptranslator.patches.Patch import Patch +from autosync.cpptranslator.TemplateCollector import ( + TemplateCollector, + TemplateRefInstance, +) class TemplateDeclaration(Patch): @@ -37,13 +44,24 @@ def get_search_pattern(self) -> str: def get_main_capture_name(self) -> str: return "template_decl" - def get_patch(self, captures: list[tuple[Node, str]], src: bytes, **kwargs) -> bytes: + def get_patch( + self, captures: list[tuple[Node, str]], src: bytes, **kwargs + ) -> bytes: t_params, sc, tid, f_name, f_params, _ = parse_function_capture(captures, src) if f_name in self.collector.templates_with_arg_deduction: return sc + tid + b" " + f_name + f_params + b";" - declaration = b"#define DECLARE_" + f_name + b"(" + b", ".join(t_params) + b")\n" - declaration += sc + b" " + tid + b" " + TemplateCollector.get_macro_c_call(f_name, t_params, f_params) + b";" + declaration = ( + b"#define DECLARE_" + f_name + b"(" + b", ".join(t_params) + b")\n" + ) + declaration += ( + sc + + b" " + + tid + + b" " + + TemplateCollector.get_macro_c_call(f_name, t_params, f_params) + + b";" + ) declaration = declaration.replace(b"\n", b" \\\n") + b"\n" template_instance: TemplateRefInstance @@ -52,7 +70,13 @@ def get_patch(self, captures: list[tuple[Node, str]], src: bytes, **kwargs) -> b self.collector.log_missing_ref_and_exit(f_name) for template_instance in self.collector.template_refs[f_name]: - d = b"DECLARE_" + f_name + b"(" + b", ".join(template_instance.get_args_for_decl()) + b");\n" + d = ( + b"DECLARE_" + + f_name + + b"(" + + b", ".join(template_instance.get_args_for_decl()) + + b");\n" + ) if d in declared_implementations: continue declared_implementations.append(d) diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateDefinition.py b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateDefinition.py similarity index 71% rename from suite/auto-sync/Updater/CppTranslator/Patches/TemplateDefinition.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/TemplateDefinition.py index 2a7b6a79e6..4487cb7e67 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateDefinition.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateDefinition.py @@ -1,11 +1,17 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log import re from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import parse_function_capture -from CppTranslator.Patches.Patch import Patch -from CppTranslator.TemplateCollector import TemplateCollector, TemplateRefInstance +from autosync.cpptranslator.patches.Helper import parse_function_capture +from autosync.cpptranslator.patches.Patch import Patch +from autosync.cpptranslator.TemplateCollector import ( + TemplateCollector, + TemplateRefInstance, +) class TemplateDefinition(Patch): @@ -40,14 +46,23 @@ def get_search_pattern(self) -> str: def get_main_capture_name(self) -> str: return "template_def" - def get_patch(self, captures: list[tuple[Node, str]], src: bytes, **kwargs) -> bytes: - t_params, sc, tid, f_name, f_params, f_compound = parse_function_capture(captures, src) + def get_patch( + self, captures: list[tuple[Node, str]], src: bytes, **kwargs + ) -> bytes: + t_params, sc, tid, f_name, f_params, f_compound = parse_function_capture( + captures, src + ) if f_name in self.collector.templates_with_arg_deduction: return sc + tid + b" " + f_name + f_params + f_compound definition = b"#define DEFINE_" + f_name + b"(" + b", ".join(t_params) + b")\n" definition += ( - sc + b" " + tid + b" " + TemplateCollector.get_macro_c_call(f_name, t_params, f_params) + f_compound + sc + + b" " + + tid + + b" " + + TemplateCollector.get_macro_c_call(f_name, t_params, f_params) + + f_compound ) # Remove // comments definition = re.sub(b" *//.*", b"", definition) @@ -59,7 +74,13 @@ def get_patch(self, captures: list[tuple[Node, str]], src: bytes, **kwargs) -> b self.collector.log_missing_ref_and_exit(f_name) for template_instance in self.collector.template_refs[f_name]: - d = b"DEFINE_" + f_name + b"(" + b", ".join(template_instance.get_args_for_decl()) + b");\n" + d = ( + b"DEFINE_" + + f_name + + b"(" + + b", ".join(template_instance.get_args_for_decl()) + + b");\n" + ) if d in declared_implementations: continue declared_implementations.append(d) diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateParamDecl.py b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateParamDecl.py similarity index 86% rename from suite/auto-sync/Updater/CppTranslator/Patches/TemplateParamDecl.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/TemplateParamDecl.py index 5a3b066a89..2b2eb9b8ff 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateParamDecl.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateParamDecl.py @@ -1,9 +1,12 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + import logging as log from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch class TemplateParamDecl(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateRefs.py b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateRefs.py similarity index 80% rename from suite/auto-sync/Updater/CppTranslator/Patches/TemplateRefs.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/TemplateRefs.py index 12cc271bae..c858043455 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/TemplateRefs.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/TemplateRefs.py @@ -1,8 +1,11 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.HelperMethods import get_text -from CppTranslator.Patches.Patch import Patch -from CppTranslator.TemplateCollector import TemplateCollector +from autosync.cpptranslator.patches.Helper import get_text +from autosync.cpptranslator.patches.Patch import Patch +from autosync.cpptranslator.TemplateCollector import TemplateCollector class TemplateRefs(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/UseMarkup.py b/suite/auto-sync/src/autosync/cpptranslator/patches/UseMarkup.py similarity index 78% rename from suite/auto-sync/Updater/CppTranslator/Patches/UseMarkup.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/UseMarkup.py index 5dac967b11..7cfbae38c6 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/UseMarkup.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/UseMarkup.py @@ -1,5 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch + +from autosync.cpptranslator.patches.Patch import Patch class UseMarkup(Patch): diff --git a/suite/auto-sync/Updater/CppTranslator/Patches/UsingDeclaration.py b/suite/auto-sync/src/autosync/cpptranslator/patches/UsingDeclaration.py similarity index 78% rename from suite/auto-sync/Updater/CppTranslator/Patches/UsingDeclaration.py rename to suite/auto-sync/src/autosync/cpptranslator/patches/UsingDeclaration.py index 705171a5c5..cd56280fd7 100644 --- a/suite/auto-sync/Updater/CppTranslator/Patches/UsingDeclaration.py +++ b/suite/auto-sync/src/autosync/cpptranslator/patches/UsingDeclaration.py @@ -1,6 +1,9 @@ +# Copyright © 2022 Rot127 +# SPDX-License-Identifier: BSD-3 + from tree_sitter import Node -from CppTranslator.Patches.Patch import Patch +from autosync.cpptranslator.patches.Patch import Patch class UsingDeclaration(Patch): diff --git a/suite/auto-sync/src/autosync/cpptranslator/patches/__init__.py b/suite/auto-sync/src/autosync/cpptranslator/patches/__init__.py new file mode 100644 index 0000000000..e69de29bb2 diff --git a/suite/auto-sync/Updater/CppTranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json similarity index 100% rename from suite/auto-sync/Updater/CppTranslator/saved_patches.json rename to suite/auto-sync/src/autosync/cpptranslator/saved_patches.json diff --git a/suite/auto-sync/src/autosync/path_vars.json b/suite/auto-sync/src/autosync/path_vars.json new file mode 100644 index 0000000000..498f1e4518 --- /dev/null +++ b/suite/auto-sync/src/autosync/path_vars.json @@ -0,0 +1,42 @@ +{ + "paths": { + "{LLVM_ROOT}": "{AUTO_SYNC_ROOT}/vendor/llvm_root/", + "{LLVM_TARGET_DIR}": "{LLVM_ROOT}/llvm/lib/Target/", + "{LLVM_TBLGEN_BIN}": "{LLVM_ROOT}/build/bin/llvm-tblgen", + "{LLVM_INCLUDE_DIR}": "{LLVM_ROOT}/llvm/include/", + "{VENDOR_DIR}": "{AUTO_SYNC_ROOT}/vendor/", + "{BUILD_DIR}": "{AUTO_SYNC_ROOT}/build/", + "{C_INC_OUT_DIR}": "{BUILD_DIR}/llvm_c_inc/", + "{CPP_INC_OUT_DIR}": "{BUILD_DIR}/llvm_cpp_inc/", + "{CPP_TRANSLATOR_DIR}": "{AUTO_SYNC_SRC}/cpptranslator/", + "{CPP_TRANSLATOR_CONFIG}": "{CPP_TRANSLATOR_DIR}/arch_config.json", + "{CPP_TRANSLATOR_TEST_DIR}": "{CPP_TRANSLATOR_DIR}/Tests/", + "{PATCHES_TEST_DIR}": "{CPP_TRANSLATOR_TEST_DIR}/Patches/", + "{PATCHES_TEST_CONFIG}": "{PATCHES_TEST_DIR}/test_arch_config.json", + "{DIFFER_PERSISTENCE_FILE}": "{CPP_TRANSLATOR_DIR}/saved_patches.json", + "{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}": "{BUILD_DIR}/translate_out/", + "{CPP_TRANSLATOR_DIFF_OUT_DIR}": "{BUILD_DIR}/diff_out/", + "{INC_PATCH_DIR}": "{AUTO_SYNC_ROOT}/inc_patches/", + "{CS_INCLUDE_DIR}": "{CS_ROOT}/include/capstone/", + "{CS_ARCH_MODULE_DIR}": "{CS_ROOT}/arch/", + "{CS_CLANG_FORMAT_FILE}": "{CS_ROOT}/.clang-format", + "{HEADER_PATCHER_TEST_HEADER_FILE}": "{AUTO_SYNC_SRC}/Tests/test_header.h", + "{HEADER_PATCHER_TEST_INC_FILE}": "{AUTO_SYNC_SRC}/Tests/test_include.inc", + "{DIFFER_TEST_DIR}": "{CPP_TRANSLATOR_TEST_DIR}/Differ/", + "{DIFFER_TEST_CONFIG_FILE}": "{DIFFER_TEST_DIR}/test_arch_config.json", + "{DIFFER_TEST_OLD_SRC_DIR}": "{DIFFER_TEST_DIR}/old_src/", + "{DIFFER_TEST_NEW_SRC_DIR}": "{DIFFER_TEST_DIR}/new_src/", + "{DIFFER_TEST_PERSISTENCE_FILE}": "{DIFFER_TEST_DIR}/test_saved_patches.json" + }, + "create_during_runtime": [ + "{BUILD_DIR}", + "{C_INC_OUT_DIR}", + "{CPP_INC_OUT_DIR}", + "{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}", + "{CPP_TRANSLATOR_DIFF_OUT_DIR}" + ], + "ignore_missing": [ + "{DIFFER_TEST_PERSISTENCE_FILE}" + ] +} + diff --git a/suite/auto-sync/vendor/tree-sitter-cpp b/suite/auto-sync/vendor/tree-sitter-cpp index a714740214..e0c1678a78 160000 --- a/suite/auto-sync/vendor/tree-sitter-cpp +++ b/suite/auto-sync/vendor/tree-sitter-cpp @@ -1 +1 @@ -Subproject commit a71474021410973b29bfe99440d57bcd750246b1 +Subproject commit e0c1678a78731e78655b7d953efb4daecf58be46 From 16017d5f920f8cbbee0a6d942b8ceaee6fcc833c Mon Sep 17 00:00:00 2001 From: careworry <167077904+careworry@users.noreply.github.com> Date: Mon, 22 Apr 2024 11:57:11 +0800 Subject: [PATCH 10/26] chore: remove repetitive words (#2326) Signed-off-by: careworry chore: remove repetitive words --- arch/AArch64/AArch64Mapping.c | 2 +- arch/M680X/M680XDisassembler.c | 2 +- .../tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 2 +- suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h | 2 +- suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h | 2 +- suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h | 2 +- suite/synctools/tablegen/include/llvm/IR/InstrTypes.h | 2 +- suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h | 2 +- suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h | 2 +- suite/synctools/tablegen/include/llvm/Target/Target.td | 2 +- 10 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 8c1b208fc0..bb3f294f77 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -926,7 +926,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, break; case AArch64_OP_FP: { // printOperand does not handle FP operands. But sometimes - // is is used to print FP operands as normal immediate. + // is used to print FP operands as normal immediate. AArch64_get_detail_op(MI, 0)->type = AArch64_OP_IMM; AArch64_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum); AArch64_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum); diff --git a/arch/M680X/M680XDisassembler.c b/arch/M680X/M680XDisassembler.c index 2cb0958096..a0ade36733 100644 --- a/arch/M680X/M680XDisassembler.c +++ b/arch/M680X/M680XDisassembler.c @@ -209,7 +209,7 @@ static bool read_sdword(const m680x_info *info, int32_t *sdword, return true; } -// For PAGE2 and PAGE3 opcodes when using an an array of inst_page1 most +// For PAGE2 and PAGE3 opcodes when using an array of inst_page1 most // entries have M680X_INS_ILLGL. To avoid wasting memory an inst_pageX is // used which contains the opcode. Using a binary search for the right opcode // is much faster (= O(log n) ) in comparison to a linear search ( = O(n) ). diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index c4c2fc076d..c09c69b062 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -781,7 +781,7 @@ class MachineIRBuilder { /// /// \pre setBasicBlock or setMI must have been called. /// \pre \p TablePtr must be a generic virtual register with pointer type. - /// \pre \p JTI must be be a jump table index. + /// \pre \p JTI must be a jump table index. /// \pre \p IndexReg must be a generic virtual register with pointer type. /// /// \return a MachineInstrBuilder for the newly created instruction. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h index b07c7cd3db..c2b722e084 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h @@ -865,7 +865,7 @@ enum NodeType { STRICT_FP_TO_FP16, /// Perform various unary floating-point operations inspired by libm. For - /// FPOWI, the result is undefined if if the integer operand doesn't fit into + /// FPOWI, the result is undefined if the integer operand doesn't fit into /// sizeof(int). FNEG, FABS, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h b/suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h index af8c0cd875..b5cd74a8b4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ScheduleDAG.h @@ -758,7 +758,7 @@ class TargetRegisterInfo; /// be added from SUnit \p X to SUnit \p Y. void AddPredQueued(SUnit *Y, SUnit *X); - /// Updates the topological ordering to accommodate an an edge to be + /// Updates the topological ordering to accommodate an edge to be /// removed from the specified node \p N from the predecessors of the /// current node \p M. void RemovePred(SUnit *M, SUnit *N); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h index de8b0e9cfd..049dee25dd 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h @@ -3187,7 +3187,7 @@ class TargetLoweringBase { /// is[Z|FP]ExtFree of the related types is not true. virtual bool isExtFreeImpl(const Instruction *I) const { return false; } - /// Depth that GatherAllAliases should should continue looking for chain + /// Depth that GatherAllAliases should continue looking for chain /// dependencies when trying to find a more preferable chain. As an /// approximation, this should be more than the number of consecutive stores /// expected to be merged. diff --git a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h index 589926c0fa..a73285b484 100644 --- a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h +++ b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h @@ -1699,7 +1699,7 @@ class CallBase : public Instruction { paramHasAttr(ArgNo, Attribute::DereferenceableOrNull); } - /// Determine if there are is an inalloca argument. Only the last argument can + /// Determine if there is an inalloca argument. Only the last argument can /// have the inalloca attribute. bool hasInAllocaArgument() const { return !arg_empty() && paramHasAttr(arg_size() - 1, Attribute::InAlloca); diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h index 311a407f1a..caba0ee223 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h @@ -424,7 +424,7 @@ class PMDataManager { SmallVector PassVector; // Collection of Analysis provided by Parent pass manager and - // used by current pass manager. At at time there can not be more + // used by current pass manager. At time there can not be more // then PMT_Last active pass mangers. DenseMap *InheritedAnalysis[PMT_Last]; diff --git a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h index 29b55a8172..f55f521681 100644 --- a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h +++ b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h @@ -52,7 +52,7 @@ struct PassConcept { /// Polymorphic method to access the name of a pass. virtual StringRef name() const = 0; - /// Polymorphic method to to let a pass optionally exempted from skipping by + /// Polymorphic method to let a pass optionally exempted from skipping by /// PassInstrumentation. /// To opt-in, pass should implement `static bool isRequired()`. It's no-op /// to have `isRequired` always return false since that is the default. diff --git a/suite/synctools/tablegen/include/llvm/Target/Target.td b/suite/synctools/tablegen/include/llvm/Target/Target.td index d8faa63ee8..85dabebcb1 100644 --- a/suite/synctools/tablegen/include/llvm/Target/Target.td +++ b/suite/synctools/tablegen/include/llvm/Target/Target.td @@ -301,7 +301,7 @@ class RegisterClass regTypes, int alignment, string DiagnosticType = ""; // A diagnostic message to emit when an invalid value is provided for this - // register class when it is being used an an assembly operand. If this is + // register class when it is being used an assembly operand. If this is // non-empty, an anonymous diagnostic type enum value will be generated, and // the assembly matcher will provide a function to map from diagnostic types // to message strings. From bf05d695ddbcd1241e99aac259d71f681eb8c825 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Florian=20M=C3=A4rkl?= Date: Tue, 23 Apr 2024 15:57:39 +0200 Subject: [PATCH 11/26] Fix cstool Makefile for non-C99-defaulting compilers (#2315) --- cstool/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/cstool/Makefile b/cstool/Makefile index f709d3a79c..bfe568d4cd 100644 --- a/cstool/Makefile +++ b/cstool/Makefile @@ -7,6 +7,7 @@ include ../functions.mk LIBNAME = capstone CFLAGS += -I../include -I. +CFLAGS += -std=gnu99 LDFLAGS += -O3 -Wall -L.. -l$(LIBNAME) TARGET = cstool From e9284b6b367342bb1c42d7b7af946d61848f0c15 Mon Sep 17 00:00:00 2001 From: Ced2911 Date: Tue, 23 Apr 2024 15:58:40 +0200 Subject: [PATCH 12/26] check if decode[idx] is callable (#2322) --- arch/SH/SHDisassembler.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/SH/SHDisassembler.c b/arch/SH/SHDisassembler.c index 32d60a9564..879a8508a5 100644 --- a/arch/SH/SHDisassembler.c +++ b/arch/SH/SHDisassembler.c @@ -2163,7 +2163,7 @@ static bool sh_disassemble(const uint8_t *code, MCInst *MI, uint64_t address, idx = ((insn >> 8) & 0xf0) | (insn & 0x000f); } - if (decode[idx]) { + if (idx < ARR_SIZE(decode) && decode[idx]) { return decode[idx](insn, address, MI, mode, info, detail); } else { return MCDisassembler_Fail; From c4d09930710c99ab8469a4d7fc45d28b5b1b106e Mon Sep 17 00:00:00 2001 From: Shuyi Cheng Date: Tue, 23 Apr 2024 22:04:37 +0800 Subject: [PATCH 13/26] Add eBPF bswap16/32/64 instruction (#2323) --- arch/BPF/BPFDisassembler.c | 5 +- arch/BPF/BPFMapping.c | 16 ++++++ bindings/python/capstone/bpf_const.py | 77 ++++++++++++++------------- include/capstone/bpf.h | 3 ++ suite/cstest/issues.cs | 12 +++++ 5 files changed, 73 insertions(+), 40 deletions(-) diff --git a/arch/BPF/BPFDisassembler.c b/arch/BPF/BPFDisassembler.c index cc137c0171..6b3e00bdac 100644 --- a/arch/BPF/BPFDisassembler.c +++ b/arch/BPF/BPFDisassembler.c @@ -277,13 +277,12 @@ static bool decodeALU(cs_struct *ud, MCInst *MI, bpf_internal *bpf) if (BPF_OP(bpf->op) > BPF_ALU_END) return false; - /* ALU64 class doesn't have ENDian */ /* ENDian's imm must be one of 16, 32, 64 */ if (BPF_OP(bpf->op) == BPF_ALU_END) { - if (BPF_CLASS(bpf->op) == BPF_CLASS_ALU64) - return false; if (bpf->k != 16 && bpf->k != 32 && bpf->k != 64) return false; + if (BPF_CLASS(bpf->op) == BPF_CLASS_ALU64 && BPF_SRC(bpf->op) != BPF_SRC_LITTLE) + return false; } /* - op dst, imm diff --git a/arch/BPF/BPFMapping.c b/arch/BPF/BPFMapping.c index c2b7979462..17d3c55710 100644 --- a/arch/BPF/BPFMapping.c +++ b/arch/BPF/BPFMapping.c @@ -69,6 +69,9 @@ static const name_map insn_name_maps[BPF_INS_ENDING] = { { BPF_INS_BE16, "be16" }, { BPF_INS_BE32, "be32" }, { BPF_INS_BE64, "be64" }, + { BPF_INS_BSWAP16, "bswap16" }, + { BPF_INS_BSWAP32, "bswap32" }, + { BPF_INS_BSWAP64, "bswap64" }, { BPF_INS_LDW, "ldw" }, { BPF_INS_LDH, "ldh" }, @@ -211,6 +214,19 @@ static bpf_insn op2insn_alu(unsigned opcode) { /* Endian is a special case */ if (BPF_OP(opcode) == BPF_ALU_END) { + if (BPF_CLASS(opcode) == BPF_CLASS_ALU64) { + switch (opcode ^ BPF_CLASS_ALU64 ^ BPF_ALU_END ^ BPF_SRC_LITTLE) { + case (16 << 4): + return BPF_INS_BSWAP16; + case (32 << 4): + return BPF_INS_BSWAP32; + case (64 << 4): + return BPF_INS_BSWAP64; + default: + return BPF_INS_INVALID; + } + } + switch (opcode ^ BPF_CLASS_ALU ^ BPF_ALU_END) { case BPF_SRC_LITTLE | (16 << 4): return BPF_INS_LE16; diff --git a/bindings/python/capstone/bpf_const.py b/bindings/python/capstone/bpf_const.py index 671eca81bd..2dad952825 100644 --- a/bindings/python/capstone/bpf_const.py +++ b/bindings/python/capstone/bpf_const.py @@ -62,43 +62,46 @@ BPF_INS_BE16 = 30 BPF_INS_BE32 = 31 BPF_INS_BE64 = 32 -BPF_INS_LDW = 33 -BPF_INS_LDH = 34 -BPF_INS_LDB = 35 -BPF_INS_LDDW = 36 -BPF_INS_LDXW = 37 -BPF_INS_LDXH = 38 -BPF_INS_LDXB = 39 -BPF_INS_LDXDW = 40 -BPF_INS_STW = 41 -BPF_INS_STH = 42 -BPF_INS_STB = 43 -BPF_INS_STDW = 44 -BPF_INS_STXW = 45 -BPF_INS_STXH = 46 -BPF_INS_STXB = 47 -BPF_INS_STXDW = 48 -BPF_INS_XADDW = 49 -BPF_INS_XADDDW = 50 -BPF_INS_JMP = 51 -BPF_INS_JEQ = 52 -BPF_INS_JGT = 53 -BPF_INS_JGE = 54 -BPF_INS_JSET = 55 -BPF_INS_JNE = 56 -BPF_INS_JSGT = 57 -BPF_INS_JSGE = 58 -BPF_INS_CALL = 59 -BPF_INS_CALLX = 60 -BPF_INS_EXIT = 61 -BPF_INS_JLT = 62 -BPF_INS_JLE = 63 -BPF_INS_JSLT = 64 -BPF_INS_JSLE = 65 -BPF_INS_RET = 66 -BPF_INS_TAX = 67 -BPF_INS_TXA = 68 -BPF_INS_ENDING = 69 +BPF_INS_BSWAP16 = 33 +BPF_INS_BSWAP32 = 34 +BPF_INS_BSWAP64 = 35 +BPF_INS_LDW = 36 +BPF_INS_LDH = 37 +BPF_INS_LDB = 38 +BPF_INS_LDDW = 39 +BPF_INS_LDXW = 40 +BPF_INS_LDXH = 41 +BPF_INS_LDXB = 42 +BPF_INS_LDXDW = 43 +BPF_INS_STW = 44 +BPF_INS_STH = 45 +BPF_INS_STB = 46 +BPF_INS_STDW = 47 +BPF_INS_STXW = 48 +BPF_INS_STXH = 49 +BPF_INS_STXB = 50 +BPF_INS_STXDW = 51 +BPF_INS_XADDW = 52 +BPF_INS_XADDDW = 53 +BPF_INS_JMP = 54 +BPF_INS_JEQ = 55 +BPF_INS_JGT = 56 +BPF_INS_JGE = 57 +BPF_INS_JSET = 58 +BPF_INS_JNE = 59 +BPF_INS_JSGT = 60 +BPF_INS_JSGE = 61 +BPF_INS_CALL = 62 +BPF_INS_CALLX = 63 +BPF_INS_EXIT = 64 +BPF_INS_JLT = 65 +BPF_INS_JLE = 66 +BPF_INS_JSLT = 67 +BPF_INS_JSLE = 68 +BPF_INS_RET = 69 +BPF_INS_TAX = 70 +BPF_INS_TXA = 71 +BPF_INS_ENDING = 72 BPF_INS_LD = BPF_INS_LDW BPF_INS_LDX = BPF_INS_LDXW BPF_INS_ST = BPF_INS_STW diff --git a/include/capstone/bpf.h b/include/capstone/bpf.h index 5a5c927d51..12c8d1d0ea 100644 --- a/include/capstone/bpf.h +++ b/include/capstone/bpf.h @@ -131,6 +131,9 @@ typedef enum bpf_insn { BPF_INS_BE16, BPF_INS_BE32, BPF_INS_BE64, + BPF_INS_BSWAP16, + BPF_INS_BSWAP32, + BPF_INS_BSWAP64, ///< Load BPF_INS_LDW, ///< eBPF only diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs index fecd353716..841b0bc52a 100644 --- a/suite/cstest/issues.cs +++ b/suite/cstest/issues.cs @@ -1,3 +1,15 @@ +!# issue 2323 eBPF bswap16 instruction +!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL +0xd7,0x53,0x3f,0x0c,0x10,0x00,0x00,0x00 == bswap16 r3 + +!# issue 2323 eBPF bswap32 instruction +!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL +0xd7,0x53,0x3f,0x0c,0x20,0x00,0x00,0x00 == bswap32 r3 + +!# issue 2323 eBPF bswap64 instruction +!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL +0xd7,0x53,0x3f,0x0c,0x40,0x00,0x00,0x00 == bswap64 r3 + !# issue 2258 vcmpunordss incorrect read/modified register !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x62,0xd1,0x56,0x08,0xc2,0xca,0x03 == vcmpunordss k1, xmm5, xmm10 ; operands[0].access: WRITE ; operands[1].access: READ ; operands[2].access: READ From 6c7b54817f792dd8d69959d3efb9fedbe740b648 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Fri, 26 Apr 2024 07:11:46 +0000 Subject: [PATCH 14/26] Add a clang-tidy checks and warnings (#2312) --- .github/workflows/clang-tidy.yml | 29 ++++++++++++++ .gitignore | 2 +- CMakeLists.txt | 14 ++++++- arch/AArch64/AArch64BaseInfo.h | 2 + arch/AArch64/AArch64Disassembler.c | 16 ++++---- arch/AArch64/AArch64GenAsmWriter.inc | 2 +- arch/AArch64/AArch64InstPrinter.c | 2 +- arch/AArch64/AArch64Mapping.c | 2 +- arch/ARM/ARMDisassembler.c | 2 +- arch/ARM/ARMMapping.c | 58 ++++++++++++++-------------- arch/HPPA/HPPADisassembler.c | 2 +- arch/M68K/M68KDisassembler.c | 4 +- cstool/cstool.c | 2 - docs/cs_v6_release_guide.md | 4 +- run-clang-tidy.sh | 30 ++++++++++++++ suite/fuzz/fuzz_disasm.c | 8 ++-- 16 files changed, 123 insertions(+), 56 deletions(-) create mode 100644 .github/workflows/clang-tidy.yml create mode 100755 run-clang-tidy.sh diff --git a/.github/workflows/clang-tidy.yml b/.github/workflows/clang-tidy.yml new file mode 100644 index 0000000000..1a814caee0 --- /dev/null +++ b/.github/workflows/clang-tidy.yml @@ -0,0 +1,29 @@ +name: Run clang-tidy +on: + push: + paths: + - '**.c' + - '**.h' + pull_request: + +jobs: + analyze: + runs-on: ubuntu-latest + + name: Install clang-tidy + steps: + - uses: actions/checkout@v3 + - name: Install clang-tidy + run: | + sudo apt install clang-tidy + + - name: Build + run: | + mkdir build && cd build + cmake -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DBUILD_SHARED_LIBS=1 .. + sudo cmake --build . --config Release + cd .. + + - name: Check for warnings + run: | + ./run-clang-tidy.sh build diff --git a/.gitignore b/.gitignore index 1fa7b654c4..bbd7315f99 100644 --- a/.gitignore +++ b/.gitignore @@ -131,7 +131,7 @@ fuzz_bindisasm fuzz_disasm fuzz_decode_platform capstone_get_setup -suite/fuzz/ +suite/fuzz/corpus suite/cstest/cmocka/ *.s diff --git a/CMakeLists.txt b/CMakeLists.txt index 2a01ae8b6b..0a42ef28b8 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -25,22 +25,32 @@ project(capstone VERSION 5.0 ) -set(UNIX_COMPILER_OPTIONS -Werror -Wshift-negative-value -Wreturn-type -Wformat -Wmissing-braces -Wunused-function -Warray-bounds -Wunused-variable -Wparentheses -Wint-in-bool-context -Wmisleading-indentation) +set(UNIX_COMPILER_OPTIONS -Werror -Wall -Warray-bounds -Wshift-negative-value -Wreturn-type -Wformat -Wmissing-braces -Wunused-function -Warray-bounds -Wunused-variable -Wparentheses -Wint-in-bool-context -Wmisleading-indentation) # maybe-unitialzied is only supported by newer versions of GCC. # Unfortunately, it is pretty unreliable and reports wrong results. # So we disable it for all compilers versions which support it. include(CheckCCompilerFlag) check_c_compiler_flag("-Wno-maybe-unitialized" SUPPORTS_MU) +check_c_compiler_flag("-Wshadow=local" SUPPORTS_SHADOWING) +check_c_compiler_flag("-Wsometimes-uninitialized" SUPPORTS_SUNINIT) if (SUPPORTS_MU) set(UNIX_COMPILER_OPTIONS ${UNIX_COMPILER_OPTIONS} -Wno-maybe-unitialized) endif() +if (SUPPORTS_SHADOWING) + set(UNIX_COMPILER_OPTIONS ${UNIX_COMPILER_OPTIONS} -Wshadow=local) +endif() + +if (SUPPORTS_SUNINIT) + set(UNIX_COMPILER_OPTIONS ${UNIX_COMPILER_OPTIONS} -Wsometimes-uninitialized) +endif() + if (MSVC) add_compile_options(/W1 /w14189) else() - add_compile_options(${UNIX_COMPILE_OPTIONS}) + add_compile_options(${UNIX_COMPILER_OPTIONS}) endif() diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h index db1c696942..b5f0a17a99 100644 --- a/arch/AArch64/AArch64BaseInfo.h +++ b/arch/AArch64/AArch64BaseInfo.h @@ -852,6 +852,7 @@ inline static const char *AArch64PACKeyIDToString(AArch64PACKey_ID KeyID) case AArch64PACKey_DB: return "db"; } + return NULL; } /// Return numeric key ID for 2-letter identifier string. @@ -867,6 +868,7 @@ AArch64StringToPACKeyID(const char *Name) if (strcmp(Name, "db") == 0) return AArch64PACKey_DB; assert(0 && "Invalid PAC key"); + return AArch64PACKey_LAST; } // end namespace AArch64 diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c index 93bf951092..1f5ff17a4b 100644 --- a/arch/AArch64/AArch64Disassembler.c +++ b/arch/AArch64/AArch64Disassembler.c @@ -360,25 +360,25 @@ static DecodeStatus getInstruction(csh handle, const uint8_t *Bytes, size_t Byte // For Scalable Matrix Extension (SME) instructions that have an // implicit operand for the accumulator (ZA) or implicit immediate zero // which isn't encoded, manually insert operand. - for (unsigned i = 0; i < Desc.NumOperands; i++) { - if (Desc.OpInfo[i].OperandType == MCOI_OPERAND_REGISTER) { - switch (Desc.OpInfo[i].RegClass) { + for (unsigned j = 0; j < Desc.NumOperands; j++) { + if (Desc.OpInfo[j].OperandType == MCOI_OPERAND_REGISTER) { + switch (Desc.OpInfo[j].RegClass) { default: break; case AArch64_MPRRegClassID: - MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, AArch64_ZA)); + MCInst_insert0(MI, j, MCOperand_CreateReg1(MI, AArch64_ZA)); break; case AArch64_MPR8RegClassID: - MCInst_insert0(MI, i, + MCInst_insert0(MI, j, MCOperand_CreateReg1(MI, AArch64_ZAB0)); break; case AArch64_ZTRRegClassID: - MCInst_insert0(MI, i, MCOperand_CreateReg1(MI, AArch64_ZT0)); + MCInst_insert0(MI, j, MCOperand_CreateReg1(MI, AArch64_ZT0)); break; } - } else if (Desc.OpInfo[i].OperandType == + } else if (Desc.OpInfo[j].OperandType == AArch64_OP_IMPLICIT_IMM_0) { - MCInst_insert0(MI, i, MCOperand_CreateImm1(MI, 0)); + MCInst_insert0(MI, j, MCOperand_CreateImm1(MI, 0)); } } diff --git a/arch/AArch64/AArch64GenAsmWriter.inc b/arch/AArch64/AArch64GenAsmWriter.inc index 58e1e0d3f7..7e8a0e63f5 100644 --- a/arch/AArch64/AArch64GenAsmWriter.inc +++ b/arch/AArch64/AArch64GenAsmWriter.inc @@ -33535,7 +33535,7 @@ static bool AArch64InstPrinterValidateMCOperand(const MCOperand *MCOp, switch (PredicateIndex) { default: assert(0 && "Unknown MCOperandPredicate kind"); - break; + return false; case 1: { if (!MCOperand_isImm(MCOp)) diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index 043d351fbb..f5bcf70552 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -1358,7 +1358,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O) unsigned Reg = MCOperand_getReg(Op); printRegName(O, Reg); } else if (MCOperand_isImm(Op)) { - MCOperand *Op = MCInst_getOperand(MI, (OpNo)); + Op = MCInst_getOperand(MI, (OpNo)); SStream_concat(O, "%s", markup("")); diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index bb3f294f77..7b2fa56094 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -1483,7 +1483,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, case AArch64_OP_GROUP_ZPRasFPR_32: case AArch64_OP_GROUP_ZPRasFPR_64: case AArch64_OP_GROUP_ZPRasFPR_8: { - unsigned Base; + unsigned Base = AArch64_NoRegister; unsigned Width = temp_arg_0; switch (Width) { case 8: diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index 43d81e87c3..da91a758e1 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -2082,7 +2082,7 @@ static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst *Inst, unsigned Insn, unsigned amt = fieldFromInstruction_4(Insn, 7, 5); if (Opc == ARM_AM_ror && amt == 0) Opc = ARM_AM_rrx; - unsigned imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); + imm = ARM_AM_getAM2Opc(Op, amt, Opc, idx_mode); MCOperand_CreateImm0(Inst, (imm)); } else { diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 9ec29c2d6d..19cbcd11f6 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -1354,11 +1354,11 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, MCInst_getOpVal(MI, OpNum) + 1); break; case ARM_OP_GROUP_RotImmOperand: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); - if (Imm == 0) + unsigned RotImm = MCInst_getOpVal(MI, OpNum); + if (RotImm == 0) return; ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ROR; - ARM_get_detail_op(MI, -1)->shift.value = Imm * 8; + ARM_get_detail_op(MI, -1)->shift.value = RotImm * 8; break; } case ARM_OP_GROUP_FBits16: @@ -1390,16 +1390,16 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, break; } case ARM_OP_GROUP_PostIdxImm8Operand: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); - bool sub = !(Imm & 256); - ARM_set_detail_op_mem_offset(MI, OpNum, (Imm & 0xff), sub); + unsigned Imm8 = MCInst_getOpVal(MI, OpNum); + bool sub = !(Imm8 & 256); + ARM_set_detail_op_mem_offset(MI, OpNum, (Imm8 & 0xff), sub); ARM_get_detail(MI)->post_index = true; break; } case ARM_OP_GROUP_PostIdxImm8s4Operand: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); - bool sub = !(Imm & 256); - ARM_set_detail_op_mem_offset(MI, OpNum, (Imm & 0xff) << 2, sub); + unsigned Imm8s = MCInst_getOpVal(MI, OpNum); + bool sub = !(Imm8s & 256); + ARM_set_detail_op_mem_offset(MI, OpNum, (Imm8s & 0xff) << 2, sub); ARM_get_detail(MI)->post_index = true; break; } @@ -1569,26 +1569,26 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, ARM_set_mem_access(MI, true); ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, MCInst_getOpVal(MI, OpNum)); - int64_t Imm = MCInst_getOpVal(MI, OpNum + 1); - if (Imm) + int64_t Imm0_1024s4 = MCInst_getOpVal(MI, OpNum + 1); + if (Imm0_1024s4) ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, - Imm * 4); + Imm0_1024s4 * 4); ARM_set_mem_access(MI, false); break; case ARM_OP_GROUP_PKHLSLShiftImm: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); - if (Imm == 0) + unsigned ShiftImm = MCInst_getOpVal(MI, OpNum); + if (ShiftImm == 0) return; ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_LSL; - ARM_get_detail_op(MI, -1)->shift.value = Imm; + ARM_get_detail_op(MI, -1)->shift.value = ShiftImm; break; } case ARM_OP_GROUP_PKHASRShiftImm: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); - if (Imm == 0) - Imm = 32; + unsigned RShiftImm = MCInst_getOpVal(MI, OpNum); + if (RShiftImm == 0) + RShiftImm = 32; ARM_get_detail_op(MI, -1)->shift.type = ARM_SFT_ASR; - ARM_get_detail_op(MI, -1)->shift.value = Imm; + ARM_get_detail_op(MI, -1)->shift.value = RShiftImm; break; } case ARM_OP_GROUP_ThumbS4ImmOperand: @@ -1596,9 +1596,9 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, MCInst_getOpVal(MI, OpNum) * 4); break; case ARM_OP_GROUP_ThumbSRImm: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); + unsigned SRImm = MCInst_getOpVal(MI, OpNum); ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, - Imm == 0 ? 32 : Imm); + SRImm == 0 ? 32 : SRImm); break; } case ARM_OP_GROUP_BitfieldInvMaskImmOperand: { @@ -1610,8 +1610,8 @@ static void add_cs_detail_general(MCInst *MI, arm_op_group op_group, break; } case ARM_OP_GROUP_CPSIMod: { - unsigned Imm = MCInst_getOpVal(MI, OpNum); - ARM_get_detail(MI)->cps_mode = Imm; + unsigned Mode = MCInst_getOpVal(MI, OpNum); + ARM_get_detail(MI)->cps_mode = Mode; break; } case ARM_OP_GROUP_CPSIFlag: { @@ -1730,10 +1730,10 @@ static void add_cs_detail_template_1(MCInst *MI, arm_op_group op_group, ARM_set_mem_access(MI, true); ARM_set_detail_op_mem(MI, OpNum, false, 0, 0, MCInst_getOpVal(MI, OpNum)); - int32_t Imm = MCInst_getOpVal(MI, OpNum + 1); - if (Imm == INT32_MIN) - Imm = 0; - ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm); + int32_t Imm8 = MCInst_getOpVal(MI, OpNum + 1); + if (Imm8 == INT32_MIN) + Imm8 = 0; + ARM_set_detail_op_mem(MI, OpNum + 1, false, 0, 0, Imm8); if (AlwaysPrintImm0) map_add_implicit_write(MI, MCInst_getOpVal(MI, OpNum)); @@ -1864,8 +1864,8 @@ static void add_cs_detail_template_2(MCInst *MI, arm_op_group op_group, case ARM_OP_GROUP_ComplexRotationOp_180_90: { unsigned Angle = temp_arg_0; unsigned Remainder = temp_arg_1; - unsigned Imm = (MCInst_getOpVal(MI, OpNum) * Angle) + Remainder; - ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Imm); + unsigned Rotation = (MCInst_getOpVal(MI, OpNum) * Angle) + Remainder; + ARM_set_detail_op_imm(MI, OpNum, ARM_OP_IMM, Rotation); break; } } diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c index a73c6eafe0..5da27156e0 100644 --- a/arch/HPPA/HPPADisassembler.c +++ b/arch/HPPA/HPPADisassembler.c @@ -2776,7 +2776,7 @@ static void fill_copr_mods(uint32_t insn, uint32_t uid, uint32_t class, push_str_modifier(hppa_ext, "n"); } } else { - uint32_t uid = get_insn_field(insn, 23, 25); + uid = get_insn_field(insn, 23, 25); uint32_t sop = (get_insn_field(insn, 6, 22) << 5) | get_insn_field(insn, 27, 31); push_int_modifier(hppa_ext, uid); diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index a1df81c336..b502e5ae9f 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -1944,9 +1944,7 @@ static void d68020_cpgen(m68k_info *info) // special handling for fmovecr if (BITFIELD(info->ir, 5, 0) == 0 && BITFIELD(next, 15, 10) == 0x17) { - cs_m68k_op* op0; - cs_m68k_op* op1; - cs_m68k* ext = build_init_op(info, M68K_INS_FMOVECR, 2, 0); + ext = build_init_op(info, M68K_INS_FMOVECR, 2, 0); op0 = &ext->operands[0]; op1 = &ext->operands[1]; diff --git a/cstool/cstool.c b/cstool/cstool.c index 88bc94a178..795850840f 100644 --- a/cstool/cstool.c +++ b/cstool/cstool.c @@ -645,8 +645,6 @@ int main(int argc, char **argv) count = cs_disasm(handle, assembly, size, address, 0, &insn); if (count > 0) { - size_t i; - for (i = 0; i < count; i++) { int j; diff --git a/docs/cs_v6_release_guide.md b/docs/cs_v6_release_guide.md index aef1184e4e..4ac1b2bc3f 100644 --- a/docs/cs_v6_release_guide.md +++ b/docs/cs_v6_release_guide.md @@ -157,9 +157,9 @@ Write it into `rename_arm64.sh` and run it on files with `sh rename_arm64.sh " + exit 1 +fi + +BUILD_PATH="$1" + +clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks=clang-analyzer-*,-clang-analyzer-cplusplus* | tee ct-warnings.txt + +tmp=$(mktemp) +grep ": warning" ct-warnings.txt | grep -oE "^[/a-zA-Z0-9]*\.[ch]" | sort | uniq > $tmp +top_level=$(git rev-parse --show-toplevel) + +echo "\n\n###### REPORT\n\n" + +for modified in $(git diff --name-only origin/next); do + full_path="$top_level/$modified" + if grep -q "$full_path" $tmp; then + echo "$full_path as warnings. Please fix them." + needs_fixes=1 + fi +done + +if [ -z $needs_fixes ]; then + echo "All good" + exit 0 +fi +exit 1 diff --git a/suite/fuzz/fuzz_disasm.c b/suite/fuzz/fuzz_disasm.c index 0dd7ef72d4..b402e7eecd 100644 --- a/suite/fuzz/fuzz_disasm.c +++ b/suite/fuzz/fuzz_disasm.c @@ -60,12 +60,12 @@ int LLVMFuzzerTestOneInput(const uint8_t *Data, size_t Size) { unsigned int n; for (j = 0; j < count; j++) { - cs_insn *i = &(all_insn[j]); + cs_insn *insn = &(all_insn[j]); fprintf(outfile, "0x%"PRIx64":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n", - i->address, i->mnemonic, i->op_str, - i->id, cs_insn_name(handle, i->id)); + insn->address, insn->mnemonic, insn->op_str, + insn->id, cs_insn_name(handle, insn->id)); - detail = i->detail; + detail = insn->detail; if (detail->regs_read_count > 0) { fprintf(outfile, "\tImplicit registers read: "); From 514b8fca9c5cb66ee8d91b3373203499a1e41e2f Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Fri, 26 Apr 2024 07:12:42 +0000 Subject: [PATCH 15/26] Fix #2128 by adding missing mapping values. (#2335) --- arch/X86/X86MappingInsn.inc | 2 +- arch/X86/X86MappingInsnOp.inc | 4 ++-- suite/cstest/issues.cs | 4 ++++ 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/X86/X86MappingInsn.inc b/arch/X86/X86MappingInsn.inc index 906dc07a70..0703eb8265 100644 --- a/arch/X86/X86MappingInsn.inc +++ b/arch/X86/X86MappingInsn.inc @@ -18808,7 +18808,7 @@ { X86_TEST64mr, X86_INS_TEST, 1, #ifndef CAPSTONE_DIET - { 0 }, { 0 }, { 0 }, 0, 0 + { 0 }, { X86_REG_EFLAGS, 0 }, { 0 }, 0, 0 #endif }, diff --git a/arch/X86/X86MappingInsnOp.inc b/arch/X86/X86MappingInsnOp.inc index 16b2a4525b..cb5cd434c7 100644 --- a/arch/X86/X86MappingInsnOp.inc +++ b/arch/X86/X86MappingInsnOp.inc @@ -13434,8 +13434,8 @@ }, { /* X86_TEST64mr, X86_INS_TEST: test */ - 0, - { 0 } + X86_EFLAGS_RESET_OF | X86_EFLAGS_MODIFY_SF | X86_EFLAGS_MODIFY_ZF | X86_EFLAGS_UNDEFINED_AF | X86_EFLAGS_MODIFY_PF | X86_EFLAGS_RESET_CF, + { CS_AC_READ, CS_AC_READ, 0 } }, { /* X86_TEST64ri32, X86_INS_TEST: test */ diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs index 841b0bc52a..567e607835 100644 --- a/suite/cstest/issues.cs +++ b/suite/cstest/issues.cs @@ -1066,3 +1066,7 @@ !# issue 2233 ARM write to PC is branch !# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL 0x87,0x46 == mov pc, r0 ; Groups: IsThumb jump + +!# issue 2128 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0x4c,0x85,0x7d,0x30 == test qword ptr [rbp + 0x30], r15 ; operands[1].type: REG = r15 ; operands[1].access: READ ; Registers read: rbp r15 ; Registers modified: rflags From eb4fc2d7612db10379adf7aeb287a7923dcc0fc7 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Fri, 26 Apr 2024 07:16:00 +0000 Subject: [PATCH 16/26] Replace manually compile tree-sitter-cpp with their Python bindings. (#2337) --- suite/auto-sync/README.md | 6 ------ suite/auto-sync/pyproject.toml | 3 ++- .../autosync/cpptranslator/Configurator.py | 21 +++---------------- suite/auto-sync/vendor/tree-sitter-cpp | 1 - 4 files changed, 5 insertions(+), 26 deletions(-) delete mode 160000 suite/auto-sync/vendor/tree-sitter-cpp diff --git a/suite/auto-sync/README.md b/suite/auto-sync/README.md index 93d82d109e..3f98037a34 100644 --- a/suite/auto-sync/README.md +++ b/suite/auto-sync/README.md @@ -20,13 +20,7 @@ sudo apt install python3-venv # Setup virtual environment in Capstone root dir python3 -m venv ./.venv source ./.venv/bin/activate -``` - -Clone C++ grammar - -``` cd suite/auto-sync/ -git submodule update --init --recursive ./vendor/ pip install -e . ``` diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml index ffa1f5aff5..bc77298317 100644 --- a/suite/auto-sync/pyproject.toml +++ b/suite/auto-sync/pyproject.toml @@ -7,7 +7,8 @@ name = "autosync" version = "0.1.0" dependencies = [ "termcolor >= 2.3.0", - "tree_sitter < 0.22.0", + "tree_sitter >= 0.21.3", + "tree-sitter-cpp >=0.22.0", "black >= 24.3.0", "usort >= 1.0.8", "setuptools >= 69.2.0", diff --git a/suite/auto-sync/src/autosync/cpptranslator/Configurator.py b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py index ba19fa0de1..72b729e389 100644 --- a/suite/auto-sync/src/autosync/cpptranslator/Configurator.py +++ b/suite/auto-sync/src/autosync/cpptranslator/Configurator.py @@ -5,9 +5,10 @@ import logging as log from pathlib import Path +import tree_sitter_cpp as ts_cpp from tree_sitter import Language, Parser -from autosync.Helper import fail_exit, get_path +from autosync.Helper import fail_exit class Configurator: @@ -25,9 +26,7 @@ class Configurator: def __init__(self, arch: str, config_path: Path) -> None: self.arch = arch self.config_path = config_path - self.ts_shared_object = get_path("{VENDOR_DIR}").joinpath("ts_cpp.so") self.load_config() - self.ts_compile_cpp() self.ts_set_cpp_language() self.init_parser() @@ -69,22 +68,8 @@ def load_config(self) -> None: ) self.config = conf - def ts_compile_cpp(self) -> None: - log.info("Compile Cpp language") - ts_grammar_path = get_path("{VENDOR_DIR}").joinpath("tree-sitter-cpp") - if not Path.exists(ts_grammar_path): - fail_exit(f"Could not load the tree-sitter grammar at '{ts_grammar_path}'") - # build_library wll be deprecated in 0.22.0. But CPP tree-sitter doesn't have Python bindings. - # So we stick with it. - Language.build_library(str(self.ts_shared_object), [str(ts_grammar_path)]) - def ts_set_cpp_language(self) -> None: - log.info(f"Load language '{self.ts_shared_object}'") - if not Path.exists(self.ts_shared_object): - fail_exit( - f"Could not load the tree-sitter language shared object at '{self.ts_shared_object}'" - ) - self.ts_cpp_lang = Language(str(self.ts_shared_object), "cpp") + self.ts_cpp_lang = Language(ts_cpp.language(), "cpp") def init_parser(self) -> None: log.debug("Init parser") diff --git a/suite/auto-sync/vendor/tree-sitter-cpp b/suite/auto-sync/vendor/tree-sitter-cpp deleted file mode 160000 index e0c1678a78..0000000000 --- a/suite/auto-sync/vendor/tree-sitter-cpp +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e0c1678a78731e78655b7d953efb4daecf58be46 From b2d5b43ed21dfece72b3e942785efc1af54b7eb2 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Tue, 30 Apr 2024 02:35:40 +0000 Subject: [PATCH 17/26] Fix #2079 via the post-printer. (#2330) --- arch/X86/X86Mapping.c | 23 +++++++++++++++++++++++ arch/X86/X86Mapping.h | 2 ++ arch/X86/X86Module.c | 2 +- suite/cstest/issues.cs | 4 ++++ 4 files changed, 30 insertions(+), 1 deletion(-) diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c index d23340d771..a5b8729082 100644 --- a/arch/X86/X86Mapping.c +++ b/arch/X86/X86Mapping.c @@ -2244,4 +2244,27 @@ unsigned short X86_register_map(unsigned short id) return 0; } +/// The post-printer function. Used to fixup flaws in the disassembly information +/// of certain instructions. +void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci) { + if (!insn || !insn->detail) { + return; + } + switch (insn->id) { + default: + break; + case X86_INS_RCL: + // Addmissing 1 immediate + if (insn->detail->x86.op_count > 1) { + return; + } + insn->detail->x86.operands[1].imm = 1; + insn->detail->x86.operands[1].type = X86_OP_IMM; + insn->detail->x86.operands[1].access = CS_AC_READ; + insn->detail->x86.op_count++; + break; + } +} + + #endif diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h index 89bbfcd8c4..c6dc40377f 100644 --- a/arch/X86/X86Mapping.h +++ b/arch/X86/X86Mapping.h @@ -91,4 +91,6 @@ unsigned short X86_register_map(unsigned short id); unsigned int find_insn(unsigned int id); +void X86_postprinter(csh handle, cs_insn *insn, char *mnem, MCInst *mci); + #endif diff --git a/arch/X86/X86Module.c b/arch/X86/X86Module.c index 2ec5625de4..ed080a797c 100644 --- a/arch/X86/X86Module.c +++ b/arch/X86/X86Module.c @@ -26,7 +26,7 @@ cs_err X86_global_init(cs_struct *ud) ud->insn_id = X86_get_insn_id; ud->insn_name = X86_insn_name; ud->group_name = X86_group_name; - ud->post_printer = NULL; + ud->post_printer = X86_postprinter; #ifndef CAPSTONE_DIET ud->reg_access = X86_reg_access; #endif diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs index 567e607835..614470c958 100644 --- a/suite/cstest/issues.cs +++ b/suite/cstest/issues.cs @@ -1070,3 +1070,7 @@ !# issue 2128 !# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL 0x0: 0x4c,0x85,0x7d,0x30 == test qword ptr [rbp + 0x30], r15 ; operands[1].type: REG = r15 ; operands[1].access: READ ; Registers read: rbp r15 ; Registers modified: rflags + +!# issue 2079 +!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL +0x0: 0xd1,0x10 == rcl dword ptr [eax] ; operands[1].type: IMM = 0x1 From b91c7274812986f168b7e7b83617f0b6ba2aa981 Mon Sep 17 00:00:00 2001 From: RainRat Date: Mon, 29 Apr 2024 19:37:53 -0700 Subject: [PATCH 18/26] fix typos (#2344) --- COMPILE.TXT | 2 +- COMPILE_MSVC.TXT | 2 +- ChangeLog | 14 +++++----- MCInst.c | 4 +-- MCInst.h | 2 +- arch/AArch64/AArch64BaseInfo.h | 2 +- arch/AArch64/AArch64InstPrinter.c | 2 +- arch/AArch64/AArch64Linkage.h | 2 +- arch/AArch64/AArch64Mapping.c | 4 +-- arch/AArch64/AArch64Mapping.h | 2 +- arch/ARM/ARMAddressingModes.h | 2 +- arch/ARM/ARMBaseInfo.c | 2 +- arch/ARM/ARMDisassembler.c | 4 +-- arch/ARM/ARMInstPrinter.c | 2 +- arch/ARM/ARMInstPrinter.h | 2 +- arch/ARM/ARMLinkage.h | 2 +- arch/ARM/ARMMapping.c | 6 ++--- arch/ARM/ARMMapping.h | 2 +- arch/Alpha/AlphaLinkage.h | 2 +- arch/HPPA/HPPADisassembler.c | 8 +++--- arch/M680X/M680XDisassembler.c | 12 ++++----- arch/M68K/M68KDisassembler.c | 2 +- arch/Mips/MipsDisassembler.c | 4 +-- arch/Mips/MipsMapping.h | 2 +- arch/PowerPC/PPCInstPrinter.c | 4 +-- arch/PowerPC/PPCLinkage.h | 2 +- arch/PowerPC/PPCMapping.c | 2 +- arch/PowerPC/PPCMapping.h | 2 +- arch/RISCV/RISCVGenAsmWriter.inc | 2 +- arch/SH/SHDisassembler.c | 2 +- arch/Sparc/SparcMapping.h | 2 +- arch/SystemZ/SystemZMapping.h | 2 +- arch/TMS320C64x/TMS320C64xMapping.h | 2 +- arch/TriCore/TriCoreCallingConv.td | 2 +- arch/TriCore/TriCoreLinkage.h | 2 +- arch/X86/X86ATTInstPrinter.c | 2 +- arch/X86/X86DisassemblerDecoder.c | 4 +-- arch/X86/X86IntelInstPrinter.c | 2 +- arch/X86/X86Mapping.c | 2 +- arch/X86/X86Mapping.h | 2 +- arch/XCore/XCoreMapping.h | 2 +- bindings/java/capstone/Capstone.java | 4 +-- bindings/ocaml/capstone.ml | 2 +- bindings/python/capstone/__init__.py | 2 +- bindings/python/test_x86.py | 2 +- bindings/vb6/CX86Inst.cls | 6 ++--- bindings/vb6/mMisc.bas | 4 +-- bindings/vb6/mx86.bas | 6 ++--- config.mk | 2 +- cs.c | 6 ++--- include/capstone/cs_operand.h | 4 +-- include/capstone/m680x.h | 2 +- include/capstone/m68k.h | 2 +- include/capstone/mos65xx.h | 2 +- include/capstone/ppc.h | 8 +++--- .../ARM/01_LDM_written_reglists.patch | 2 +- .../ARM/02_VSCCLRM_written_reglists.patch | 2 +- suite/autogen_x86imm.py | 2 +- suite/cstest/README.md | 2 +- suite/disasm_mc.sh | 2 +- suite/fuzz/driverbin.c | 2 +- suite/fuzz/drivermc.c | 2 +- suite/fuzz/onefile.c | 2 +- suite/synctools/README | 2 +- suite/synctools/asmwriter.py | 2 +- .../synctools/tablegen/X86/X86InstrAVX512.td | 12 ++++----- .../tablegen/X86/X86InstrCompiler.td | 4 +-- suite/synctools/tablegen/X86/X86InstrFMA.td | 2 +- .../synctools/tablegen/X86/X86InstrFPStack.td | 2 +- suite/synctools/tablegen/X86/X86InstrSSE.td | 4 +-- .../synctools/tablegen/X86/X86InstrSystem.td | 2 +- suite/synctools/tablegen/X86/X86InstrTSX.td | 2 +- .../synctools/tablegen/X86/X86RegisterInfo.td | 2 +- suite/synctools/tablegen/X86/X86Schedule.td | 4 +-- .../synctools/tablegen/X86/X86ScheduleAtom.td | 4 +-- .../tablegen/X86/back/X86InstrAVX512.td | 12 ++++----- .../tablegen/X86/back/X86InstrCompiler.td | 4 +-- .../tablegen/X86/back/X86InstrFMA.td | 2 +- .../tablegen/X86/back/X86InstrFPStack.td | 2 +- .../tablegen/X86/back/X86InstrSSE.td | 4 +-- .../tablegen/X86/back/X86InstrSystem.td | 2 +- .../tablegen/X86/back/X86InstrTSX.td | 2 +- .../tablegen/X86/back/X86RegisterInfo.td | 2 +- .../tablegen/X86/back/X86Schedule.td | 4 +-- .../tablegen/X86/back/X86ScheduleAtom.td | 4 +-- .../include/llvm/CodeGen/AccelTable.h | 2 +- .../include/llvm/CodeGen/AntiDepBreaker.h | 2 +- .../include/llvm/CodeGen/AsmPrinter.h | 4 +-- .../include/llvm/CodeGen/BasicTTIImpl.h | 4 +-- .../include/llvm/CodeGen/CodeGenPassBuilder.h | 10 +++---- .../include/llvm/CodeGen/DFAPacketizer.h | 4 +-- .../include/llvm/CodeGen/DebugHandlerBase.h | 2 +- .../CodeGen/GlobalISel/InstructionSelector.h | 2 +- .../CodeGen/GlobalISel/LegacyLegalizerInfo.h | 2 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 2 +- .../CodeGen/GlobalISel/MachineIRBuilder.h | 2 +- .../llvm/CodeGen/GlobalISel/RegBankSelect.h | 2 +- .../CodeGen/GlobalISel/RegisterBankInfo.h | 6 ++--- .../include/llvm/CodeGen/ISDOpcodes.h | 2 +- .../include/llvm/CodeGen/LexicalScopes.h | 2 +- .../include/llvm/CodeGen/LiveInterval.h | 6 ++--- .../include/llvm/CodeGen/LiveIntervals.h | 2 +- .../include/llvm/CodeGen/LivePhysRegs.h | 2 +- .../include/llvm/CodeGen/LiveRangeEdit.h | 2 +- .../include/llvm/CodeGen/LiveRegUnits.h | 2 +- .../include/llvm/CodeGen/LoopTraversal.h | 6 ++--- .../include/llvm/CodeGen/MIRFormatter.h | 2 +- .../include/llvm/CodeGen/MIRPrinter.h | 2 +- .../include/llvm/CodeGen/MIRSampleProfile.h | 2 +- .../include/llvm/CodeGen/MachineBasicBlock.h | 4 +-- .../CodeGen/MachineBranchProbabilityInfo.h | 2 +- .../include/llvm/CodeGen/MachineFrameInfo.h | 2 +- .../include/llvm/CodeGen/MachineFunction.h | 4 +-- .../include/llvm/CodeGen/MachineInstr.h | 4 +-- .../include/llvm/CodeGen/MachineModuleInfo.h | 4 +-- .../include/llvm/CodeGen/MachineOperand.h | 6 ++--- .../include/llvm/CodeGen/MachinePassManager.h | 2 +- .../include/llvm/CodeGen/MachinePipeliner.h | 4 +-- .../include/llvm/CodeGen/MachineScheduler.h | 2 +- .../include/llvm/CodeGen/ModuloSchedule.h | 2 +- .../include/llvm/CodeGen/PBQP/Graph.h | 2 +- .../llvm/CodeGen/ReachingDefAnalysis.h | 6 ++--- .../include/llvm/CodeGen/RegisterPressure.h | 2 +- .../include/llvm/CodeGen/ReplaceWithVeclib.h | 2 +- .../include/llvm/CodeGen/SelectionDAG.h | 2 +- .../include/llvm/CodeGen/SelectionDAGNodes.h | 2 +- .../tablegen/include/llvm/CodeGen/StackMaps.h | 2 +- .../include/llvm/CodeGen/TailDuplicator.h | 2 +- .../include/llvm/CodeGen/TargetInstrInfo.h | 2 +- .../include/llvm/CodeGen/TargetLowering.h | 16 ++++++------ .../include/llvm/CodeGen/TargetPassConfig.h | 10 +++---- .../include/llvm/CodeGen/TargetRegisterInfo.h | 6 ++--- .../llvm/CodeGen/VLIWMachineScheduler.h | 2 +- .../include/llvm/CodeGen/VirtRegMap.h | 2 +- .../include/llvm/CodeGen/WinEHFuncInfo.h | 2 +- .../llvm/Frontend/Directive/DirectiveBase.td | 6 ++--- .../llvm/Frontend/OpenMP/OMPConstants.h | 4 +-- .../include/llvm/Frontend/OpenMP/OMPContext.h | 4 +-- .../llvm/Frontend/OpenMP/OMPIRBuilder.h | 26 +++++++++---------- .../tablegen/include/llvm/IR/Attributes.h | 4 +-- .../tablegen/include/llvm/IR/CallingConv.h | 4 +-- .../tablegen/include/llvm/IR/Constants.h | 2 +- .../tablegen/include/llvm/IR/DIBuilder.h | 2 +- .../include/llvm/IR/DebugInfoMetadata.h | 2 +- .../include/llvm/IR/DiagnosticHandler.h | 4 +-- .../tablegen/include/llvm/IR/Function.h | 2 +- .../tablegen/include/llvm/IR/GCStrategy.h | 2 +- .../tablegen/include/llvm/IR/GlobalValue.h | 2 +- .../tablegen/include/llvm/IR/GlobalVariable.h | 2 +- .../tablegen/include/llvm/IR/IRBuilder.h | 2 +- .../tablegen/include/llvm/IR/InstVisitor.h | 2 +- .../tablegen/include/llvm/IR/InstrTypes.h | 4 +-- .../tablegen/include/llvm/IR/Instruction.h | 2 +- .../tablegen/include/llvm/IR/Intrinsics.h | 2 +- .../include/llvm/IR/IntrinsicsAMDGPU.td | 2 +- .../tablegen/include/llvm/IR/IntrinsicsARM.td | 2 +- .../tablegen/include/llvm/IR/LLVMContext.h | 2 +- .../include/llvm/IR/LegacyPassManager.h | 2 +- .../include/llvm/IR/LegacyPassManagers.h | 6 ++--- .../include/llvm/IR/LegacyPassNameParser.h | 2 +- .../tablegen/include/llvm/IR/Metadata.h | 2 +- .../tablegen/include/llvm/IR/PassManager.h | 6 ++--- .../include/llvm/IR/PassManagerInternal.h | 2 +- .../tablegen/include/llvm/IR/ProfileSummary.h | 2 +- .../include/llvm/IR/ReplaceConstant.h | 2 +- .../tablegen/include/llvm/IR/Statepoint.h | 4 +-- .../tablegen/include/llvm/IR/TrackingMDRef.h | 2 +- .../tablegen/include/llvm/IR/Value.h | 6 ++--- .../tablegen/include/llvm/IR/ValueMap.h | 2 +- .../ProfileData/Coverage/CoverageMapping.h | 4 +-- .../include/llvm/ProfileData/InstrProf.h | 10 +++---- .../include/llvm/ProfileData/SampleProf.h | 6 ++--- .../llvm/ProfileData/SampleProfReader.h | 6 ++--- .../llvm/ProfileData/SampleProfWriter.h | 2 +- .../include/llvm/Target/GlobalISel/Combine.td | 2 +- .../tablegen/include/llvm/Target/Target.td | 4 +-- .../llvm/Target/TargetLoweringObjectFile.h | 2 +- .../include/llvm/Target/TargetMachine.h | 6 ++--- .../include/llvm/Target/TargetOptions.h | 2 +- .../include/llvm/Target/TargetSchedule.td | 4 +-- suite/test_mc.sh | 2 +- utils.c | 2 +- windowsce/COMPILE.md | 2 +- 183 files changed, 310 insertions(+), 310 deletions(-) diff --git a/COMPILE.TXT b/COMPILE.TXT index 5d914ffc69..8674c8dfd3 100644 --- a/COMPILE.TXT +++ b/COMPILE.TXT @@ -17,7 +17,7 @@ Capstone requires no prerequisite packages, so it is easy to compile & install. (0) Tailor Capstone to your need. - Out of all archtitectures supported by Capstone, if you just need several + Out of all architectures supported by Capstone, if you just need several selected archs, choose the ones you want to compile in by editing "config.mk" before going to next steps. diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT index 6b0d4e14bc..77d16c558b 100644 --- a/COMPILE_MSVC.TXT +++ b/COMPILE_MSVC.TXT @@ -19,7 +19,7 @@ or newer versions are required. (0) Tailor Capstone to your need. - Out of 9 archtitectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, + Out of 9 architectures supported by Capstone (Arm, Arm64, M68K, Mips, PPC, Sparc, SystemZ, X86 & XCore), if you just need several selected archs, choose the ones you want to compile in by opening Visual Studio solution "msvc\capstone.sln", then directly editing the projects "capstone_static" & "capstone_dll" for static diff --git a/ChangeLog b/ChangeLog index b06d27e0c5..fb4c214bdc 100644 --- a/ChangeLog +++ b/ChangeLog @@ -424,7 +424,7 @@ Version 3.0.5: July 18th, 2018 [ Core ] - Fix the include path for Android builds when building cstool. -- Add posibility to disable universal build for Mac OS. +- Add possibility to disable universal build for Mac OS. - cstool: Separate instruction bytes by spaces. - Fix code path of pkg-config in Cmake. - Update XCode project for XCode 9.1. @@ -444,7 +444,7 @@ Version 3.0.5: July 18th, 2018 [ ARM ] -- Fix an integer overlow bug. +- Fix an integer overflow bug. [ ARM64 ] @@ -464,12 +464,12 @@ Version 3.0.5: July 18th, 2018 [ Sparc ] -- Fix an integer overlow bug. +- Fix an integer overflow bug. [ SystemZ ] -- Fix an integer overlow bug. +- Fix an integer overflow bug. [ Python binding ] @@ -961,7 +961,7 @@ Version 2.1: March 5th, 2014 ---------------------------------- Version 2.0: January 22nd, 2014 -Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. +Release 2.0 deprecates version 1.0 and brings a lot of crucial changes. [ API changes ] @@ -973,7 +973,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. cs_option(). - New option CS_OPT_MEM allows to specify user-defined functions for dynamically memory management used internally by Capstone. This is useful to embed Capstone - into special environments such as kernel or firware. + into special environments such as kernel or firmware. - New API cs_support() can be used to check if this lib supports a particular architecture (this is necessary since we now allow to choose which architectures to compile in). @@ -1009,7 +1009,7 @@ Release 2.0 deprecates verison 1.0 and brings a lot of crucial changes. - Cython support has been added, which can further speed up over the default pure Python binding (up to 30% in some cases) - Function cs_disasm_quick() & Cs.disasm() now use generator (rather than a list) - to return succesfully disassembled instructions. This improves the performance + to return successfully disassembled instructions. This improves the performance and reduces memory usage. diff --git a/MCInst.c b/MCInst.c index aed26086ae..933327a468 100644 --- a/MCInst.c +++ b/MCInst.c @@ -18,7 +18,7 @@ void MCInst_Init(MCInst *inst) { - // unnecessary to initialize in loop . its expensive and inst->size shuold be honored + // unnecessary to initialize in loop . its expensive and inst->size should be honored inst->Operands[0].Kind = kInvalid; inst->Operands[0].ImmVal = 0; @@ -89,7 +89,7 @@ unsigned MCInst_getNumOperands(const MCInst *inst) return inst->size; } -// This addOperand2 function doesnt free Op +// This addOperand2 function doesn't free Op void MCInst_addOperand2(MCInst *inst, MCOperand *Op) { assert(inst->size < MAX_MC_OPS); diff --git a/MCInst.h b/MCInst.h index 25f8f5c469..08a4f5891d 100644 --- a/MCInst.h +++ b/MCInst.h @@ -153,7 +153,7 @@ MCOperand *MCInst_getOperand(MCInst *inst, unsigned i); unsigned MCInst_getNumOperands(const MCInst *inst); -// This addOperand2 function doesnt free Op +// This addOperand2 function doesn't free Op void MCInst_addOperand2(MCInst *inst, MCOperand *Op); bool MCInst_isPredicable(const MCInstrDesc *MIDesc); diff --git a/arch/AArch64/AArch64BaseInfo.h b/arch/AArch64/AArch64BaseInfo.h index b5f0a17a99..b67054eb94 100644 --- a/arch/AArch64/AArch64BaseInfo.h +++ b/arch/AArch64/AArch64BaseInfo.h @@ -815,7 +815,7 @@ typedef enum TOF { /// an LDG instruction to obtain the tag value. AArch64II_MO_TAGGED = 0x400, - /// MO_DLLIMPORTAUX - Symbol refers to "auxilliary" import stub. On + /// MO_DLLIMPORTAUX - Symbol refers to "auxiliary" import stub. On /// Arm64EC, there are two kinds of import stubs used for DLL import of /// functions: MO_DLLIMPORT refers to natively callable Arm64 code, and /// MO_DLLIMPORTAUX refers to the original address which can be compared diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c index f5bcf70552..a1bf0e2a11 100644 --- a/arch/AArch64/AArch64InstPrinter.c +++ b/arch/AArch64/AArch64InstPrinter.c @@ -318,7 +318,7 @@ void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O) (ImmR == 0 || ImmS < ImmR) && (AArch64_getFeatureBits(MI->csh->mode, AArch64_FeatureAll) || AArch64_getFeatureBits(MI->csh->mode, AArch64_HasV8_2aOps))) { - // BFC takes precedence over its entire range, sligtly differently + // BFC takes precedence over its entire range, slightly differently // to BFI. int BitWidth = Opcode == AArch64_BFMXri ? 64 : 32; int LSB = (BitWidth - ImmR) % BitWidth; diff --git a/arch/AArch64/AArch64Linkage.h b/arch/AArch64/AArch64Linkage.h index aa1a0ba2d7..7245a0ce73 100644 --- a/arch/AArch64/AArch64Linkage.h +++ b/arch/AArch64/AArch64Linkage.h @@ -4,7 +4,7 @@ #ifndef CS_AARCH64_LINKAGE_H #define CS_AARCH64_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 7b2fa56094..2a208e3bda 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -247,7 +247,7 @@ void AArch64_init_cs_detail(MCInst *MI) /// So the only generic way to determine, if the memory access is in /// post-indexed addressing mode, is by search for "], #" in /// @p OS. -/// Searching the asm string to determine such a property is enourmously ugly +/// Searching the asm string to determine such a property is enormously ugly /// and wastes resources. /// Sorry, I know and do feel bad about it. But for now it works. static bool AArch64_check_post_index_am(const MCInst *MI, const SStream *OS) { @@ -279,7 +279,7 @@ static void AArch64_check_updates_flags(MCInst *MI) if (!detail_is_set(MI)) return; cs_detail *detail = get_detail(MI); - // Implicity written registers + // Implicitly written registers for (int i = 0; i < detail->regs_write_count; ++i) { if (detail->regs_write[i] == 0) break; diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h index 01a96fd69c..a982885fa3 100644 --- a/arch/AArch64/AArch64Mapping.h +++ b/arch/AArch64/AArch64Mapping.h @@ -14,7 +14,7 @@ typedef enum { #include "AArch64GenCSOpGroup.inc" } aarch64_op_group; -// return name of regiser in friendly string +// return name of register in friendly string const char *AArch64_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/ARM/ARMAddressingModes.h b/arch/ARM/ARMAddressingModes.h index c6d248287e..16d4b14337 100644 --- a/arch/ARM/ARMAddressingModes.h +++ b/arch/ARM/ARMAddressingModes.h @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMBaseInfo.c b/arch/ARM/ARMBaseInfo.c index 0f46c31639..fc15921eb6 100644 --- a/arch/ARM/ARMBaseInfo.c +++ b/arch/ARM/ARMBaseInfo.c @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMDisassembler.c b/arch/ARM/ARMDisassembler.c index da91a758e1..383c7b1be1 100644 --- a/arch/ARM/ARMDisassembler.c +++ b/arch/ARM/ARMDisassembler.c @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ @@ -6411,7 +6411,7 @@ static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst *Inst, unsigned Val, // Inst. Reason is because MRRC2 stores to two // registers so it's tablegen desc has has two // outputs whereas MCRR doesn't store to any - // registers so all of it's operands are listed + // registers so all of its operands are listed // as inputs, therefore the operand order for // MRRC2 needs to be [Rt, Rt2, cop, opc1, CRm] // and MCRR2 operand order is [cop, opc1, Rt, Rt2, CRm] diff --git a/arch/ARM/ARMInstPrinter.c b/arch/ARM/ARMInstPrinter.c index 212887d1c4..14170eb522 100644 --- a/arch/ARM/ARMInstPrinter.c +++ b/arch/ARM/ARMInstPrinter.c @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMInstPrinter.h b/arch/ARM/ARMInstPrinter.h index 772584756c..dcc7ba141e 100644 --- a/arch/ARM/ARMInstPrinter.h +++ b/arch/ARM/ARMInstPrinter.h @@ -7,7 +7,7 @@ /* LLVM-tag: llvmorg-16.0.2-5-g464bda7750a3 */ /* Only small edits allowed. */ -/* For multiple similiar edits, please create a Patch for the translator. */ +/* For multiple similar edits, please create a Patch for the translator. */ /* Capstone's C++ file translator: */ /* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */ diff --git a/arch/ARM/ARMLinkage.h b/arch/ARM/ARMLinkage.h index deb3b9842a..3dc431d14b 100644 --- a/arch/ARM/ARMLinkage.h +++ b/arch/ARM/ARMLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_ARM_LINKAGE_H #define CS_ARM_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/ARM/ARMMapping.c b/arch/ARM/ARMMapping.c index 19cbcd11f6..beb0214a02 100644 --- a/arch/ARM/ARMMapping.c +++ b/arch/ARM/ARMMapping.c @@ -531,7 +531,7 @@ static void ARM_add_not_defined_ops(MCInst *MI) } /// Unfortunately there is currently no way to easily extract -/// informaion about the vector data usage (sign and width used). +/// information about the vector data usage (sign and width used). /// See: https://github.com/capstone-engine/capstone/issues/2152 void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type) { @@ -541,7 +541,7 @@ void ARM_add_vector_data(MCInst *MI, arm_vectordata_type data_type) } /// Unfortunately there is currently no way to easily extract -/// informaion about the vector size. +/// information about the vector size. /// See: https://github.com/capstone-engine/capstone/issues/2152 void ARM_add_vector_size(MCInst *MI, unsigned size) { @@ -2110,7 +2110,7 @@ void ARM_set_detail_op_sysop(MCInst *MI, int Val, arm_op_type type, ARM_get_detail_op(MI, 0)->type = type; switch (type) { default: - assert(0 && "Unkown system operand type."); + assert(0 && "Unknown system operand type."); case ARM_OP_SYSREG: ARM_get_detail_op(MI, 0)->sysop.reg.mclasssysreg = Val; break; diff --git a/arch/ARM/ARMMapping.h b/arch/ARM/ARMMapping.h index 045530302c..21092428f3 100644 --- a/arch/ARM/ARMMapping.h +++ b/arch/ARM/ARMMapping.h @@ -17,7 +17,7 @@ ARMBankedReg_lookupBankedRegByEncoding(uint8_t Encoding); extern const ARMSysReg_MClassSysReg * ARMSysReg_lookupMClassSysRegByEncoding(uint16_t Encoding); -// return name of regiser in friendly string +// return name of register in friendly string const char *ARM_reg_name(csh handle, unsigned int reg); void ARM_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info); diff --git a/arch/Alpha/AlphaLinkage.h b/arch/Alpha/AlphaLinkage.h index c3501ddecd..ae5008da8b 100644 --- a/arch/Alpha/AlphaLinkage.h +++ b/arch/Alpha/AlphaLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_ALPHA_LINKAGE_H #define CS_ALPHA_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCInst.h" #include "../../MCRegisterInfo.h" diff --git a/arch/HPPA/HPPADisassembler.c b/arch/HPPA/HPPADisassembler.c index 5da27156e0..7db01d7e93 100644 --- a/arch/HPPA/HPPADisassembler.c +++ b/arch/HPPA/HPPADisassembler.c @@ -884,7 +884,7 @@ static void fill_alu_mods(uint32_t insn, hppa_ext *hppa_ext, cs_mode mode) goto unit_cond; case 0x2f: push_str_modifier(hppa_ext, "i"); - // fallthough + // fallthrough case 0x26: case 0x0e: case 0x2e: @@ -2857,7 +2857,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) case 0x05: CREATE_FPR_REG(MI, r1); CREATE_FPR_REG(MI, t); - // fallthough + // fallthrough case 0x00: break; default: @@ -2882,7 +2882,7 @@ static bool decode_copr(const cs_struct *ud, MCInst *MI, uint32_t insn) case 0x00: CREATE_FPR_REG(MI, r1); CREATE_FPR_REG(MI, r2); - // fallthough + // fallthrough case 0x01: break; default: @@ -3041,7 +3041,7 @@ static void fill_float_mods(uint32_t insn, uint32_t class, hppa_ext *hppa_ext, return; case 0x03: push_str_modifier(hppa_ext, "t"); - // fallthough + // fallthrough case 0x02: push_str_modifier(hppa_ext, float_format_names[sf]); diff --git a/arch/M680X/M680XDisassembler.c b/arch/M680X/M680XDisassembler.c index a0ade36733..6e71c465f3 100644 --- a/arch/M680X/M680XDisassembler.c +++ b/arch/M680X/M680XDisassembler.c @@ -149,7 +149,7 @@ typedef struct insn_props { ////////////////////////////////////////////////////////////////////////////// -// M680X instuctions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2). +// M680X instructions have 1 up to 8 bytes (CPU12: MOVW IDX2,IDX2). // A reader is needed to read a byte or word from a given memory address. // See also X86 reader(...) static bool read_byte(const m680x_info *info, uint8_t *byte, uint16_t address) @@ -627,7 +627,7 @@ typedef struct insn_desc { uint16_t insn_size; } insn_desc; -// If successfull return the additional byte size needed for M6809 +// If successful return the additional byte size needed for M6809 // indexed addressing mode (including the indexed addressing post_byte). // On error return -1. static int get_indexed09_post_byte_size(const m680x_info *info, @@ -681,7 +681,7 @@ static int get_indexed09_post_byte_size(const m680x_info *info, return 1; } -// If successfull return the additional byte size needed for CPU12 +// If successful return the additional byte size needed for CPU12 // indexed addressing mode (including the indexed addressing post_byte). // On error return -1. static int get_indexed12_post_byte_size(const m680x_info *info, @@ -750,7 +750,7 @@ static bool is_tfm_reg_valid(const m680x_info *info, uint8_t reg_nibble) return reg_nibble <= 4; } -// If successfull return the additional byte size needed for CPU12 +// If successful return the additional byte size needed for CPU12 // loop instructions DBEQ/DBNE/IBEQ/IBNE/TBEQ/TBNE (including the post byte). // On error return -1. static int get_loop_post_byte_size(const m680x_info *info, uint16_t address) @@ -772,7 +772,7 @@ static int get_loop_post_byte_size(const m680x_info *info, uint16_t address) return 2; } -// If successfull return the additional byte size needed for HD6309 +// If successful return the additional byte size needed for HD6309 // bit move instructions BAND/BEOR/BIAND/BIEOR/BIOR/BOR/LDBT/STBT // (including the post byte). // On error return -1. @@ -1885,7 +1885,7 @@ static unsigned int m680x_disassemble(MCInst *MI, m680x_info *info, access_mode = g_insn_props[info->insn].access_mode; - // Fix for M6805 BSET/BCLR. It has a differnt operand order + // Fix for M6805 BSET/BCLR. It has a different operand order // in comparison to the M6811 if ((info->cpu->insn_cc_not_modified[0] == info->insn) || (info->cpu->insn_cc_not_modified[1] == info->insn)) diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c index b502e5ae9f..5c555ae4c1 100644 --- a/arch/M68K/M68KDisassembler.c +++ b/arch/M68K/M68KDisassembler.c @@ -3526,7 +3526,7 @@ static void build_regs_read_write_counts(m68k_info *info) // first operand is always read update_op_reg_list(info, &info->extension.operands[0], 0); - // remaning write + // remaining write for (i = 1; i < info->extension.op_count; ++i) update_op_reg_list(info, &info->extension.operands[i], 1); } diff --git a/arch/Mips/MipsDisassembler.c b/arch/Mips/MipsDisassembler.c index 294082394a..c5c6b5c97b 100644 --- a/arch/Mips/MipsDisassembler.c +++ b/arch/Mips/MipsDisassembler.c @@ -365,7 +365,7 @@ void Mips_init(MCRegisterInfo *MRI) } /// Read two bytes from the ArrayRef and return 16 bit halfword sorted -/// according to the given endianess. +/// according to the given endianness. static void readInstruction16(unsigned char *code, uint32_t *insn, bool isBigEndian) { @@ -377,7 +377,7 @@ static void readInstruction16(unsigned char *code, uint32_t *insn, } /// readInstruction - read four bytes from the MemoryObject -/// and return 32 bit word sorted according to the given endianess +/// and return 32 bit word sorted according to the given endianness static void readInstruction32(unsigned char *code, uint32_t *insn, bool isBigEndian, bool isMicroMips) { // High 16 bits of a 32-bit microMIPS instruction (where the opcode is) diff --git a/arch/Mips/MipsMapping.h b/arch/Mips/MipsMapping.h index 42b86e6e98..2b5c95dce5 100644 --- a/arch/Mips/MipsMapping.h +++ b/arch/Mips/MipsMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *Mips_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/PowerPC/PPCInstPrinter.c b/arch/PowerPC/PPCInstPrinter.c index 7ce0916fd8..a13aa0fbd9 100644 --- a/arch/PowerPC/PPCInstPrinter.c +++ b/arch/PowerPC/PPCInstPrinter.c @@ -650,7 +650,7 @@ void printTLSCall(MCInst *MI, unsigned OpNo, SStream *O) { add_cs_detail(MI, PPC_OP_GROUP_TLSCall, OpNo); - // Expresion logic removed. + // Expression logic removed. set_mem_access(MI, true); SStream_concat0(O, "("); @@ -682,7 +682,7 @@ bool showRegistersWithPercentPrefix(const MCInst *MI, const char *RegName) } /// getVerboseConditionalRegName - This method expands the condition register -/// when requested explicitly or targetting Darwin. +/// when requested explicitly or targeting Darwin. const char *getVerboseConditionRegName(const MCInst *MI, unsigned RegNum, unsigned RegEncoding) { diff --git a/arch/PowerPC/PPCLinkage.h b/arch/PowerPC/PPCLinkage.h index 58725c59bb..9b0463a3a9 100644 --- a/arch/PowerPC/PPCLinkage.h +++ b/arch/PowerPC/PPCLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_PPC_LINKAGE_H #define CS_PPC_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c index 73444de7fa..f3e4503f73 100644 --- a/arch/PowerPC/PPCMapping.c +++ b/arch/PowerPC/PPCMapping.c @@ -203,7 +203,7 @@ void PPC_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen) } } -/// Inialize PPCs detail. +/// Initialize PPCs detail. void PPC_init_cs_detail(MCInst *MI) { if (!detail_is_set(MI)) diff --git a/arch/PowerPC/PPCMapping.h b/arch/PowerPC/PPCMapping.h index bfaaa3009e..a30813144b 100644 --- a/arch/PowerPC/PPCMapping.h +++ b/arch/PowerPC/PPCMapping.h @@ -16,7 +16,7 @@ void PPC_init_mri(MCRegisterInfo *MRI); void PPC_init_cs_detail(MCInst *MI); -// return name of regiser in friendly string +// return name of register in friendly string const char *PPC_reg_name(csh handle, unsigned int reg); void PPC_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info); diff --git a/arch/RISCV/RISCVGenAsmWriter.inc b/arch/RISCV/RISCVGenAsmWriter.inc index dadbd5c621..b4dde75836 100644 --- a/arch/RISCV/RISCVGenAsmWriter.inc +++ b/arch/RISCV/RISCVGenAsmWriter.inc @@ -2619,7 +2619,7 @@ static void printCustomAliasOperand( static bool RISCVInstPrinterValidateMCOperand(MCOperand *MCOp, unsigned PredicateIndex) { // TODO: need some constant untils operate the MCOperand, - // but current CAPSTONE does't have. + // but current CAPSTONE doesn't have. // So, We just return true return true; diff --git a/arch/SH/SHDisassembler.c b/arch/SH/SHDisassembler.c index 879a8508a5..8f788096b4 100644 --- a/arch/SH/SHDisassembler.c +++ b/arch/SH/SHDisassembler.c @@ -2108,7 +2108,7 @@ static bool sh_disassemble(const uint8_t *code, MCInst *MI, uint64_t address, insn = code[1] << 8 | code[0]; } if (mode & CS_MODE_SH2A) { - /* SH2A 32bit instrcution test */ + /* SH2A 32bit instruction test */ if (((insn & 0xf007) == 0x3001 || (insn & 0xf00e) == 0x0000)) { if (code_len < 4) diff --git a/arch/Sparc/SparcMapping.h b/arch/Sparc/SparcMapping.h index 1c8c1b19d6..9c930f0f51 100644 --- a/arch/Sparc/SparcMapping.h +++ b/arch/Sparc/SparcMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *Sparc_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/SystemZ/SystemZMapping.h b/arch/SystemZ/SystemZMapping.h index 9a6ceb356e..0f8909cea2 100644 --- a/arch/SystemZ/SystemZMapping.h +++ b/arch/SystemZ/SystemZMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *SystemZ_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/TMS320C64x/TMS320C64xMapping.h b/arch/TMS320C64x/TMS320C64xMapping.h index ce26d3e89a..e8514283f9 100644 --- a/arch/TMS320C64x/TMS320C64xMapping.h +++ b/arch/TMS320C64x/TMS320C64xMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *TMS320C64x_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/TriCore/TriCoreCallingConv.td b/arch/TriCore/TriCoreCallingConv.td index 0a43914802..f9ebe1b30a 100644 --- a/arch/TriCore/TriCoreCallingConv.td +++ b/arch/TriCore/TriCoreCallingConv.td @@ -46,7 +46,7 @@ def CC_TriCore : CallingConv<[ // Pointer arguments are handled inside TriCoreIselLowering, because // LLVM lowers i32** type into i32, hence there is no way to distingusish - // beetwen a pointer type and an integer type. + // between a pointer type and an integer type. diff --git a/arch/TriCore/TriCoreLinkage.h b/arch/TriCore/TriCoreLinkage.h index cfee58f77f..3689de36c2 100644 --- a/arch/TriCore/TriCoreLinkage.h +++ b/arch/TriCore/TriCoreLinkage.h @@ -4,7 +4,7 @@ #ifndef CS_TRICORE_LINKAGE_H #define CS_TRICORE_LINKAGE_H -// Function defintions to call static LLVM functions. +// Function definitions to call static LLVM functions. #include "../../MCDisassembler.h" #include "../../MCInst.h" diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c index 800d9e4e70..3106dc74a0 100644 --- a/arch/X86/X86ATTInstPrinter.c +++ b/arch/X86/X86ATTInstPrinter.c @@ -534,7 +534,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) if (MCOperand_isImm(Op)) { int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; - // truncat imm for non-64bit + // truncate imm for non-64bit if (MI->csh->mode != CS_MODE_64) { imm = imm & 0xffffffff; } diff --git a/arch/X86/X86DisassemblerDecoder.c b/arch/X86/X86DisassemblerDecoder.c index 22acab36e5..95ac06f8b7 100644 --- a/arch/X86/X86DisassemblerDecoder.c +++ b/arch/X86/X86DisassemblerDecoder.c @@ -1155,8 +1155,8 @@ static int getID(struct InternalInstruction *insn) } /* - * The tables can't distinquish between cases where the W-bit is used to - * select register size and cases where its a required part of the opcode. + * The tables can't distinguish between cases where the W-bit is used to + * select register size and cases where it's a required part of the opcode. */ if ((insn->vectorExtensionType == TYPE_EVEX && wFromEVEX3of4(insn->vectorExtensionPrefix[2])) || diff --git a/arch/X86/X86IntelInstPrinter.c b/arch/X86/X86IntelInstPrinter.c index bdd4457850..7f83cddd5d 100644 --- a/arch/X86/X86IntelInstPrinter.c +++ b/arch/X86/X86IntelInstPrinter.c @@ -765,7 +765,7 @@ static void printPCRelImm(MCInst *MI, unsigned OpNo, SStream *O) int64_t imm = MCOperand_getImm(Op) + MI->flat_insn->size + MI->address; uint8_t opsize = X86_immediate_size(MI->Opcode, NULL); - // truncat imm for non-64bit + // truncate imm for non-64bit if (MI->csh->mode != CS_MODE_64) { imm = imm & 0xffffffff; } diff --git a/arch/X86/X86Mapping.c b/arch/X86/X86Mapping.c index a5b8729082..46ecfcb77b 100644 --- a/arch/X86/X86Mapping.c +++ b/arch/X86/X86Mapping.c @@ -2098,7 +2098,7 @@ void op_addAvxBroadcast(MCInst *MI, x86_avx_bcast v) #ifndef CAPSTONE_DIET // map instruction to its characteristics typedef struct insn_op { - uint64_t flags; // how this instruction update EFLAGS(arithmetic instrcutions) of FPU FLAGS(for FPU instructions) + uint64_t flags; // how this instruction update EFLAGS(arithmetic instructions) of FPU FLAGS(for FPU instructions) uint8_t access[6]; } insn_op; diff --git a/arch/X86/X86Mapping.h b/arch/X86/X86Mapping.h index c6dc40377f..933f208dfa 100644 --- a/arch/X86/X86Mapping.h +++ b/arch/X86/X86Mapping.h @@ -32,7 +32,7 @@ x86_reg x86_map_sib_index(int r); // map seg_override to x86_reg x86_reg x86_map_segment(int r); -// return name of regiser in friendly string +// return name of register in friendly string const char *X86_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/arch/XCore/XCoreMapping.h b/arch/XCore/XCoreMapping.h index f9b506a252..f4cad95c91 100644 --- a/arch/XCore/XCoreMapping.h +++ b/arch/XCore/XCoreMapping.h @@ -6,7 +6,7 @@ #include "capstone/capstone.h" -// return name of regiser in friendly string +// return name of register in friendly string const char *XCore_reg_name(csh handle, unsigned int reg); // given internal insn id, return public instruction info diff --git a/bindings/java/capstone/Capstone.java b/bindings/java/capstone/Capstone.java index b1117d242d..1a37b5d400 100644 --- a/bindings/java/capstone/Capstone.java +++ b/bindings/java/capstone/Capstone.java @@ -490,13 +490,13 @@ public void setMode(int opt) { } } - // destructor automatically caled at destroyed time. + // destructor automatically called at destroyed time. protected void finalize() { // FIXME: crashed on Ubuntu 14.04 64bit, OpenJDK java 1.6.0_33 // cs.cs_close(ns.handleRef); } - // destructor automatically caled at destroyed time. + // destructor automatically called at destroyed time. public int close() { return cs.cs_close(ns.handleRef); } diff --git a/bindings/ocaml/capstone.ml b/bindings/ocaml/capstone.ml index 9019cde996..7899091826 100644 --- a/bindings/ocaml/capstone.ml +++ b/bindings/ocaml/capstone.ml @@ -63,7 +63,7 @@ type mode = (* Runtime option for the disassembled engine *) type opt_type = - | CS_OPT_SYNTAX (* Asssembly output syntax *) + | CS_OPT_SYNTAX (* Assembly output syntax *) | CS_OPT_DETAIL (* Break down instruction structure into details *) | CS_OPT_MODE (* Change engine's mode at run-time *) | CS_OPT_MEM (* User-defined dynamic memory related functions *) diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py index 8e1174e396..154e6f1105 100755 --- a/bindings/python/capstone/__init__.py +++ b/bindings/python/capstone/__init__.py @@ -341,7 +341,7 @@ CS_GRP_BRANCH_RELATIVE = 7 # all relative branching instructions # Access types for instruction operands. -CS_AC_INVALID = 0 # Invalid/unitialized access type. +CS_AC_INVALID = 0 # Invalid/uninitialized access type. CS_AC_READ = (1 << 0) # Operand that is read from. CS_AC_WRITE = (1 << 1) # Operand that is written to. CS_AC_READ_WRITE = (2) diff --git a/bindings/python/test_x86.py b/bindings/python/test_x86.py index 3c08e7783c..3ac5348dab 100755 --- a/bindings/python/test_x86.py +++ b/bindings/python/test_x86.py @@ -180,7 +180,7 @@ def print_string_hex(comment, str): # print instruction's opcode print_string_hex("\tOpcode:", insn.opcode) - # print operand's REX prefix (non-zero value is relavant for x86_64 instructions) + # print operand's REX prefix (non-zero value is relevant for x86_64 instructions) print("\trex: 0x%x" % (insn.rex)) # print operand's address size diff --git a/bindings/vb6/CX86Inst.cls b/bindings/vb6/CX86Inst.cls index bfdb19765e..70e62258d4 100644 --- a/bindings/vb6/CX86Inst.cls +++ b/bindings/vb6/CX86Inst.cls @@ -31,12 +31,12 @@ Option Explicit ' // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) ' uint8_t prefix[4]; ' -' // Instruction opcode, wich can be from 1 to 4 bytes in size. +' // Instruction opcode, which can be from 1 to 4 bytes in size. ' // This contains VEX opcode as well. ' // An trailing opcode byte gets value 0 when irrelevant. ' uint8_t opcode[4]; ' -' // REX prefix: only a non-zero value is relavant for x86_64 +' // REX prefix: only a non-zero value is relevant for x86_64 ' uint8_t rex; ' ' // Address size, which can be overrided with above prefix[5]. @@ -54,7 +54,7 @@ Option Explicit ' /* SIB state */ ' // SIB index register, or X86_REG_INVALID when irrelevant. ' x86_reg sib_index; -' // SIB scale. only applicable if sib_index is relavant. +' // SIB scale. only applicable if sib_index is relevant. ' int8_t sib_scale; ' // SIB base register, or X86_REG_INVALID when irrelevant. ' x86_reg sib_base; diff --git a/bindings/vb6/mMisc.bas b/bindings/vb6/mMisc.bas index 2ccb1308e0..561d1b68d7 100644 --- a/bindings/vb6/mMisc.bas +++ b/bindings/vb6/mMisc.bas @@ -148,7 +148,7 @@ Function AryIsEmpty(ary) As Boolean Dim i As Long On Error GoTo oops - i = UBound(ary) '<- throws error if not initalized + i = UBound(ary) '<- throws error if not initialized AryIsEmpty = False Exit Function oops: AryIsEmpty = True @@ -211,7 +211,7 @@ Private Sub bpush(bAry() As Byte, b As Byte) 'this modifies parent ary object On Error GoTo init Dim x As Long - x = UBound(bAry) '<-throws Error If Not initalized + x = UBound(bAry) '<-throws Error If Not initialized ReDim Preserve bAry(UBound(bAry) + 1) bAry(UBound(bAry)) = b diff --git a/bindings/vb6/mx86.bas b/bindings/vb6/mx86.bas index 2fc47da180..c10b8b4ecc 100644 --- a/bindings/vb6/mx86.bas +++ b/bindings/vb6/mx86.bas @@ -388,18 +388,18 @@ Public Type cs_x86 ' prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE) prefix(0 To 3) As Byte ' UNSIGNED - ' Instruction opcode, wich can be from 1 to 4 bytes in size. + ' Instruction opcode, which can be from 1 to 4 bytes in size. ' This contains VEX opcode as well. ' An trailing opcode byte gets value 0 when irrelevant. opcode(0 To 3) As Byte ' UNSIGNED - rex As Byte ' REX prefix: only a non-zero value is relavant for x86_64 UNSIGNED + rex As Byte ' REX prefix: only a non-zero value is relevant for x86_64 UNSIGNED addr_size As Byte ' Address size, which can be overrided with above prefix[5]. UNSIGNED modrm As Byte ' ModR/M byte UNSIGNED sib As Byte ' SIB value, or 0 when irrelevant. UNSIGNED disp As Long ' Displacement value, or 0 when irrelevant. sib_index As x86_reg ' SIB index register, or X86_REG_INVALID when irrelevant. - sib_scale As Byte ' SIB scale. only applicable if sib_index is relavant. + sib_scale As Byte ' SIB scale. only applicable if sib_index is relevant. sib_base As x86_reg ' SIB base register, or X86_REG_INVALID when irrelevant. sse_cc As x86_sse_cc ' SSE Code Condition avx_cc As x86_avx_cc ' AVX Code Condition diff --git a/config.mk b/config.mk index 5b7a3d14e0..fb92ac7449 100644 --- a/config.mk +++ b/config.mk @@ -25,7 +25,7 @@ CAPSTONE_USE_SYS_DYN_MEM ?= yes # such as @regs_read/write & @group. The amount of binary size reduced is # up to 50% in some individual archs. # -# NOTE: we still keep all those related fileds @mnemonic, @op_str, @regs_read, +# NOTE: we still keep all those related fields @mnemonic, @op_str, @regs_read, # @regs_write, @groups, etc in fields in cs_insn structure regardless, but they # will not be updated (i.e empty), thus become irrelevant. diff --git a/cs.c b/cs.c index 25476df9f6..65f89b8e5b 100644 --- a/cs.c +++ b/cs.c @@ -784,7 +784,7 @@ static int str_replace(char *result, char *target, const char *str1, char *str2) { // only perform replacement if the output fits into result if (strlen(target) - strlen(str1) + strlen(str2) < CS_MNEMONIC_SIZE - 1) { - // copy str2 to begining of result + // copy str2 to beginning of result strcpy(result, str2); // skip str1 - already replaced by str2 strcat(result, target + strlen(str1)); @@ -1120,7 +1120,7 @@ static void skipdata_opstr(char *opstr, const uint8_t *buffer, size_t size) } #endif -// dynamicly allocate memory to contain disasm insn +// dynamically allocate memory to contain disasm insn // NOTE: caller must free() the allocated memory itself to avoid memory leaking CAPSTONE_EXPORT size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64_t offset, size_t count, cs_insn **insn) @@ -1288,7 +1288,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 // continue to fill in the cache after the last instruction insn_cache = (cs_insn *)((char *)total + sizeof(cs_insn) * c); - // reset f back to 0, so we fill in the cache from begining + // reset f back to 0, so we fill in the cache from beginning f = 0; } else insn_cache++; diff --git a/include/capstone/cs_operand.h b/include/capstone/cs_operand.h index 9110813c1b..81f2697c46 100644 --- a/include/capstone/cs_operand.h +++ b/include/capstone/cs_operand.h @@ -26,8 +26,8 @@ typedef enum cs_op_type { CS_OP_SPECIAL = 0x10, ///< Special operands from archs CS_OP_MEM = 0x80, ///< Memory operand. Can be ORed with another operand type. - CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referenceing register operand. - CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referenceing immediate operand. + CS_OP_MEM_REG = CS_OP_MEM | CS_OP_REG, ///< Memory referencing register operand. + CS_OP_MEM_IMM = CS_OP_MEM | CS_OP_IMM, ///< Memory referencing immediate operand. } cs_op_type; diff --git a/include/capstone/m680x.h b/include/capstone/m680x.h index c8296e49de..07533cce97 100644 --- a/include/capstone/m680x.h +++ b/include/capstone/m680x.h @@ -161,7 +161,7 @@ typedef enum m680x_group_type { /// instruction mnemonic #define M680X_SECOND_OP_IN_MNEM 2 -/// The M680X instruction and it's operands +/// The M680X instruction and its operands typedef struct cs_m680x { uint8_t flags; ///< See: M680X instruction flags uint8_t op_count; ///< number of operands for the instruction or 0 diff --git a/include/capstone/m68k.h b/include/capstone/m68k.h index 41e23f3883..35918d38ac 100644 --- a/include/capstone/m68k.h +++ b/include/capstone/m68k.h @@ -206,7 +206,7 @@ typedef struct m68k_op_size { }; } m68k_op_size; -/// The M68K instruction and it's operands +/// The M68K instruction and its operands typedef struct cs_m68k { // Number of operands of this instruction or 0 when instruction has no operand. cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction. diff --git a/include/capstone/mos65xx.h b/include/capstone/mos65xx.h index 13c2788a3e..e942c96184 100644 --- a/include/capstone/mos65xx.h +++ b/include/capstone/mos65xx.h @@ -186,7 +186,7 @@ typedef struct cs_mos65xx_op { }; } cs_mos65xx_op; -/// The MOS65XX address mode and it's operands +/// The MOS65XX address mode and its operands typedef struct cs_mos65xx { mos65xx_address_mode am; bool modifies_flags; diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h index 27789dafe3..b38c4eee97 100644 --- a/include/capstone/ppc.h +++ b/include/capstone/ppc.h @@ -42,7 +42,7 @@ extern "C" { /// |--------|-------------|-------|------------|------------| /// Alter- | | Hint bit: | | Hint bit: | Hint bit: | /// native | None | a | None | a | t | -/// meaning | | or ingored | | or ignored | or ignored | +/// meaning | | or ignored | | or ignored | or ignored | /// /// NOTE: If we do not decrement the counter, it is not used for the condition. /// @@ -62,8 +62,8 @@ typedef enum ppc_pred { PPC_PRED_GE = (0 << 5) | 4, PPC_PRED_GT = (1 << 5) | 12, PPC_PRED_NE = (2 << 5) | 4, - PPC_PRED_UN = (3 << 5) | 12, ///< Unordered (after fp comparision) - PPC_PRED_NU = (3 << 5) | 4, ///< Not Unordered (after fp comparision) + PPC_PRED_UN = (3 << 5) | 12, ///< Unordered (after fp comparison) + PPC_PRED_NU = (3 << 5) | 4, ///< Not Unordered (after fp comparison) PPC_PRED_SO = (3 << 5) | 12, ///< summary overflow PPC_PRED_NS = (3 << 5) | 4, ///< not summary overflow @@ -154,7 +154,7 @@ typedef enum { } ppc_bh; -/// Returns the predicate wihtout branch hint information. +/// Returns the predicate without branch hint information. inline static ppc_pred PPC_get_no_hint_pred(ppc_pred Code) { switch (Code) { diff --git a/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch b/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch index 795f5ba5f6..d59b2dc870 100644 --- a/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch +++ b/suite/auto-sync/inc_patches/ARM/01_LDM_written_reglists.patch @@ -1,4 +1,4 @@ -# Sets the correct access attributes for register lists of LDM instrucions. +# Sets the correct access attributes for register lists of LDM instructions. # See issue: https://github.com/llvm/llvm-project/issues/62455 diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc diff --git a/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch b/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch index fadb1a462f..5c59b0d873 100644 --- a/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch +++ b/suite/auto-sync/inc_patches/ARM/02_VSCCLRM_written_reglists.patch @@ -1,4 +1,4 @@ -# Sets the correct access attributes for register lists of VSCCLRM instrucions. +# Sets the correct access attributes for register lists of VSCCLRM instructions. # See issue: https://github.com/llvm/llvm-project/issues/62455 diff --git a/arch/ARM/ARMGenCSMappingInsnOp.inc b/arch/ARM/ARMGenCSMappingInsnOp.inc diff --git a/suite/autogen_x86imm.py b/suite/autogen_x86imm.py index 1e6fb67803..a764b81a65 100755 --- a/suite/autogen_x86imm.py +++ b/suite/autogen_x86imm.py @@ -1,6 +1,6 @@ #!/usr/bin/python # By Nguyen Anh Quynh, 2015 -# This tool extract sizes of immediadte operands from X86 instruction names. +# This tool extract sizes of immediate operands from X86 instruction names. # Syntax: ./autogen_x86imm.py # Gather immediate sizes to put into X86ImmSize.inc diff --git a/suite/cstest/README.md b/suite/cstest/README.md index a9880dadf6..d2d2b4cc8e 100644 --- a/suite/cstest/README.md +++ b/suite/cstest/README.md @@ -19,7 +19,7 @@ mkdir build cd build cmake .. make -sudo make isntall +sudo make install ``` ## Build diff --git a/suite/disasm_mc.sh b/suite/disasm_mc.sh index 8de5a1529b..6b8936cd2c 100755 --- a/suite/disasm_mc.sh +++ b/suite/disasm_mc.sh @@ -4,7 +4,7 @@ find MC/ -name *.cs | ./disasm_mc.py -# To test just one architecture, specify the corresponsing dir: +# To test just one architecture, specify the corresponding dir: # $ find MC/X86 -name *.cs | ./disasm_mc.py # To test just one input file, run disasm_mc.py with that file: diff --git a/suite/fuzz/driverbin.c b/suite/fuzz/driverbin.c index d5e3a0fcc2..dfb5293850 100644 --- a/suite/fuzz/driverbin.c +++ b/suite/fuzz/driverbin.c @@ -77,7 +77,7 @@ int main(int argc, char** argv) } printf("\n"); - //lauch fuzzer + //launch fuzzer LLVMFuzzerTestOneInput(Data, Size); fclose(fp); } diff --git a/suite/fuzz/drivermc.c b/suite/fuzz/drivermc.c index ff31ebdeec..5b53543d3c 100644 --- a/suite/fuzz/drivermc.c +++ b/suite/fuzz/drivermc.c @@ -128,7 +128,7 @@ int main(int argc, char** argv) return 1; } } - //lauch fuzzer + //launch fuzzer LLVMFuzzerTestOneInput(Data, Size); } fclose(fp); diff --git a/suite/fuzz/onefile.c b/suite/fuzz/onefile.c index 74be3063a8..c3c6551abc 100644 --- a/suite/fuzz/onefile.c +++ b/suite/fuzz/onefile.c @@ -42,7 +42,7 @@ int main(int argc, char** argv) return 2; } - //lauch fuzzer + //launch fuzzer LLVMFuzzerTestOneInput(Data, Size); free(Data); fclose(fp); diff --git a/suite/synctools/README b/suite/synctools/README index 61a0ec45d8..247ee93439 100644 --- a/suite/synctools/README +++ b/suite/synctools/README @@ -11,7 +11,7 @@ For X86 2. Run disassemblertables_reduce2 & disassemblertables_reduce2 to generate optimized (index table) X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc - # use 2x name to avoid overwritting X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc + # use 2x name to avoid overwriting X86GenDisassemblerTables2.inc & X86GenDisassemblerTables_reduce2.inc $ make $ ./disassemblertables2 > X86GenDisassemblerTables2x.inc diff --git a/suite/synctools/asmwriter.py b/suite/synctools/asmwriter.py index 33d0a22312..7549b64ceb 100755 --- a/suite/synctools/asmwriter.py +++ b/suite/synctools/asmwriter.py @@ -682,7 +682,7 @@ def print_line(line): break; } } - // Chech for match + // Check for match if(opcode != OpToPatterns[OpToIndex].Opcode) return NULL; diff --git a/suite/synctools/tablegen/X86/X86InstrAVX512.td b/suite/synctools/tablegen/X86/X86InstrAVX512.td index 17ac45ba6f..3872b128ba 100644 --- a/suite/synctools/tablegen/X86/X86InstrAVX512.td +++ b/suite/synctools/tablegen/X86/X86InstrAVX512.td @@ -107,7 +107,7 @@ class X86VectorVTInfo("v" # !srl(Size, 6) # "i64"); @@ -251,7 +251,7 @@ multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. // This version uses a separate dag for non-masking and masking. multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, @@ -272,7 +272,7 @@ multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -423,7 +423,7 @@ multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -7557,7 +7557,7 @@ multiclass avx512_cvt_fp_scalar opc, string OpcodeStr, X86VectorVTInfo _ } } -// Scalar Coversion with SAE - suppress all exceptions +// Scalar Conversion with SAE - suppress all exceptions multiclass avx512_cvt_fp_sae_scalar opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { @@ -7671,7 +7671,7 @@ multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, ))>, EVEX, EVEX_B, Sched<[sched.Folded]>; } -// Coversion with SAE - suppress all exceptions +// Conversion with SAE - suppress all exceptions multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { diff --git a/suite/synctools/tablegen/X86/X86InstrCompiler.td b/suite/synctools/tablegen/X86/X86InstrCompiler.td index 373f850203..76b93bdada 100644 --- a/suite/synctools/tablegen/X86/X86InstrCompiler.td +++ b/suite/synctools/tablegen/X86/X86InstrCompiler.td @@ -795,9 +795,9 @@ defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; // the base pointer. Indeed, in such situation RBX is a reserved // register and the register allocator will ignore any use/def of // it. In other words, the register will not fix the clobbering of -// RBX that will happen when setting the arguments for the instrucion. +// RBX that will happen when setting the arguments for the instruction. // -// Unlike the actual related instuction, we mark that this one +// Unlike the actual related instruction, we mark that this one // defines EBX (instead of using EBX). // The rationale is that we will define RBX during the expansion of // the pseudo. The argument feeding EBX is ebx_input. diff --git a/suite/synctools/tablegen/X86/X86InstrFMA.td b/suite/synctools/tablegen/X86/X86InstrFMA.td index a559f62c8f..18277417a3 100644 --- a/suite/synctools/tablegen/X86/X86InstrFMA.td +++ b/suite/synctools/tablegen/X86/X86InstrFMA.td @@ -166,7 +166,7 @@ let ExeDomain = SSEPackedDouble in { } // All source register operands of FMA opcodes defined in fma3s_rm multiclass -// can be commuted. In many cases such commute transformation requres an opcode +// can be commuted. In many cases such commute transformation requires an opcode // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form // would require an opcode change to FMA*231: // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; diff --git a/suite/synctools/tablegen/X86/X86InstrFPStack.td b/suite/synctools/tablegen/X86/X86InstrFPStack.td index b0c9bd1637..a21f077927 100644 --- a/suite/synctools/tablegen/X86/X86InstrFPStack.td +++ b/suite/synctools/tablegen/X86/X86InstrFPStack.td @@ -242,7 +242,7 @@ defm MUL : FPBinary_rr; defm DIV : FPBinary_rr; } -// Sets the scheduling resources for the actual NAME#_Fm defintions. +// Sets the scheduling resources for the actual NAME#_Fm definitions. let SchedRW = [WriteFAddLd] in { defm ADD : FPBinary; defm SUB : FPBinary; diff --git a/suite/synctools/tablegen/X86/X86InstrSSE.td b/suite/synctools/tablegen/X86/X86InstrSSE.td index c99af69f6f..5c6b4155b1 100644 --- a/suite/synctools/tablegen/X86/X86InstrSSE.td +++ b/suite/synctools/tablegen/X86/X86InstrSSE.td @@ -1004,7 +1004,7 @@ defm CVTSI642SD : sse12_cvt_s<0x2A, GR64, FR64, sint_to_fp, i64mem, loadi64, // and/or XMM operand(s). // FIXME: We probably want to match the rm form only when optimizing for -// size, to avoid false depenendecies (see sse_fp_unop_s for details) +// size, to avoid false dependencies (see sse_fp_unop_s for details) multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, Operand memop, ComplexPattern mem_cpat, string asm, X86FoldableSchedWrite sched> { @@ -3122,7 +3122,7 @@ def PAUSE : I<0x90, RawFrm, (outs), (ins), let SchedRW = [WriteFence] in { // Load, store, and memory fence -// TODO: As with mfence, we may want to ease the availablity of sfence/lfence +// TODO: As with mfence, we may want to ease the availability of sfence/lfence // to include any 64-bit target. def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, PS, Requires<[HasSSE1]>; diff --git a/suite/synctools/tablegen/X86/X86InstrSystem.td b/suite/synctools/tablegen/X86/X86InstrSystem.td index 5bb0a5f37d..5bc58e298c 100644 --- a/suite/synctools/tablegen/X86/X86InstrSystem.td +++ b/suite/synctools/tablegen/X86/X86InstrSystem.td @@ -711,7 +711,7 @@ def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, let Predicates = [In64BitMode, HasRDPID] in { // Due to silly instruction definition, we have to compensate for the - // instruction outputing a 64-bit register. + // instruction outputting a 64-bit register. def : Pat<(int_x86_rdpid), (EXTRACT_SUBREG (RDPID64), sub_32bit)>; } diff --git a/suite/synctools/tablegen/X86/X86InstrTSX.td b/suite/synctools/tablegen/X86/X86InstrTSX.td index b1fdd18074..8b9f723a41 100644 --- a/suite/synctools/tablegen/X86/X86InstrTSX.td +++ b/suite/synctools/tablegen/X86/X86InstrTSX.td @@ -32,7 +32,7 @@ def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), "xbegin\t$dst", []>, OpSize32; } -// Psuedo instruction to fake the definition of EAX on the fallback code path. +// Pseudo instruction to fake the definition of EAX on the fallback code path. //let isPseudo = 1, Defs = [EAX] in { //def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; //} diff --git a/suite/synctools/tablegen/X86/X86RegisterInfo.td b/suite/synctools/tablegen/X86/X86RegisterInfo.td index ee9e7891f9..907d402223 100644 --- a/suite/synctools/tablegen/X86/X86RegisterInfo.td +++ b/suite/synctools/tablegen/X86/X86RegisterInfo.td @@ -488,7 +488,7 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; -// When RBP is used as a base pointer in a 32-bit addresses environement, +// When RBP is used as a base pointer in a 32-bit addresses environment, // this is also safe to use the full register to access addresses. // Since RBP will never be spilled, stick to a 32 alignment to save // on memory consumption. diff --git a/suite/synctools/tablegen/X86/X86Schedule.td b/suite/synctools/tablegen/X86/X86Schedule.td index ef9ce94706..6215d58ae1 100644 --- a/suite/synctools/tablegen/X86/X86Schedule.td +++ b/suite/synctools/tablegen/X86/X86Schedule.td @@ -628,8 +628,8 @@ def SchedWriteFShuffleSizes // Generic Processor Scheduler Models. // IssueWidth is analogous to the number of decode units. Core and its -// descendents, including Nehalem and SandyBridge have 4 decoders. -// Resources beyond the decoder operate on micro-ops and are bufferred +// descendants, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are buffered // so adjacent micro-ops don't directly compete. // // MicroOpBufferSize > 1 indicates that RAW dependencies can be diff --git a/suite/synctools/tablegen/X86/X86ScheduleAtom.td b/suite/synctools/tablegen/X86/X86ScheduleAtom.td index a7f461c456..daa6fc73cc 100644 --- a/suite/synctools/tablegen/X86/X86ScheduleAtom.td +++ b/suite/synctools/tablegen/X86/X86ScheduleAtom.td @@ -20,8 +20,8 @@ def AtomModel : SchedMachineModel { let IssueWidth = 2; // Allows 2 instructions per scheduling group. let MicroOpBufferSize = 0; // In-order execution, always hide latency. - let LoadLatency = 3; // Expected cycles, may be overriden. - let HighLatency = 30;// Expected, may be overriden. + let LoadLatency = 3; // Expected cycles, may be overridden. + let HighLatency = 30;// Expected, may be overridden. // On the Atom, the throughput for taken branches is 2 cycles. For small // simple loops, expand by a small factor to hide the backedge cost. diff --git a/suite/synctools/tablegen/X86/back/X86InstrAVX512.td b/suite/synctools/tablegen/X86/back/X86InstrAVX512.td index 43f16634c2..fcb3723121 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrAVX512.td +++ b/suite/synctools/tablegen/X86/back/X86InstrAVX512.td @@ -107,7 +107,7 @@ class X86VectorVTInfo("v" # !srl(Size, 6) # "i64"); @@ -251,7 +251,7 @@ multiclass AVX512_maskable_common O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. // This version uses a separate dag for non-masking and masking. multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, @@ -272,7 +272,7 @@ multiclass AVX512_maskable_split O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -423,7 +423,7 @@ multiclass AVX512_maskable_cmp_alt O, Format F, X86VectorVTInfo _, // This multiclass generates the unconditional/non-masking, the masking and // the zero-masking variant of the vector instruction. In the masking case, the -// perserved vector elements come from a new dummy input operand tied to $dst. +// preserved vector elements come from a new dummy input operand tied to $dst. multiclass AVX512_maskable_logic O, Format F, X86VectorVTInfo _, dag Outs, dag Ins, string OpcodeStr, string AttSrcAsm, string IntelSrcAsm, @@ -7557,7 +7557,7 @@ multiclass avx512_cvt_fp_scalar opc, string OpcodeStr, X86VectorVTInfo _ } } -// Scalar Coversion with SAE - suppress all exceptions +// Scalar Conversion with SAE - suppress all exceptions multiclass avx512_cvt_fp_sae_scalar opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { @@ -7671,7 +7671,7 @@ multiclass avx512_vcvt_fp opc, string OpcodeStr, X86VectorVTInfo _, ))>, EVEX, EVEX_B, Sched<[sched.Folded]>; } -// Coversion with SAE - suppress all exceptions +// Conversion with SAE - suppress all exceptions multiclass avx512_vcvt_fp_sae opc, string OpcodeStr, X86VectorVTInfo _, X86VectorVTInfo _Src, SDNode OpNodeRnd, X86FoldableSchedWrite sched> { diff --git a/suite/synctools/tablegen/X86/back/X86InstrCompiler.td b/suite/synctools/tablegen/X86/back/X86InstrCompiler.td index 373f850203..76b93bdada 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrCompiler.td +++ b/suite/synctools/tablegen/X86/back/X86InstrCompiler.td @@ -795,9 +795,9 @@ defm LCMPXCHG8B : LCMPXCHG_UnOp<0xC7, MRM1m, "cmpxchg8b", X86cas8, i64mem>; // the base pointer. Indeed, in such situation RBX is a reserved // register and the register allocator will ignore any use/def of // it. In other words, the register will not fix the clobbering of -// RBX that will happen when setting the arguments for the instrucion. +// RBX that will happen when setting the arguments for the instruction. // -// Unlike the actual related instuction, we mark that this one +// Unlike the actual related instruction, we mark that this one // defines EBX (instead of using EBX). // The rationale is that we will define RBX during the expansion of // the pseudo. The argument feeding EBX is ebx_input. diff --git a/suite/synctools/tablegen/X86/back/X86InstrFMA.td b/suite/synctools/tablegen/X86/back/X86InstrFMA.td index a559f62c8f..18277417a3 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrFMA.td +++ b/suite/synctools/tablegen/X86/back/X86InstrFMA.td @@ -166,7 +166,7 @@ let ExeDomain = SSEPackedDouble in { } // All source register operands of FMA opcodes defined in fma3s_rm multiclass -// can be commuted. In many cases such commute transformation requres an opcode +// can be commuted. In many cases such commute transformation requires an opcode // adjustment, for example, commuting the operands 1 and 2 in FMA*132 form // would require an opcode change to FMA*231: // FMA*132* reg1, reg2, reg3; // reg1 * reg3 + reg2; diff --git a/suite/synctools/tablegen/X86/back/X86InstrFPStack.td b/suite/synctools/tablegen/X86/back/X86InstrFPStack.td index b0c9bd1637..a21f077927 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrFPStack.td +++ b/suite/synctools/tablegen/X86/back/X86InstrFPStack.td @@ -242,7 +242,7 @@ defm MUL : FPBinary_rr; defm DIV : FPBinary_rr; } -// Sets the scheduling resources for the actual NAME#_Fm defintions. +// Sets the scheduling resources for the actual NAME#_Fm definitions. let SchedRW = [WriteFAddLd] in { defm ADD : FPBinary; defm SUB : FPBinary; diff --git a/suite/synctools/tablegen/X86/back/X86InstrSSE.td b/suite/synctools/tablegen/X86/back/X86InstrSSE.td index 910b80636f..54db88114a 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrSSE.td +++ b/suite/synctools/tablegen/X86/back/X86InstrSSE.td @@ -1004,7 +1004,7 @@ def : InstAlias<"cvtsi2sd\t{$src, $dst|$dst, $src}", // and/or XMM operand(s). // FIXME: We probably want to match the rm form only when optimizing for -// size, to avoid false depenendecies (see sse_fp_unop_s for details) +// size, to avoid false dependencies (see sse_fp_unop_s for details) multiclass sse12_cvt_sint opc, RegisterClass SrcRC, RegisterClass DstRC, Intrinsic Int, Operand memop, ComplexPattern mem_cpat, string asm, X86FoldableSchedWrite sched> { @@ -3122,7 +3122,7 @@ def PAUSE : I<0x90, RawFrm, (outs), (ins), let SchedRW = [WriteFence] in { // Load, store, and memory fence -// TODO: As with mfence, we may want to ease the availablity of sfence/lfence +// TODO: As with mfence, we may want to ease the availability of sfence/lfence // to include any 64-bit target. def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>, PS, Requires<[HasSSE1]>; diff --git a/suite/synctools/tablegen/X86/back/X86InstrSystem.td b/suite/synctools/tablegen/X86/back/X86InstrSystem.td index e9dba76f44..c0d51aa3bf 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrSystem.td +++ b/suite/synctools/tablegen/X86/back/X86InstrSystem.td @@ -699,7 +699,7 @@ def RDPID64 : I<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdpid\t$dst", []>, XS, let Predicates = [In64BitMode, HasRDPID] in { // Due to silly instruction definition, we have to compensate for the - // instruction outputing a 64-bit register. + // instruction outputting a 64-bit register. def : Pat<(int_x86_rdpid), (EXTRACT_SUBREG (RDPID64), sub_32bit)>; } diff --git a/suite/synctools/tablegen/X86/back/X86InstrTSX.td b/suite/synctools/tablegen/X86/back/X86InstrTSX.td index b1fdd18074..8b9f723a41 100644 --- a/suite/synctools/tablegen/X86/back/X86InstrTSX.td +++ b/suite/synctools/tablegen/X86/back/X86InstrTSX.td @@ -32,7 +32,7 @@ def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst), "xbegin\t$dst", []>, OpSize32; } -// Psuedo instruction to fake the definition of EAX on the fallback code path. +// Pseudo instruction to fake the definition of EAX on the fallback code path. //let isPseudo = 1, Defs = [EAX] in { //def XABORT_DEF : I<0, Pseudo, (outs), (ins), "# XABORT DEF", []>; //} diff --git a/suite/synctools/tablegen/X86/back/X86RegisterInfo.td b/suite/synctools/tablegen/X86/back/X86RegisterInfo.td index ee9e7891f9..907d402223 100644 --- a/suite/synctools/tablegen/X86/back/X86RegisterInfo.td +++ b/suite/synctools/tablegen/X86/back/X86RegisterInfo.td @@ -488,7 +488,7 @@ def GR64_NOREX_NOSP : RegisterClass<"X86", [i64], 64, // which we do not have right now. def LOW32_ADDR_ACCESS : RegisterClass<"X86", [i32], 32, (add GR32, RIP)>; -// When RBP is used as a base pointer in a 32-bit addresses environement, +// When RBP is used as a base pointer in a 32-bit addresses environment, // this is also safe to use the full register to access addresses. // Since RBP will never be spilled, stick to a 32 alignment to save // on memory consumption. diff --git a/suite/synctools/tablegen/X86/back/X86Schedule.td b/suite/synctools/tablegen/X86/back/X86Schedule.td index ef9ce94706..6215d58ae1 100644 --- a/suite/synctools/tablegen/X86/back/X86Schedule.td +++ b/suite/synctools/tablegen/X86/back/X86Schedule.td @@ -628,8 +628,8 @@ def SchedWriteFShuffleSizes // Generic Processor Scheduler Models. // IssueWidth is analogous to the number of decode units. Core and its -// descendents, including Nehalem and SandyBridge have 4 decoders. -// Resources beyond the decoder operate on micro-ops and are bufferred +// descendants, including Nehalem and SandyBridge have 4 decoders. +// Resources beyond the decoder operate on micro-ops and are buffered // so adjacent micro-ops don't directly compete. // // MicroOpBufferSize > 1 indicates that RAW dependencies can be diff --git a/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td b/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td index a7f461c456..daa6fc73cc 100644 --- a/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td +++ b/suite/synctools/tablegen/X86/back/X86ScheduleAtom.td @@ -20,8 +20,8 @@ def AtomModel : SchedMachineModel { let IssueWidth = 2; // Allows 2 instructions per scheduling group. let MicroOpBufferSize = 0; // In-order execution, always hide latency. - let LoadLatency = 3; // Expected cycles, may be overriden. - let HighLatency = 30;// Expected, may be overriden. + let LoadLatency = 3; // Expected cycles, may be overridden. + let HighLatency = 30;// Expected, may be overridden. // On the Atom, the throughput for taken branches is 2 cycles. For small // simple loops, expand by a small factor to hide the backedge cost. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h b/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h index 1190d6061e..e49ac1b6c1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/AccelTable.h @@ -190,7 +190,7 @@ class AccelTableBase { }; /// This class holds an abstract representation of an Accelerator Table, -/// consisting of a sequence of buckets, each bucket containint a sequence of +/// consisting of a sequence of buckets, each bucket containing a sequence of /// HashData entries. The class is parameterized by the type of entries it /// holds. The type template parameter also defines the hash function to use for /// hashing names. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h b/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h index c5c2b57486..7c7cb04ca9 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/AntiDepBreaker.h @@ -39,7 +39,7 @@ class AntiDepBreaker { /// Initialize anti-dep breaking for a new basic block. virtual void StartBlock(MachineBasicBlock *BB) = 0; - /// Identifiy anti-dependencies within a basic-block region and break them by + /// Identify anti-dependencies within a basic-block region and break them by /// renaming registers. Return the number of anti-dependencies broken. virtual unsigned BreakAntiDependencies(const std::vector &SUnits, MachineBasicBlock::iterator Begin, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h b/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h index d911bfd435..40898d8a81 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/AsmPrinter.h @@ -268,7 +268,7 @@ class AsmPrinter : public MachineFunctionPass { void EmitToStreamer(MCStreamer &S, const MCInst &Inst); - /// Emits inital debug location directive. + /// Emits initial debug location directive. void emitInitialRawDwarfLocDirective(const MachineFunction &MF); /// Return the current section we are emitting to. @@ -444,7 +444,7 @@ class AsmPrinter : public MachineFunctionPass { /// Print a general LLVM constant to the .s file. void emitGlobalConstant(const DataLayout &DL, const Constant *CV); - /// Unnamed constant global variables solely contaning a pointer to + /// Unnamed constant global variables solely containing a pointer to /// another globals variable act like a global variable "proxy", or GOT /// equivalents, i.e., it's only used to hold the address of the latter. One /// optimization is to replace accesses to these proxies by using the GOT diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h b/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h index 0b27376289..83e09115e5 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/BasicTTIImpl.h @@ -447,7 +447,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { /// Relative lookup table entries consist of 32-bit offsets. /// Do not generate relative lookup tables for large code models - /// in 64-bit achitectures where 32-bit offsets might not be enough. + /// in 64-bit architectures where 32-bit offsets might not be enough. if (TM.getCodeModel() == CodeModel::Medium || TM.getCodeModel() == CodeModel::Large) return false; @@ -2198,7 +2198,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase { // The minimal length of the vector is limited by the real length of vector // operations performed on the current platform. That's why several final - // reduction opertions are perfomed on the vectors with the same + // reduction operations are performed on the vectors with the same // architecture-dependent length. ShuffleCost += NumReduxLevels * thisT()->getShuffleCost( TTI::SK_PermuteSingleSrc, Ty, None, 0, Ty); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h index dbc36888fb..5fc32cd9a5 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/CodeGenPassBuilder.h @@ -409,7 +409,7 @@ template class CodeGenPassBuilder { /// codegen pass pipeline where targets may insert passes. Methods with /// out-of-line standard implementations are major CodeGen stages called by /// addMachinePasses. Some targets may override major stages when inserting - /// passes is insufficient, but maintaining overriden stages is more work. + /// passes is insufficient, but maintaining overridden stages is more work. /// /// addMachineSSAOptimization - Add standard passes that optimize machine @@ -448,11 +448,11 @@ template class CodeGenPassBuilder { /// this target at the current optimization level. void addTargetRegisterAllocator(AddMachinePass &, bool Optimized) const; - /// addMachinePasses helper to create the target-selected or overriden + /// addMachinePasses helper to create the target-selected or overridden /// regalloc pass. void addRegAllocPass(AddMachinePass &, bool Optimized) const; - /// Add core register alloator passes which do the actual register assignment + /// Add core register allocator passes which do the actual register assignment /// and rewriting. \returns true if any passes were added. Error addRegAssignmentFast(AddMachinePass &) const; Error addRegAssignmentOptimized(AddMachinePass &) const; @@ -830,7 +830,7 @@ Error CodeGenPassBuilder::addCoreISelPasses( /// with nontrivial configuration or multiple passes are broken out below in /// add%Stage routines. /// -/// Any CodeGenPassBuilder::addXX routine may be overriden by the +/// Any CodeGenPassBuilder::addXX routine may be overridden by the /// Target. The addPre/Post methods with empty header implementations allow /// injecting target-specific fixups just before or after major stages. /// Additionally, targets have the flexibility to change pass order within a @@ -1023,7 +1023,7 @@ void CodeGenPassBuilder::addRegAllocPass(AddMachinePass &addPass, else if (Opt.RegAlloc == RegAllocType::PBQP) addPass(RAPBQPPass()); else - llvm_unreachable("unknonwn register allocator type"); + llvm_unreachable("unknown register allocator type"); } template diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h b/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h index 9cdaedc9e8..7668d76f80 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/DFAPacketizer.h @@ -94,7 +94,7 @@ class DFAPacketizer { // packet. The resources are returned as a bitvector of functional units. // // Note that a bundle may be packed in multiple valid ways. This function - // returns one arbitary valid packing. + // returns one arbitrary valid packing. // // Requires setTrackResources(true) to have been called. unsigned getUsedResources(unsigned InstIdx); @@ -179,7 +179,7 @@ class VLIWPacketizerList { return false; } - // Check if it is legal to prune dependece between SUI and SUJ. + // Check if it is legal to prune dependence between SUI and SUJ. virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) { return false; } diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h b/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h index 45823b2ba3..c0305b834a 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/DebugHandlerBase.h @@ -92,7 +92,7 @@ class DebugHandlerBase : public AsmPrinterHandler { /// Maps instruction with label emitted after instruction. DenseMap LabelsAfterInsn; - /// Indentify instructions that are marking the beginning of or + /// Identify instructions that are marking the beginning of or /// ending of a scope. void identifyScopeMarkers(); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h index 03f4f3bf0b..0f1b11b1b1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/InstructionSelector.h @@ -560,7 +560,7 @@ class InstructionSelector { /// Return true if MI can obviously be folded into IntoMI. /// MI and IntoMI do not need to be in the same basic blocks, but MI must - /// preceed IntoMI. + /// precede IntoMI. bool isObviouslySafeToFold(MachineInstr &MI, MachineInstr &IntoMI) const; }; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h index 3cacdc99db..281ca39ccd 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h @@ -161,7 +161,7 @@ class LegacyLegalizerInfo { } /// The setAction calls record the non-size-changing legalization actions - /// to take on specificly-sized types. The SizeChangeStrategy defines what + /// to take on specifically-sized types. The SizeChangeStrategy defines what /// to do when the size of the type needs to be changed to reach a legally /// sized type (i.e., one that was defined through a setAction call). /// e.g. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h index 179f2f07ac..cf4c649b9c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h @@ -82,7 +82,7 @@ class LegalizerHelper { LegalizeResult legalizeInstrStep(MachineInstr &MI, LostDebugLocObserver &LocObserver); - /// Legalize an instruction by emiting a runtime library call instead. + /// Legalize an instruction by emitting a runtime library call instead. LegalizeResult libcall(MachineInstr &MI, LostDebugLocObserver &LocObserver); /// Legalize an instruction by reducing the width of the underlying scalar diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index c09c69b062..1e7111cd23 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -945,7 +945,7 @@ class MachineIRBuilder { /// Build and insert instructions to put \p Ops together at the specified p /// Indices to form a larger register. /// - /// If the types of the input registers are uniform and cover the entirity of + /// If the types of the input registers are uniform and cover the entirety of /// \p Res then a G_MERGE_VALUES will be produced. Otherwise an IMPLICIT_DEF /// followed by a sequence of G_INSERT instructions. /// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h index 45006eecfc..421aa555dc 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegBankSelect.h @@ -610,7 +610,7 @@ class RegBankSelect : public MachineFunctionPass { /// Apply \p Mapping to \p MI. \p RepairPts represents the different /// mapping action that need to happen for the mapping to be /// applied. - /// \return True if the mapping was applied sucessfully, false otherwise. + /// \return True if the mapping was applied successfully, false otherwise. bool applyMapping(MachineInstr &MI, const RegisterBankInfo::InstructionMapping &InstrMapping, SmallVectorImpl &RepairPts); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h index da785406bc..906819bb2c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h @@ -40,7 +40,7 @@ class RegisterBankInfo { public: /// Helper struct that represents how a value is partially mapped /// into a register. - /// The StartIdx and Length represent what region of the orginal + /// The StartIdx and Length represent what region of the original /// value this partial mapping covers. /// This can be represented as a Mask of contiguous bit starting /// at StartIdx bit and spanning Length bits. @@ -77,7 +77,7 @@ class RegisterBankInfo { void print(raw_ostream &OS) const; /// Check that the Mask is compatible with the RegBank. - /// Indeed, if the RegBank cannot accomadate the "active bits" of the mask, + /// Indeed, if the RegBank cannot accommodate the "active bits" of the mask, /// there is no way this mapping is valid. /// /// \note This method does not check anything when assertions are disabled. @@ -255,7 +255,7 @@ class RegisterBankInfo { return getID() != InvalidMappingID && OperandsMapping; } - /// Verifiy that this mapping makes sense for \p MI. + /// Verify that this mapping makes sense for \p MI. /// \pre \p MI must be connected to a MachineFunction. /// /// \note This method does not check anything when assertions are disabled. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h index c2b722e084..f343f2dd72 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ISDOpcodes.h @@ -294,7 +294,7 @@ enum NodeType { /// subtraction. These nodes take three operands: The first two are normal lhs /// and rhs to the add or sub, and the third is a boolean indicating if there /// is an incoming carry. They produce two results: the normal result of the - /// add or sub, and a boolean that indicates if an overflow occured (*not* + /// add or sub, and a boolean that indicates if an overflow occurred (*not* /// flag, because it may be a store to memory, etc.). If the type of the /// boolean is not i1 then the high bits conform to getBooleanContents. SADDO_CARRY, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h b/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h index 9617ba80c1..0366de8ecb 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LexicalScopes.h @@ -142,7 +142,7 @@ class LexicalScopes { public: LexicalScopes() = default; - /// initialize - Scan machine function and constuct lexical scope nest, resets + /// initialize - Scan machine function and construct lexical scope nest, resets /// the instance if necessary. void initialize(const MachineFunction &); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h index 09ae23bb2c..7de2e42f26 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveInterval.h @@ -359,7 +359,7 @@ namespace llvm { /// Merge all of the live segments of a specific val# in RHS into this live /// range as the specified value number. The segments in RHS are allowed /// to overlap with segments in the current range, it will replace the - /// value numbers of the overlaped live segments with the specified value + /// value numbers of the overlapped live segments with the specified value /// number. void MergeSegmentsInAsValue(const LiveRange &RHS, VNInfo *LHSValNo); @@ -416,7 +416,7 @@ namespace llvm { } /// getVNInfoBefore - Return the VNInfo that is live up to but not - /// necessarilly including Idx, or NULL. Use this to find the reaching def + /// necessarily including Idx, or NULL. Use this to find the reaching def /// used by an instruction at this SlotIndex position. VNInfo *getVNInfoBefore(SlotIndex Idx) const { const_iterator I = FindSegmentContaining(Idx.getPrevSlot()); @@ -977,7 +977,7 @@ namespace llvm { } /// ConnectedVNInfoEqClasses - Helper class that can divide VNInfos in a - /// LiveInterval into equivalence clases of connected components. A + /// LiveInterval into equivalence classes of connected components. A /// LiveInterval that has multiple connected components can be broken into /// multiple LiveIntervals. /// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h index fa08166791..22d10bb93a 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveIntervals.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // /// \file This file implements the LiveInterval analysis pass. Given some -/// numbering of each the machine instructions (in this implemention depth-first +/// numbering of each the machine instructions (in this implementation depth-first /// order) an interval [i, j) is said to be a live interval for register v if /// there is no instruction with number j' > j such that v is live at j' and /// there is no instruction with number i' < i such that v is live at i'. In diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h b/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h index 99ba1a28c9..710737feff 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LivePhysRegs.h @@ -51,7 +51,7 @@ class LivePhysRegs { RegisterSet LiveRegs; public: - /// Constructs an unitialized set. init() needs to be called to initialize it. + /// Constructs an uninitialized set. init() needs to be called to initialize it. LivePhysRegs() = default; /// Constructs and initializes an empty set. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h index d80522f5bd..7000bfac7d 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRangeEdit.h @@ -161,7 +161,7 @@ class LiveRangeEdit : private MachineRegisterInfo::Delegate { /// dead after rematerialization, we still want to keep it for following /// rematerializations. We save the def instruction in DeadRemats, /// and replace the original dst register with a new dummy register so - /// the live range of original dst register can be shrinked normally. + /// the live range of original dst register can be shrunk normally. /// We don't want to allocate phys register for the dummy register, so /// we want to drop it from the NewRegs set. void pop_back() { NewRegs.pop_back(); } diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h index 39a1ec461e..3ef3e6bab4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LiveRegUnits.h @@ -43,7 +43,7 @@ class LiveRegUnits { /// For a machine instruction \p MI, adds all register units used in /// \p UsedRegUnits and defined or clobbered in \p ModifiedRegUnits. This is /// useful when walking over a range of instructions to track registers - /// used or defined seperately. + /// used or defined separately. static void accumulateUsedDefed(const MachineInstr &MI, LiveRegUnits &ModifiedRegUnits, LiveRegUnits &UsedRegUnits, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h b/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h index 93d140cabd..eaa4594d92 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/LoopTraversal.h @@ -33,7 +33,7 @@ class MachineFunction; /// We want to visit every instruction in every basic block in order to update /// it's execution domain or collect clearance information. However, for the /// clearance calculation, we need to know clearances from all predecessors -/// (including any backedges), therfore we need to visit some blocks twice. +/// (including any backedges), therefore we need to visit some blocks twice. /// As an example, consider the following loop. /// /// @@ -57,7 +57,7 @@ class MachineFunction; /// straight-line code, and a small loop, that would be a lot of unnecessary /// work (since only the BBs that are part of the loop require two passes). /// -/// E.g., the naive iteration order for the above exmple is as follows: +/// E.g., the naive iteration order for the above example is as follows: /// Naive: PH A B C D A' B' C' D' /// /// In the optimized approach we avoid processing D twice, because we @@ -80,7 +80,7 @@ class LoopTraversal { MBBInfo() = default; }; using MBBInfoMap = SmallVector; - /// Helps keep track if we proccessed this block and all its predecessors. + /// Helps keep track if we processed this block and all its predecessors. MBBInfoMap MBBInfos; public: diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h b/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h index fb276ff117..12be5ede28 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MIRFormatter.h @@ -42,7 +42,7 @@ class MIRFormatter { } /// Implement target specific parsing of immediate mnemonics. The mnemonic is - /// dot seperated strings. + /// dot separated strings. virtual bool parseImmMnemonic(const unsigned OpCode, const unsigned OpIdx, StringRef Src, int64_t &Imm, ErrorCallbackType ErrorCallback) const { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h b/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h index 45e30686b6..5e94418d5f 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MIRPrinter.h @@ -34,7 +34,7 @@ void printMIR(raw_ostream &OS, const MachineFunction &MF); /// you the correct list of successor blocks in most cases except for things /// like jump tables where the basic block references can't easily be found. /// The MIRPRinter will skip printing successors if they match the result of -/// this funciton and the parser will use this function to construct a list if +/// this function and the parser will use this function to construct a list if /// it is missing. void guessSuccessors(const MachineBasicBlock &MBB, SmallVectorImpl &Result, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h b/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h index 2503524ccf..a9638fc3fd 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MIRSampleProfile.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This file contains the supoorting functions for machine level Sample FDO +// This file contains the supporting functions for machine level Sample FDO // loader. This is used in Flow Sensitive SampelFDO. // //===----------------------------------------------------------------------===// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h index 638b6732a5..02a7308d54 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBasicBlock.h @@ -787,7 +787,7 @@ class MachineBasicBlock /// \c SkipPseudoOp should be true when it's used in optimizations that /// unlikely hurt profile quality, e.g., without block merging. The default /// value of \c SkipPseudoOp is set to true to maximize code quality in - /// general, with an explict false value passed in in a few places like branch + /// general, with an explicit false value passed in in a few places like branch /// folding and if-conversion to favor profile quality. iterator getFirstNonDebugInstr(bool SkipPseudoOp = true); const_iterator getFirstNonDebugInstr(bool SkipPseudoOp = true) const { @@ -809,7 +809,7 @@ class MachineBasicBlock /// \c SkipPseudoOp should be true when it's used in optimizations that /// unlikely hurt profile quality, e.g., without block merging. The default /// value of \c SkipPseudoOp is set to true to maximize code quality in - /// general, with an explict false value passed in in a few places like branch + /// general, with an explicit false value passed in in a few places like branch /// folding and if-conversion to favor profile quality. iterator getLastNonDebugInstr(bool SkipPseudoOp = true); const_iterator getLastNonDebugInstr(bool SkipPseudoOp = true) const { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h index 7e7e0a9c47..06f9ee3abb 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineBranchProbabilityInfo.h @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// // -// This pass is used to evaluate branch probabilties on machine basic blocks. +// This pass is used to evaluate branch probabilities on machine basic blocks. // //===----------------------------------------------------------------------===// diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h index 864ca73180..0105c14101 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFrameInfo.h @@ -148,7 +148,7 @@ class MachineFrameInfo { /// register allocator. bool isStatepointSpillSlot = false; - /// Identifier for stack memory type analagous to address space. If this is + /// Identifier for stack memory type analogous to address space. If this is /// non-0, the meaning is target defined. Offsets cannot be directly /// compared between objects with different stack IDs. The object may not /// necessarily reside in the same contiguous memory block as other stack diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h index c4767a51b0..a41fcb4072 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineFunction.h @@ -906,7 +906,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// into \p MBB before \p InsertBefore. /// /// Note: Does not perform target specific adjustments; consider using - /// TargetInstrInfo::duplicate() intead. + /// TargetInstrInfo::duplicate() instead. MachineInstr & cloneMachineInstrBundle(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore, @@ -1020,7 +1020,7 @@ class LLVM_EXTERNAL_VISIBILITY MachineFunction { /// Returns a reference to a list of cfi instructions in the function's /// prologue. Used to construct frame maps for debug and exception handling - /// comsumers. + /// consumers. const std::vector &getFrameInstructions() const { return FrameInstructions; } diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h index 2893e138a9..357dba79f4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineInstr.h @@ -96,7 +96,7 @@ class MachineInstr FmContract = 1 << 8, // Instruction supports Fast math // contraction operations like fma. FmAfn = 1 << 9, // Instruction may map to Fast math - // instrinsic approximation. + // intrinsic approximation. FmReassoc = 1 << 10, // Instruction supports Fast math // reassociation of operand order. NoUWrap = 1 << 11, // Instruction supports binary operator @@ -488,7 +488,7 @@ class MachineInstr /// Returns the opcode of this MachineInstr. unsigned getOpcode() const { return MCID->Opcode; } - /// Retuns the total number of operands. + /// Returns the total number of operands. unsigned getNumOperands() const { return NumOperands; } /// Returns the total number of operands which are debug locations. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h index c07606e893..b7569acf4d 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineModuleInfo.h @@ -64,14 +64,14 @@ class MachineModuleInfoImpl { virtual ~MachineModuleInfoImpl(); protected: - /// Return the entries from a DenseMap in a deterministic sorted orer. + /// Return the entries from a DenseMap in a deterministic sorted order. /// Clears the map. static SymbolListTy getSortedStubs(DenseMap&); }; //===----------------------------------------------------------------------===// /// This class contains meta information specific to a module. Queries can be -/// made by different debugging and exception handling schemes and reformated +/// made by different debugging and exception handling schemes and reformatted /// for specific use. /// class MachineModuleInfo { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h index eded28183e..9bc946a54e 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineOperand.h @@ -249,7 +249,7 @@ class MachineOperand { void clearParent() { ParentMI = nullptr; } /// Print a subreg index operand. - /// MO_Immediate operands can also be subreg idices. If it's the case, the + /// MO_Immediate operands can also be subreg indices. If it's the case, the /// subreg index name will be printed. MachineInstr::isOperandSubregIdx can be /// called to check this. static void printSubRegIdx(raw_ostream &OS, uint64_t Index, @@ -296,8 +296,8 @@ class MachineOperand { /// \param TiedOperandIdx - if we need to print register ties this needs to /// provide the index of the tied register. If not, it will be ignored. /// \param TRI - provide more target-specific information to the printer. - /// Unlike the previous function, this one will not try and get the - /// information from it's parent. + /// Unlike the previous function, this one will not try to get the + /// information from its parent. /// \param IntrinsicInfo - same as \p TRI. void print(raw_ostream &os, ModuleSlotTracker &MST, LLT TypeToPrint, Optional OpIdx, bool PrintDef, bool IsStandalone, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h index 75b8a89c81..1f1dddba02 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePassManager.h @@ -117,7 +117,7 @@ extern template class PassManager; /// `PreservedAnalyses run(MachineFunction &, /// MachineFunctionAnalysisManager &)` /// But this interface wouldn't be executed. It is just a placeholder -/// to satisfy the pass manager type-erased inteface. This +/// to satisfy the pass manager type-erased interface. This /// special-casing of machine module pass is due to its limited use /// cases and the unnecessary complexity it may bring to the machine /// pass manager. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h index 7e7fa57d80..1237005fa2 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachinePipeliner.h @@ -17,7 +17,7 @@ // // "Swing Modulo Scheduling: A Lifetime-Sensitive Approach", by J. Llosa, // A. Gonzalez, E. Ayguade, and M. Valero. In PACT '96 Proceedings of the 1996 -// Conference on Parallel Architectures and Compilation Techiniques. +// Conference on Parallel Architectures and Compilation Techniques. // // "Lifetime-Sensitive Modulo Scheduling in a Production Environment", by J. // Llosa, E. Ayguade, A. Gonzalez, M. Valero, and J. Eckhardt. In IEEE @@ -480,7 +480,7 @@ class ResourceManager { /// This class represents the scheduled code. The main data structure is a /// map from scheduled cycle to instructions. During scheduling, the /// data structure explicitly represents all stages/iterations. When -/// the algorithm finshes, the schedule is collapsed into a single stage, +/// the algorithm finishes, the schedule is collapsed into a single stage, /// which represents instructions from different loop iterations. /// /// The SMS algorithm allows negative values for cycles, so the first cycle diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h b/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h index 267c4b595e..fab296c2a1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/MachineScheduler.h @@ -174,7 +174,7 @@ class MachineSchedRegistry class ScheduleDAGMI; /// Define a generic scheduling policy for targets that don't provide their own -/// MachineSchedStrategy. This can be overriden for each scheduling region +/// MachineSchedStrategy. This can be overridden for each scheduling region /// before building the DAG. struct MachineSchedPolicy { // Allow the scheduler to disable register pressure tracking. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h b/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h index e8dbf49994..dfe8f0f517 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ModuloSchedule.h @@ -17,7 +17,7 @@ // // A schedule is, for every instruction in a block, a Cycle and a Stage. Note // that we only support single-block loops, so "block" and "loop" can be used -// interchangably. +// interchangeably. // // The Cycle of an instruction defines a partial order of the instructions in // the remapped loop. Instructions within a cycle must not consume the output diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h b/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h index 5c802802a8..5077ae8377 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/PBQP/Graph.h @@ -352,7 +352,7 @@ namespace PBQP { /// Lock this graph to the given solver instance in preparation /// for running the solver. This method will call solver.handleAddNode for /// each node in the graph, and handleAddEdge for each edge, to give the - /// solver an opportunity to set up any requried metadata. + /// solver an opportunity to set up any required metadata. void setSolver(SolverT &S) { assert(!Solver && "Solver already set. Call unsetSolver()."); Solver = &S; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h b/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h index 5144548a27..68e913576c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ReachingDefAnalysis.h @@ -138,7 +138,7 @@ class ReachingDefAnalysis : public MachineFunctionPass { void traverse(); /// Provides the instruction id of the closest reaching def instruction of - /// PhysReg that reaches MI, relative to the begining of MI's basic block. + /// PhysReg that reaches MI, relative to the beginning of MI's basic block. int getReachingDef(MachineInstr *MI, MCRegister PhysReg) const; /// Return whether A and B use the same def of PhysReg. @@ -179,7 +179,7 @@ class ReachingDefAnalysis : public MachineFunctionPass { bool isRegDefinedAfter(MachineInstr *MI, MCRegister PhysReg) const; /// Provides the clearance - the number of instructions since the closest - /// reaching def instuction of PhysReg that reaches MI. + /// reaching def instruction of PhysReg that reaches MI. int getClearance(MachineInstr *MI, MCRegister PhysReg) const; /// Provides the uses, in the same block as MI, of register that MI defines. @@ -271,7 +271,7 @@ class ReachingDefAnalysis : public MachineFunctionPass { MachineInstr *getInstFromId(MachineBasicBlock *MBB, int InstId) const; /// Provides the instruction of the closest reaching def instruction of - /// PhysReg that reaches MI, relative to the begining of MI's basic block. + /// PhysReg that reaches MI, relative to the beginning of MI's basic block. MachineInstr *getReachingLocalMIDef(MachineInstr *MI, MCRegister PhysReg) const; }; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h b/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h index 1deeb4d415..32da3e032b 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/RegisterPressure.h @@ -440,7 +440,7 @@ class RegPressureTracker { /// RegisterOperands of the instruction. void advance(const RegisterOperands &RegOpers); - /// Finalize the region boundaries and recored live ins and live outs. + /// Finalize the region boundaries and record live ins and live outs. void closeRegion(); /// Initialize the LiveThru pressure set based on the untied defs found in diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h b/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h index 7c0ebe7191..461b57f2af 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/ReplaceWithVeclib.h @@ -1,4 +1,4 @@ -//===- ReplaceWithVeclib.h - Replace vector instrinsics with veclib calls -===// +//===- ReplaceWithVeclib.h - Replace vector intrinsics with veclib calls -===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h index 4f348c9fea..6f140da1ef 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAG.h @@ -1425,7 +1425,7 @@ class SelectionDAG { /// Expand the specified \c ISD::VACOPY node as the Legalize pass would. SDValue expandVACopy(SDNode *Node); - /// Returs an GlobalAddress of the function from the current module with + /// Returns an GlobalAddress of the function from the current module with /// name matching the given ExternalSymbol. Additionally can provide the /// matched function. /// Panics the function doesn't exists. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h index 04c6b50197..40d7c4d6d1 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1761,7 +1761,7 @@ class FrameIndexSDNode : public SDNode { }; /// This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate -/// the offet and size that are started/ended in the underlying FrameIndex. +/// the offset and size that are started/ended in the underlying FrameIndex. class LifetimeSDNode : public SDNode { friend class SelectionDAG; int64_t Size; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h b/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h index 928d7cc6cc..c2f374d689 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/StackMaps.h @@ -381,7 +381,7 @@ class StackMaps { /// Record the locations of the operands of the provided instruction in a /// record keyed by the provided label. For instructions w/AnyReg calling /// convention the return register is also recorded if requested. For - /// STACKMAP, and PATCHPOINT the label is expected to immediately *preceed* + /// STACKMAP, and PATCHPOINT the label is expected to immediately *precede* /// lowering of the MI to MCInsts. For STATEPOINT, it expected to /// immediately *follow*. It's not clear this difference was intentional, /// but it exists today. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h b/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h index daaa27f72d..4ff43bfcd4 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TailDuplicator.h @@ -65,7 +65,7 @@ class TailDuplicator { /// probabilities when modifying the CFG. /// @param LayoutMode - When true, don't use the existing layout to make /// decisions. - /// @param TailDupSize - Maxmimum size of blocks to tail-duplicate. Zero + /// @param TailDupSize - Maximum size of blocks to tail-duplicate. Zero /// default implies using the command line value TailDupSize. void initMF(MachineFunction &MF, bool PreRegAlloc, const MachineBranchProbabilityInfo *MBPI, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h index 411811d08c..b937f2f284 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h @@ -140,7 +140,7 @@ class TargetInstrInfo : public MCInstrInfo { /// set, this hook lets the target specify whether the instruction is actually /// trivially rematerializable, taking into consideration its operands. This /// predicate must return false if the instruction has any side effects other - /// than producing a value, or if it requres any address registers that are + /// than producing a value, or if it requires any address registers that are /// not always available. /// Requirements must be check as stated in isTriviallyReMaterializable() . virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h index 049dee25dd..981cfe648c 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetLowering.h @@ -734,10 +734,10 @@ class TargetLoweringBase { return true; } - /// Should we tranform the IR-optimal check for whether given truncation + /// Should we transform the IR-optimal check for whether given truncation /// down into KeptBits would be truncating or not: /// (add %x, (1 << (KeptBits-1))) srccond (1 << KeptBits) - /// Into it's more traditional form: + /// Into its more traditional form: /// ((%x << C) a>> C) dstcond %x /// Return true if we should transform. /// Return false if there is no preference. @@ -822,8 +822,8 @@ class TargetLoweringBase { virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const; - /// Return the ValueType for comparison libcalls. Comparions libcalls include - /// floating point comparion calls, and Ordered/Unordered check calls on + /// Return the ValueType for comparison libcalls. Comparison libcalls include + /// floating point comparison calls, and Ordered/Unordered check calls on /// floating point numbers. virtual MVT::SimpleValueType getCmpLibcallReturnType() const; @@ -3269,7 +3269,7 @@ class TargetLoweringBase { bool isLegalRC(const TargetRegisterInfo &TRI, const TargetRegisterClass &RC) const; - /// Replace/modify any TargetFrameIndex operands with a targte-dependent + /// Replace/modify any TargetFrameIndex operands with a target-dependent /// sequence of memory operands that is recognized by PrologEpilogInserter. MachineBasicBlock *emitPatchPoint(MachineInstr &MI, MachineBasicBlock *MBB) const; @@ -4672,12 +4672,12 @@ class TargetLowering : public TargetLoweringBase { unsigned Scale, SelectionDAG &DAG) const; /// Method for building the DAG expansion of ISD::U(ADD|SUB)O. Expansion - /// always suceeds and populates the Result and Overflow arguments. + /// always succeeds and populates the Result and Overflow arguments. void expandUADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const; /// Method for building the DAG expansion of ISD::S(ADD|SUB)O. Expansion - /// always suceeds and populates the Result and Overflow arguments. + /// always succeeds and populates the Result and Overflow arguments. void expandSADDSUBO(SDNode *Node, SDValue &Result, SDValue &Overflow, SelectionDAG &DAG) const; @@ -4774,7 +4774,7 @@ class TargetLowering : public TargetLoweringBase { // combiner can fold the new nodes. SDValue lowerCmpEqZeroToCtlzSrl(SDValue Op, SelectionDAG &DAG) const; - /// Give targets the chance to reduce the number of distinct addresing modes. + /// Give targets the chance to reduce the number of distinct addressing modes. ISD::MemIndexType getCanonicalIndexType(ISD::MemIndexType IndexType, EVT MemVT, SDValue Offsets) const; diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h index ff23cffdcd..6f04a1b713 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetPassConfig.h @@ -40,11 +40,11 @@ using legacy::PassManagerBase; /// /// The PassConfig API prefers dealing with IDs because they are safer and more /// efficient. IDs decouple configuration from instantiation. This way, when a -/// pass is overriden, it isn't unnecessarily instantiated. It is also unsafe to +/// pass is overridden, it isn't unnecessarily instantiated. It is also unsafe to /// refer to a Pass pointer after adding it to a pass manager, which deletes /// redundant pass instances. /// -/// However, it is convient to directly instantiate target passes with +/// However, it is convenient to directly instantiate target passes with /// non-default ctors. These often don't have a registered PassInfo. Rather than /// force all target passes to implement the pass registry boilerplate, allow /// the PassConfig API to handle either type. @@ -209,7 +209,7 @@ class TargetPassConfig : public ImmutablePass { bool getOptimizeRegAlloc() const; /// Return true if the default global register allocator is in use and - /// has not be overriden on the command line with '-regalloc=...' + /// has not be overridden on the command line with '-regalloc=...' bool usingDefaultRegAlloc() const; /// High level function that adds all passes necessary to go from llvm IR @@ -349,7 +349,7 @@ class TargetPassConfig : public ImmutablePass { /// codegen pass pipeline where targets may insert passes. Methods with /// out-of-line standard implementations are major CodeGen stages called by /// addMachinePasses. Some targets may override major stages when inserting - /// passes is insufficient, but maintaining overriden stages is more work. + /// passes is insufficient, but maintaining overridden stages is more work. /// /// addPreISelPasses - This method should add any "last minute" LLVM->LLVM @@ -454,7 +454,7 @@ class TargetPassConfig : public ImmutablePass { /// pass. void addPass(Pass *P); - /// addMachinePasses helper to create the target-selected or overriden + /// addMachinePasses helper to create the target-selected or overridden /// regalloc pass. virtual FunctionPass *createRegAllocPass(bool Optimized); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h index c3b842052e..04a1252512 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetRegisterInfo.h @@ -680,7 +680,7 @@ class TargetRegisterInfo : public MCRegisterInfo { } /// Return the register cost table index. This implementation is sufficient - /// for most architectures and can be overriden by targets in case there are + /// for most architectures and can be overridden by targets in case there are /// multiple cost values associated with each register. virtual unsigned getRegisterCostTableIndex(const MachineFunction &MF) const { return 0; @@ -996,7 +996,7 @@ class TargetRegisterInfo : public MCRegisterInfo { return false; } - /// This method must be overriden to eliminate abstract frame indices from + /// This method must be overridden to eliminate abstract frame indices from /// instructions which may use them. The instruction referenced by the /// iterator contains an MO_FrameIndex operand which must be eliminated by /// this method. This method may modify or replace the specified instruction, @@ -1170,7 +1170,7 @@ class BitMaskClassIterator { const unsigned NumRegClasses; /// Base index of CurrentChunk. /// In other words, the number of bit we read to get at the - /// beginning of that chunck. + /// beginning of that chunk. unsigned Base = 0; /// Adjust base index of CurrentChunk. /// Base index + how many bit we read within CurrentChunk. diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h b/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h index a39f04f6db..e0ed86e97e 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/VLIWMachineScheduler.h @@ -165,7 +165,7 @@ class ConvergingVLIWScheduler : public MachineSchedStrategy { CriticalPathLength = DAG->getBBSize() / SchedModel->getIssueWidth(); if (DAG->getBBSize() < 50) // We divide by two as a cheap and simple heuristic to reduce the - // critcal path length, which increases the priority of using the graph + // critical path length, which increases the priority of using the graph // height/depth in the scheduler's cost computation. CriticalPathLength >>= 1; else { diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h b/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h index 42e8d294a6..639368fe5e 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/VirtRegMap.h @@ -189,7 +189,7 @@ class TargetInstrInfo; return Virt2StackSlotMap[virtReg.id()]; } - /// create a mapping for the specifed virtual register to + /// create a mapping for the specified virtual register to /// the next available stack slot int assignVirt2StackSlot(Register virtReg); diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h index f098316de7..ddfb49a2a3 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/WinEHFuncInfo.h @@ -32,7 +32,7 @@ class InvokeInst; class MachineBasicBlock; class MCSymbol; -// The following structs respresent the .xdata tables for various +// The following structs represent the .xdata tables for various // Windows-related EH personalities. using MBBOrBasicBlock = PointerUnion; diff --git a/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td b/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td index e40f40f74c..d47c12483a 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td +++ b/suite/synctools/tablegen/include/llvm/Frontend/Directive/DirectiveBase.td @@ -40,7 +40,7 @@ class DirectiveLanguage { // Generate include and macro to enable LLVM BitmaskEnum. bit enableBitmaskEnumInNamespace = false; - // Header file included in the implementation code generated. Ususally the + // Header file included in the implementation code generated. Usually the // output file of the declaration code generation. Can be left blank. string includeHeader = ""; @@ -108,7 +108,7 @@ class VersionedClause { // Actual clause. Clause clause = c; - // Mininum version number where this clause is valid. + // Minimum version number where this clause is valid. int minVersion = min; // Maximum version number where this clause is valid. @@ -117,7 +117,7 @@ class VersionedClause { // Information about a specific directive. class Directive { - // Name of the directive. Can be composite directive sepearted by whitespace. + // Name of the directive. Can be composite directive separated by whitespace. string name = d; // Define an alternative name return in getDirectiveName diff --git a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h index bee90281e0..695eca784f 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h +++ b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPConstants.h @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// /// \file /// -/// This file defines constans and helpers used when dealing with OpenMP. +/// This file defines constants and helpers used when dealing with OpenMP. /// //===----------------------------------------------------------------------===// @@ -62,7 +62,7 @@ enum class DefaultKind { #include "llvm/Frontend/OpenMP/OMPKinds.def" /// IDs for all omp runtime library ident_t flag encodings (see -/// their defintion in openmp/runtime/src/kmp.h). +/// their definition in openmp/runtime/src/kmp.h). enum class IdentFlag { #define OMP_IDENT_FLAG(Enum, Str, Value) Enum = Value, #include "llvm/Frontend/OpenMP/OMPKinds.def" diff --git a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h index 544f698655..ca81b94b9c 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h +++ b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPContext.h @@ -114,8 +114,8 @@ bool isValidTraitPropertyForTraitSetAndSelector(TraitProperty Property, TraitSet Set); /// Variant match information describes the required traits and how they are -/// scored (via the ScoresMap). In addition, the required consturct nesting is -/// decribed as well. +/// scored (via the ScoresMap). In addition, the required construct nesting is +/// described as well. struct VariantMatchInfo { /// Add the trait \p Property to the required trait set. \p RawString is the /// string we parsed and derived \p Property from. If \p Score is not null, it diff --git a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h index f60debe841..dd3e197b3c 100644 --- a/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/Frontend/OpenMP/OMPIRBuilder.h @@ -176,7 +176,7 @@ class OpenMPIRBuilder { /// /// \param Loc The location where the directive was encountered. /// \param IfCondition The evaluated 'if' clause expression, if any. - /// \param CanceledDirective The kind of directive that is cancled. + /// \param CanceledDirective The kind of directive that is canceled. /// /// \returns The insertion point after the barrier. InsertPointTy createCancel(const LocationDescription &Loc, Value *IfCondition, @@ -392,7 +392,7 @@ class OpenMPIRBuilder { /// \param AllocaIP An insertion point for Alloca instructions usable in the /// preheader of the loop. /// \param SchedType Type of scheduling to be passed to the init function. - /// \param NeedsBarrier Indicates whether a barrier must be insterted after + /// \param NeedsBarrier Indicates whether a barrier must be inserted after /// the loop. /// \param Chunk The size of loop chunk considered as a unit when /// scheduling. If \p nullptr, defaults to 1. @@ -418,7 +418,7 @@ class OpenMPIRBuilder { /// \param CLI A descriptor of the canonical loop to workshare. /// \param AllocaIP An insertion point for Alloca instructions usable in the /// preheader of the loop. - /// \param NeedsBarrier Indicates whether a barrier must be insterted after + /// \param NeedsBarrier Indicates whether a barrier must be inserted after /// the loop. /// /// \returns Point where to insert code after the workshare construct. @@ -699,7 +699,7 @@ class OpenMPIRBuilder { /// Generate control flow and cleanup for cancellation. /// /// \param CancelFlag Flag indicating if the cancellation is performed. - /// \param CanceledDirective The kind of directive that is cancled. + /// \param CanceledDirective The kind of directive that is canceled. /// \param ExitCB Extra code to be generated in the exit block. void emitCancelationCheckImpl(Value *CancelFlag, omp::Directive CanceledDirective, @@ -873,7 +873,7 @@ class OpenMPIRBuilder { /// /// \param Loc The insert and source location description. /// \param BodyGenCB Callback that will generate the region code. - /// \param FiniCB Callback to finialize variable copies. + /// \param FiniCB Callback to finalize variable copies. /// /// \returns The insertion position *after* the masked. InsertPointTy createMasked(const LocationDescription &Loc, @@ -1008,7 +1008,7 @@ class OpenMPIRBuilder { /// \param Loc The insert and source location description. /// \param InteropVar variable to be allocated /// \param InteropType type of interop operation - /// \param Device devide to which offloading will occur + /// \param Device device to which offloading will occur /// \param NumDependences number of dependence variables /// \param DependenceAddress pointer to dependence variables /// \param HaveNowaitClause does nowait clause exist @@ -1025,7 +1025,7 @@ class OpenMPIRBuilder { /// /// \param Loc The insert and source location description. /// \param InteropVar variable to be allocated - /// \param Device devide to which offloading will occur + /// \param Device device to which offloading will occur /// \param NumDependences number of dependence variables /// \param DependenceAddress pointer to dependence variables /// \param HaveNowaitClause does nowait clause exist @@ -1041,7 +1041,7 @@ class OpenMPIRBuilder { /// /// \param Loc The insert and source location description. /// \param InteropVar variable to be allocated - /// \param Device devide to which offloading will occur + /// \param Device device to which offloading will occur /// \param NumDependences number of dependence variables /// \param DependenceAddress pointer to dependence variables /// \param HaveNowaitClause does nowait clause exist @@ -1206,7 +1206,7 @@ class OpenMPIRBuilder { /// \param AO The required atomic ordering /// \param AK The OpenMP atomic operation kind used. /// - /// \returns wether a flush was emitted or not + /// \returns whether a flush was emitted or not bool checkAndEmitFlushAfterAtomic(const LocationDescription &Loc, AtomicOrdering AO, AtomicKind AK); @@ -1388,7 +1388,7 @@ class OpenMPIRBuilder { /// such that the CanonicalLoopInfo itself can be side-effect free. /// /// Keep in mind that CanonicalLoopInfo is meant to only describe a repeated -/// execution of a loop body that satifies these constraints. It does NOT +/// execution of a loop body that satisfies these constraints. It does NOT /// represent arbitrary SESE regions that happen to contain a loop. Do not use /// CanonicalLoopInfo for such purposes. /// @@ -1425,11 +1425,11 @@ class OpenMPIRBuilder { /// Latch to guarantee that there is only a single edge to the latch. It would /// make loop transformations easier to not needing to consider multiple /// predecessors of the latch (See redirectAllPredecessorsTo) and would give us -/// an equivalant to PreheaderIP, AfterIP and BodyIP for inserting code that +/// an equivalent to PreheaderIP, AfterIP and BodyIP for inserting code that /// executes after each body iteration. /// /// There must be no loop-carried dependencies through llvm::Values. This is -/// equivalant to that the Latch has no PHINode and the Header's only PHINode is +/// equivalent to that the Latch has no PHINode and the Header's only PHINode is /// for the induction variable. /// /// All code in Header, Cond, Latch and Exit (plus the terminator of the @@ -1487,7 +1487,7 @@ class CanonicalLoopInfo { public: /// Returns whether this object currently represents the IR of a loop. If /// returning false, it may have been consumed by a loop transformation or not - /// been intialized. Do not use in this case; + /// been initialized. Do not use in this case; bool isValid() const { return Header; } /// The preheader ensures that there is only a single edge entering the loop. diff --git a/suite/synctools/tablegen/include/llvm/IR/Attributes.h b/suite/synctools/tablegen/include/llvm/IR/Attributes.h index 74b60f1e3d..b75917822f 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Attributes.h +++ b/suite/synctools/tablegen/include/llvm/IR/Attributes.h @@ -72,7 +72,7 @@ class Attribute { None, ///< No attributes have been set #define GET_ATTR_ENUM #include "llvm/IR/Attributes.inc" - EndAttrKinds, ///< Sentinal value useful for loops + EndAttrKinds, ///< Sentinel value useful for loops EmptyKey, ///< Use as Empty key for DenseMap of AttrKind TombstoneKey, ///< Use as Tombstone key for DenseMap of AttrKind }; @@ -665,7 +665,7 @@ class AttributeList { return removeAttributesAtIndex(C, ArgNo + FirstArgIndex); } - /// Replace the type contained by attribute \p AttrKind at index \p ArgNo wih + /// Replace the type contained by attribute \p AttrKind at index \p ArgNo with /// \p ReplacementTy, preserving all other attributes. LLVM_NODISCARD AttributeList replaceAttributeTypeAtIndex( LLVMContext &C, unsigned ArgNo, Attribute::AttrKind Kind, diff --git a/suite/synctools/tablegen/include/llvm/IR/CallingConv.h b/suite/synctools/tablegen/include/llvm/IR/CallingConv.h index fd28542465..ece864e731 100644 --- a/suite/synctools/tablegen/include/llvm/IR/CallingConv.h +++ b/suite/synctools/tablegen/include/llvm/IR/CallingConv.h @@ -75,13 +75,13 @@ namespace CallingConv { // CXX_FAST_TLS - Calling convention for access functions. CXX_FAST_TLS = 17, - /// Tail - This calling convention attemps to make calls as fast as + /// Tail - This calling convention attempts to make calls as fast as /// possible while guaranteeing that tail call optimization can always /// be performed. Tail = 18, /// Special calling convention on Windows for calling the Control - /// Guard Check ICall funtion. The function takes exactly one argument + /// Guard Check ICall function. The function takes exactly one argument /// (address of the target function) passed in the first argument register, /// and has no return value. All register values are preserved. CFGuard_Check = 19, diff --git a/suite/synctools/tablegen/include/llvm/IR/Constants.h b/suite/synctools/tablegen/include/llvm/IR/Constants.h index fb884912b3..e23ecd8e4c 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Constants.h +++ b/suite/synctools/tablegen/include/llvm/IR/Constants.h @@ -986,7 +986,7 @@ class ConstantExpr : public Constant { public: // Static methods to construct a ConstantExpr of different kinds. Note that - // these methods may return a object that is not an instance of the + // these methods may return an object that is not an instance of the // ConstantExpr class, because they will attempt to fold the constant // expression into something simpler if possible. diff --git a/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h b/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h index fc461fc3f4..69949b96f7 100644 --- a/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h +++ b/suite/synctools/tablegen/include/llvm/IR/DIBuilder.h @@ -222,7 +222,7 @@ namespace llvm { /// Create debugging information entry for a qualified /// type, e.g. 'const int'. - /// \param Tag Tag identifing type, e.g. dwarf::TAG_volatile_type + /// \param Tag Tag identifying type, e.g. dwarf::TAG_volatile_type /// \param FromTy Base Type. DIDerivedType *createQualifiedType(unsigned Tag, DIType *FromTy); diff --git a/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h b/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h index 9656917906..4dc3d5d2e0 100644 --- a/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h +++ b/suite/synctools/tablegen/include/llvm/IR/DebugInfoMetadata.h @@ -2235,7 +2235,7 @@ DILocation::cloneWithDiscriminator(unsigned Discriminator) const { DIScope *Scope = getScope(); // Skip all parent DILexicalBlockFile that already have a discriminator // assigned. We do not want to have nested DILexicalBlockFiles that have - // mutliple discriminators because only the leaf DILexicalBlockFile's + // multiple discriminators because only the leaf DILexicalBlockFile's // dominator will be used. for (auto *LBF = dyn_cast(Scope); LBF && LBF->getDiscriminator() != 0; diff --git a/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h b/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h index 55e5e59758..5edcc678a3 100644 --- a/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h +++ b/suite/synctools/tablegen/include/llvm/IR/DiagnosticHandler.h @@ -18,8 +18,8 @@ namespace llvm { class DiagnosticInfo; /// This is the base class for diagnostic handling in LLVM. -/// The handleDiagnostics method must be overriden by the subclasses to handle -/// diagnostic. The *RemarkEnabled methods can be overriden to control +/// The handleDiagnostics method must be overridden by the subclasses to handle +/// diagnostic. The *RemarkEnabled methods can be overridden to control /// which remarks are enabled. struct DiagnosticHandler { void *DiagnosticContext = nullptr; diff --git a/suite/synctools/tablegen/include/llvm/IR/Function.h b/suite/synctools/tablegen/include/llvm/IR/Function.h index 90095cd1bc..0eb3910c1b 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Function.h +++ b/suite/synctools/tablegen/include/llvm/IR/Function.h @@ -516,7 +516,7 @@ class LLVM_EXTERNAL_VISIBILITY Function : public GlobalObject, addFnAttr(Attribute::WriteOnly); } - /// Determine if the call can access memmory only using pointers based + /// Determine if the call can access memory only using pointers based /// on its arguments. bool onlyAccessesArgMemory() const { return hasFnAttribute(Attribute::ArgMemOnly); diff --git a/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h b/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h index 4fa8e3a8dc..d42fcf5534 100644 --- a/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h +++ b/suite/synctools/tablegen/include/llvm/IR/GCStrategy.h @@ -121,7 +121,7 @@ class GCStrategy { /// Subclasses of GCStrategy are made available for use during compilation by /// adding them to the global GCRegistry. This can done either within the -/// LLVM source tree or via a loadable plugin. An example registeration +/// LLVM source tree or via a loadable plugin. An example registration /// would be: /// static GCRegistry::Add X("custom-name", /// "my custom supper fancy gc strategy"); diff --git a/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h b/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h index 1818f2a8f3..d7236ca0a2 100644 --- a/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h +++ b/suite/synctools/tablegen/include/llvm/IR/GlobalValue.h @@ -414,7 +414,7 @@ class GlobalValue : public Constant { return !mayBeDerefined(); } - /// Return true if this global has an exact defintion. + /// Return true if this global has an exact definition. bool hasExactDefinition() const { // While this computes exactly the same thing as // isStrongDefinitionForLinker, the intended uses are different. This diff --git a/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h b/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h index e772964fcc..d3123dba6b 100644 --- a/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h +++ b/suite/synctools/tablegen/include/llvm/IR/GlobalVariable.h @@ -180,7 +180,7 @@ class GlobalVariable : public GlobalObject, public ilist_node { /// Attach a DIGlobalVariableExpression. void addDebugInfo(DIGlobalVariableExpression *GV); - /// Fill the vector with all debug info attachements. + /// Fill the vector with all debug info attachments. void getDebugInfo(SmallVectorImpl &GVs) const; /// Add attribute to this global. diff --git a/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h b/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h index a178975996..2968a89527 100644 --- a/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h +++ b/suite/synctools/tablegen/include/llvm/IR/IRBuilder.h @@ -439,7 +439,7 @@ class IRBuilderBase { /// /// Make a new global variable with an initializer that has array of i8 type /// filled in with the null terminated string value specified. The new global - /// variable will be marked mergable with any others of the same contents. If + /// variable will be marked mergeable with any others of the same contents. If /// Name is specified, it is the name of the global variable created. /// /// If no module is given via \p M, it is take from the insertion point basic diff --git a/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h b/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h index 585129904d..359a4e6e4b 100644 --- a/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h +++ b/suite/synctools/tablegen/include/llvm/IR/InstVisitor.h @@ -200,7 +200,7 @@ class InstVisitor { RetTy visitCatchPadInst(CatchPadInst &I) { DELEGATE(FuncletPadInst); } RetTy visitFreezeInst(FreezeInst &I) { DELEGATE(Instruction); } - // Handle the special instrinsic instruction classes. + // Handle the special intrinsic instruction classes. RetTy visitDbgDeclareInst(DbgDeclareInst &I) { DELEGATE(DbgVariableIntrinsic);} RetTy visitDbgValueInst(DbgValueInst &I) { DELEGATE(DbgVariableIntrinsic);} RetTy visitDbgVariableIntrinsic(DbgVariableIntrinsic &I) diff --git a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h index a73285b484..6a1f5c67ed 100644 --- a/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h +++ b/suite/synctools/tablegen/include/llvm/IR/InstrTypes.h @@ -621,7 +621,7 @@ class CastInst : public UnaryInstruction { const Value *Val, ///< The value to cast bool SrcIsSigned, ///< Whether to treat the source as signed Type *Ty, ///< The Type to which the value should be casted - bool DstIsSigned ///< Whether to treate the dest. as signed + bool DstIsSigned ///< Whether to treat the dest. as signed ); /// There are several places where we need to know if a cast instruction @@ -1838,7 +1838,7 @@ class CallBase : public Instruction { } void setOnlyWritesMemory() { addFnAttr(Attribute::WriteOnly); } - /// Determine if the call can access memmory only using pointers based + /// Determine if the call can access memory only using pointers based /// on its arguments. bool onlyAccessesArgMemory() const { return hasFnAttr(Attribute::ArgMemOnly); diff --git a/suite/synctools/tablegen/include/llvm/IR/Instruction.h b/suite/synctools/tablegen/include/llvm/IR/Instruction.h index 1937ffd36f..a5d364f0bc 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Instruction.h +++ b/suite/synctools/tablegen/include/llvm/IR/Instruction.h @@ -55,7 +55,7 @@ class Instruction : public User, using OpaqueField = Bitfield::Element; // Template alias so that all Instruction storing alignment use the same - // definiton. + // definition. // Valid alignments are powers of two from 2^0 to 2^MaxAlignmentExponent = // 2^32. We store them as Log2(Alignment), so we need 6 bits to encode the 33 // possible values. diff --git a/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h b/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h index 2ff48380ac..fea543b795 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h +++ b/suite/synctools/tablegen/include/llvm/IR/Intrinsics.h @@ -236,7 +236,7 @@ namespace Intrinsic { /// This method returns true on error. bool matchIntrinsicVarArg(bool isVarArg, ArrayRef &Infos); - /// Gets the type arguments of an intrinsic call by matching type contraints + /// Gets the type arguments of an intrinsic call by matching type constraints /// specified by the .td file. The overloaded types are pushed into the /// AgTys vector. /// diff --git a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td index c5d266eb57..e709c77ee5 100644 --- a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td +++ b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsAMDGPU.td @@ -976,7 +976,7 @@ def int_amdgcn_buffer_store : AMDGPUBufferStore; // it is const 0. A struct intrinsic with constant 0 index is different to the // corresponding raw intrinsic on gfx9+ because the behavior of bound checking // and swizzling changes depending on whether idxen is set in the instruction. -// These new instrinsics also keep the offset and soffset arguments separate as +// These new intrinsics also keep the offset and soffset arguments separate as // they behave differently in bounds checking and swizzling. class AMDGPURawBufferLoad : Intrinsic < [data_ty], diff --git a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td index a424847575..ab5f6023fa 100644 --- a/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td +++ b/suite/synctools/tablegen/include/llvm/IR/IntrinsicsARM.td @@ -1158,7 +1158,7 @@ defm int_arm_mve_vabav: MVEPredicated< [llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_anyvector_ty, LLVMMatchType<0>], llvm_anyvector_ty>; -// The following 3 instrinsics are MVE vector reductions with two vector +// The following 3 intrinsics are MVE vector reductions with two vector // operands. // The first 3 operands are boolean flags (must be compile-time constants): // * unsigned - the instruction operates on vectors of unsigned values and diff --git a/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h b/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h index 446bcecf1c..4250c94ef5 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h +++ b/suite/synctools/tablegen/include/llvm/IR/LLVMContext.h @@ -233,7 +233,7 @@ class LLVMContext { std::unique_ptr MainRemarkStreamer); /// The "LLVM remark streamer" used by LLVM to serialize remark diagnostics - /// comming from IR and MIR passes. + /// coming from IR and MIR passes. /// /// If it does not exist, diagnostics are not saved in a file but only emitted /// via the diagnostic handler. diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h index b3a4820ba0..70c9e418d7 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManager.h @@ -63,7 +63,7 @@ class PassManager : public PassManagerBase { private: /// PassManagerImpl_New is the actual class. PassManager is just the - /// wraper to publish simple pass manager interface + /// wrapper to publish simple pass manager interface PassManagerImpl *PM; }; diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h index caba0ee223..62351e34ed 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassManagers.h @@ -36,7 +36,7 @@ // derive from another pass manager. // // PassManager and FunctionPassManager are two top-level pass manager that -// represents the external interface of this entire pass manager infrastucture. +// represents the external interface of this entire pass manager infrastructure. // // Important classes : // @@ -276,7 +276,7 @@ class PMTopLevelManager { // all allocated nodes in one fell swoop. SpecificBumpPtrAllocator AUFoldingSetNodeAllocator; - // Maps from a pass to it's associated entry in UniqueAnalysisUsages. Does + // Maps from a pass to its associated entry in UniqueAnalysisUsages. Does // not own the storage associated with either key or value.. DenseMap AnUsageMap; @@ -305,7 +305,7 @@ class PMDataManager { /// Augment AvailableAnalysis by adding analysis made available by pass P. void recordAvailableAnalysis(Pass *P); - /// verifyPreservedAnalysis -- Verify analysis presreved by pass P. + /// verifyPreservedAnalysis -- Verify analysis preserved by pass P. void verifyPreservedAnalysis(Pass *P); /// Remove Analysis that is not preserved by the pass diff --git a/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h b/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h index c33b9fc404..103bfab74c 100644 --- a/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h +++ b/suite/synctools/tablegen/include/llvm/IR/LegacyPassNameParser.h @@ -51,7 +51,7 @@ class PassNameParser : public PassRegistrationListener, enumeratePasses(); } - // ignorablePassImpl - Can be overriden in subclasses to refine the list of + // ignorablePassImpl - Can be overridden in subclasses to refine the list of // which passes we want to include. // virtual bool ignorablePassImpl(const PassInfo *P) const { return false; } diff --git a/suite/synctools/tablegen/include/llvm/IR/Metadata.h b/suite/synctools/tablegen/include/llvm/IR/Metadata.h index 7965884990..eeeeb90550 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Metadata.h +++ b/suite/synctools/tablegen/include/llvm/IR/Metadata.h @@ -169,7 +169,7 @@ inline raw_ostream &operator<<(raw_ostream &OS, const Metadata &MD) { /// Metadata wrapper in the Value hierarchy. /// /// A member of the \a Value hierarchy to represent a reference to metadata. -/// This allows, e.g., instrinsics to have metadata as operands. +/// This allows, e.g., intrinsics to have metadata as operands. /// /// Notably, this is the only thing in either hierarchy that is allowed to /// reference \a LocalAsMetadata. diff --git a/suite/synctools/tablegen/include/llvm/IR/PassManager.h b/suite/synctools/tablegen/include/llvm/IR/PassManager.h index 12f9052a9e..6c5e8f3616 100644 --- a/suite/synctools/tablegen/include/llvm/IR/PassManager.h +++ b/suite/synctools/tablegen/include/llvm/IR/PassManager.h @@ -680,7 +680,7 @@ template class AnalysisManager { /// cyclic dependencies between analysis results. /// /// This returns true if the given analysis's result is invalid. Any - /// dependecies on it will become invalid as a result. + /// dependencies on it will become invalid as a result. template bool invalidate(IRUnitT &IR, const PreservedAnalyses &PA) { using ResultModelT = @@ -944,7 +944,7 @@ class InnerAnalysisManagerProxy Result(Result &&Arg) : InnerAM(std::move(Arg.InnerAM)) { // We have to null out the analysis manager in the moved-from state - // because we are taking ownership of the responsibilty to clear the + // because we are taking ownership of the responsibility to clear the // analysis state. Arg.InnerAM = nullptr; } @@ -962,7 +962,7 @@ class InnerAnalysisManagerProxy Result &operator=(Result &&RHS) { InnerAM = RHS.InnerAM; // We have to null out the analysis manager in the moved-from state - // because we are taking ownership of the responsibilty to clear the + // because we are taking ownership of the responsibility to clear the // analysis state. RHS.InnerAM = nullptr; return *this; diff --git a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h index f55f521681..e2b1fea407 100644 --- a/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h +++ b/suite/synctools/tablegen/include/llvm/IR/PassManagerInternal.h @@ -123,7 +123,7 @@ template struct AnalysisResultConcept { virtual ~AnalysisResultConcept() = default; - /// Method to try and mark a result as invalid. + /// Method to try to mark a result as invalid. /// /// When the outer analysis manager detects a change in some underlying /// unit of the IR, it will call this method on all of the results cached. diff --git a/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h b/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h index 4bb6bb8d4a..dfd61e8fba 100644 --- a/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h +++ b/suite/synctools/tablegen/include/llvm/IR/ProfileSummary.h @@ -83,7 +83,7 @@ class ProfileSummary { /// Return summary information as metadata. Metadata *getMD(LLVMContext &Context, bool AddPartialField = true, bool AddPartialProfileRatioField = true); - /// Construct profile summary from metdata. + /// Construct profile summary from metadata. static ProfileSummary *getFromMD(Metadata *MD); const SummaryEntryVector &getDetailedSummary() { return DetailedSummary; } uint32_t getNumFunctions() const { return NumFunctions; } diff --git a/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h b/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h index 1d6b10d9a7..02c57239e8 100644 --- a/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h +++ b/suite/synctools/tablegen/include/llvm/IR/ReplaceConstant.h @@ -26,7 +26,7 @@ template class SmallPtrSetImpl; /// The given instruction \p I contains given constant expression \p CE as one /// of its operands, possibly nested within constant expression trees. Convert -/// all reachable paths from contant expression operands of \p I to \p CE into +/// all reachable paths from constant expression operands of \p I to \p CE into /// corresponding instructions, insert them before \p I, update operands of \p I /// accordingly, and if required, return all such converted instructions at /// \p Insts. diff --git a/suite/synctools/tablegen/include/llvm/IR/Statepoint.h b/suite/synctools/tablegen/include/llvm/IR/Statepoint.h index da9c732ad8..61f3f748b7 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Statepoint.h +++ b/suite/synctools/tablegen/include/llvm/IR/Statepoint.h @@ -129,7 +129,7 @@ class GCStatepointInst : public CallBase { /// Return the number of arguments to the underlying call. size_t actual_arg_size() const { return getNumCallArgs(); } - /// Return an iterator to the begining of the arguments to the underlying call + /// Return an iterator to the beginning of the arguments to the underlying call const_op_iterator actual_arg_begin() const { assert(CallArgsBeginPos <= (int)arg_size()); return arg_begin() + CallArgsBeginPos; @@ -177,7 +177,7 @@ class GCStatepointInst : public CallBase { return make_range(deopt_begin(), deopt_end()); } - /// Returns an iterator to the begining of the argument range describing gc + /// Returns an iterator to the beginning of the argument range describing gc /// values for the statepoint. const_op_iterator gc_args_begin() const { if (auto Opt = getOperandBundle(LLVMContext::OB_gc_live)) diff --git a/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h b/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h index d7377398b9..229dc73357 100644 --- a/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h +++ b/suite/synctools/tablegen/include/llvm/IR/TrackingMDRef.h @@ -101,7 +101,7 @@ class TrackingMDRef { /// Typed tracking ref. /// -/// Track refererences of a particular type. It's useful to use this for \a +/// Track references of a particular type. It's useful to use this for \a /// MDNode and \a ValueAsMetadata. template class TypedTrackingMDRef { TrackingMDRef Ref; diff --git a/suite/synctools/tablegen/include/llvm/IR/Value.h b/suite/synctools/tablegen/include/llvm/IR/Value.h index fc2ed00d77..bab3149870 100644 --- a/suite/synctools/tablegen/include/llvm/IR/Value.h +++ b/suite/synctools/tablegen/include/llvm/IR/Value.h @@ -242,7 +242,7 @@ class Value { /// /// This is useful when you just want to print 'int %reg126', not the /// instruction that generated it. If you specify a Module for context, then - /// even constanst get pretty-printed; for example, the type of a null + /// even constants get pretty-printed; for example, the type of a null /// pointer is printed symbolically. /// @{ void printAsOperand(raw_ostream &O, bool PrintType = true, @@ -479,8 +479,8 @@ class Value { /// Remove every uses that can safely be removed. /// /// This will remove for example uses in llvm.assume. - /// This should be used when performing want to perform a tranformation but - /// some Droppable uses pervent it. + /// This should be used when performing want to perform a transformation but + /// some Droppable uses prevent it. /// This function optionally takes a filter to only remove some droppable /// uses. void dropDroppableUses(llvm::function_ref ShouldDrop = diff --git a/suite/synctools/tablegen/include/llvm/IR/ValueMap.h b/suite/synctools/tablegen/include/llvm/IR/ValueMap.h index 67f275cc06..fb3f002b00 100644 --- a/suite/synctools/tablegen/include/llvm/IR/ValueMap.h +++ b/suite/synctools/tablegen/include/llvm/IR/ValueMap.h @@ -104,7 +104,7 @@ class ValueMap { : Map(NumInitBuckets), Data() {} explicit ValueMap(const ExtraData &Data, unsigned NumInitBuckets = 64) : Map(NumInitBuckets), Data(Data) {} - // ValueMap can't be copied nor moved, beucase the callbacks store pointer + // ValueMap can't be copied nor moved, because the callbacks store pointer // to it. ValueMap(const ValueMap &) = delete; ValueMap(ValueMap &&) = delete; diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h b/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h index e1f45019b1..4e1d9030f9 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/Coverage/CoverageMapping.h @@ -739,7 +739,7 @@ getLineCoverageStats(const coverage::CoverageData &CD) { return make_range(Begin, End); } -// Coverage mappping data (V2) has the following layout: +// Coverage mapping data (V2) has the following layout: // IPSK_covmap: // [CoverageMapFileHeader] // [ArrayStart] @@ -749,7 +749,7 @@ getLineCoverageStats(const coverage::CoverageData &CD) { // [ArrayEnd] // [Encoded Filenames and Region Mapping Data] // -// Coverage mappping data (V3) has the following layout: +// Coverage mapping data (V3) has the following layout: // IPSK_covmap: // [CoverageMapFileHeader] // [Encoded Filenames] diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h b/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h index a416eb2890..746a7875aa 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/InstrProf.h @@ -102,7 +102,7 @@ inline StringRef getInstrProfNamesVarName() { return "__llvm_prf_nm"; } -/// Return the name of a covarage mapping variable (internal linkage) +/// Return the name of a coverage mapping variable (internal linkage) /// for each instrumented source module. Such variables are allocated /// in the __llvm_covmap section. inline StringRef getCoverageMappingVarName() { @@ -485,7 +485,7 @@ class InstrProfSymtab { /// indicates if this is called from LTO optimization passes. Error create(Module &M, bool InLTO = false); - /// Create InstrProfSymtab from a set of names iteratable from + /// Create InstrProfSymtab from a set of names iterable from /// \p IterRange. This interface is used by IndexedProfReader. template Error create(const NameIterRange &IterRange); @@ -536,7 +536,7 @@ class InstrProfSymtab { inline Function *getFunction(uint64_t FuncMD5Hash); /// Return the function's original assembly name by stripping off - /// the prefix attached (to symbols with priviate linkage). For + /// the prefix attached (to symbols with private linkage). For /// global functions, it returns the same string as getFuncName. inline StringRef getOrigFuncName(uint64_t FuncMD5Hash); @@ -1038,7 +1038,7 @@ struct Summary { uint64_t Cutoff; ///< The required percentile of total execution count. uint64_t MinBlockCount; ///< The minimum execution count for this percentile. - uint64_t NumBlocks; ///< Number of blocks >= the minumum execution count. + uint64_t NumBlocks; ///< Number of blocks >= the minimum execution count. }; // The field kind enumerator to assigned value mapping should remain // unchanged when a new kind is added or an old kind gets deleted in @@ -1061,7 +1061,7 @@ struct Summary { NumKinds = TotalBlockCount + 1 }; - // The number of summmary fields following the summary header. + // The number of summary fields following the summary header. uint64_t NumSummaryFields; // The number of Cutoff Entries (Summary::Entry) following summary fields. uint64_t NumCutoffEntries; diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h index bad2139fe8..50ae26c568 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProf.h @@ -1157,7 +1157,7 @@ template class SampleSorter { SamplesWithLocList V; }; -/// SampleContextTrimmer impelements helper functions to trim, merge cold +/// SampleContextTrimmer implements helper functions to trim, merge cold /// context profiles. It also supports context profile canonicalization to make /// sure ProfileMap's key is consistent with FunctionSample's name/context. class SampleContextTrimmer { @@ -1167,8 +1167,8 @@ class SampleContextTrimmer { // should only be effective when TrimColdContext is true. On top of // TrimColdContext, TrimBaseProfileOnly can be used to specify to trim all // cold profiles or only cold base profiles. Trimming base profiles only is - // mainly to honor the preinliner decsion. Note that when MergeColdContext is - // true, preinliner decsion is not honored anyway so TrimBaseProfileOnly will + // mainly to honor the preinliner decision. Note that when MergeColdContext is + // true, preinliner decision is not honored anyway so TrimBaseProfileOnly will // be ignored. void trimAndMergeColdContextProfiles(uint64_t ColdCountThreshold, bool TrimColdContext, diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h index a2caca246d..db9ce345c4 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h @@ -167,7 +167,7 @@ // The minimum number of samples required to reach the target // CUTOFF. // NUM_COUNTS (uint64_t) -// Number of samples to get to the desrired percentile. +// Number of samples to get to the desired percentile. // // NAME TABLE // SIZE (uint32_t) @@ -306,7 +306,7 @@ class SampleProfileReaderItaniumRemapper { std::unique_ptr Remappings; // Map remapping key to the name in the profile. By looking up the // key in the remapper, a given new name can be mapped to the - // cannonical name using the NameMap. + // canonical name using the NameMap. DenseMap NameMap; // The Reader the remapper is servicing. SampleProfileReader &Reader; @@ -379,7 +379,7 @@ class SampleProfileReader { return sampleprof_error::success; } - /// The implementaion to read sample profiles from the associated file. + /// The implementation to read sample profiles from the associated file. virtual std::error_code readImpl() = 0; /// Print the profile for \p FContext on stream \p OS. diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h index 42decd2552..b4a2da3a7b 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfWriter.h @@ -277,7 +277,7 @@ class SampleProfileWriterExtBinaryBase : public SampleProfileWriterBinary { std::error_code writeProfileSymbolListSection(); SectionLayout SecLayout = DefaultLayout; - // Specifiy the order of sections in section header table. Note + // Specify the order of sections in section header table. Note // the order of sections in SecHdrTable may be different that the // order in SectionHdrLayout. sample Reader will follow the order // in SectionHdrLayout to read each section. diff --git a/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td b/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td index 4859cf6b57..6416afa3a7 100644 --- a/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td +++ b/suite/synctools/tablegen/include/llvm/Target/GlobalISel/Combine.td @@ -73,7 +73,7 @@ class GIDefKindWithArgs; /// Declare a root node. There must be at least one of these in every combine /// rule. /// TODO: The plan is to elide `root` definitions and determine it from the DAG -/// itself with an overide for situations where the usual determination +/// itself with an override for situations where the usual determination /// is incorrect. def root : GIDefKind; diff --git a/suite/synctools/tablegen/include/llvm/Target/Target.td b/suite/synctools/tablegen/include/llvm/Target/Target.td index 85dabebcb1..21af476254 100644 --- a/suite/synctools/tablegen/include/llvm/Target/Target.td +++ b/suite/synctools/tablegen/include/llvm/Target/Target.td @@ -642,8 +642,8 @@ class Instruction : InstructionEncoding { /// Should generate helper functions that help you to map a logical operand's /// index to the underlying MIOperand's index. - /// In most architectures logical operand indicies are equal to - /// MIOperand indicies, but for some CISC architectures, a logical operand + /// In most architectures logical operand indices are equal to + /// MIOperand indices, but for some CISC architectures, a logical operand /// might be consist of multiple MIOperand (e.g. a logical operand that /// uses complex address mode). bit UseLogicalOperandMappings = false; diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h b/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h index 392ee4334c..ff62907ff9 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetLoweringObjectFile.h @@ -139,7 +139,7 @@ class TargetLoweringObjectFile : public MCObjectFileInfo { const Function &F) const; /// Targets should implement this method to assign a section to globals with - /// an explicit section specfied. The implementation of this method can + /// an explicit section specified. The implementation of this method can /// assume that GO->hasSection() is true. virtual MCSection * getExplicitSectionGlobal(const GlobalObject *GO, SectionKind Kind, diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h b/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h index acfb265a9f..9048d84301 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetMachine.h @@ -153,7 +153,7 @@ class TargetMachine { return nullptr; } - /// Parse out the target's MachineFunctionInfo from the YAML reprsentation. + /// Parse out the target's MachineFunctionInfo from the YAML representation. virtual bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, @@ -439,13 +439,13 @@ class LLVMTargetMachine : public TargetMachine { raw_pwrite_stream &, raw_pwrite_stream *, CodeGenFileType, CGPassBuilderOption, PassInstrumentationCallbacks *) { - return make_error("buildCodeGenPipeline is not overriden", + return make_error("buildCodeGenPipeline is not overridden", inconvertibleErrorCode()); } virtual std::pair getPassNameFromLegacyName(StringRef) { llvm_unreachable( - "getPassNameFromLegacyName parseMIRPipeline is not overriden"); + "getPassNameFromLegacyName parseMIRPipeline is not overridden"); } /// Add passes to the specified pass manager to get machine code emitted with diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h b/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h index a636c48228..19968c83e0 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h @@ -353,7 +353,7 @@ namespace llvm { /// If greater than 0, override TargetLoweringBase::PrefLoopAlignment. unsigned LoopAlignment = 0; - /// FloatABIType - This setting is set by -float-abi=xxx option is specfied + /// FloatABIType - This setting is set by -float-abi=xxx option is specified /// on the command line. This setting may either be Default, Soft, or Hard. /// Default selects the target's default behavior. Soft selects the ABI for /// software floating point, but does not indicate that FP hardware may not diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td b/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td index 3bc467fbbf..b312618fe3 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td +++ b/suite/synctools/tablegen/include/llvm/Target/TargetSchedule.td @@ -67,7 +67,7 @@ def instregex; // coarse grained instruction cost model. Default values for the // properties are defined in MCSchedModel. A value of "-1" in the // target description's SchedMachineModel indicates that the property -// is not overriden by the target. +// is not overridden by the target. // // Target hooks allow subtargets to associate LoadLatency and // HighLatency with groups of opcodes. @@ -491,7 +491,7 @@ class SchedAlias { // // This is what happens for example on AMD processors (at least from Bulldozer // onwards), where AL and AH are not treated as independent from AX, and AX is -// not treated as independent from EAX. A write to AL has an implicity false +// not treated as independent from EAX. A write to AL has an implicitly false // dependency on the last write to EAX (or a portion of EAX). As a consequence, // a write to AL cannot go in parallel with a write to AH. // diff --git a/suite/test_mc.sh b/suite/test_mc.sh index 5430f5f544..b4552aedad 100755 --- a/suite/test_mc.sh +++ b/suite/test_mc.sh @@ -8,7 +8,7 @@ find MC/ -name *.cs | ./test_mc.py -# To test just one architecture, specify the corresponsing dir: +# To test just one architecture, specify the corresponding dir: # $ find MC/X86 -name *.cs | ./test_mc.py # To test just one input file, run test_mc.py with that file: diff --git a/utils.c b/utils.c index c97902e5b6..bd5fcf5612 100644 --- a/utils.c +++ b/utils.c @@ -111,7 +111,7 @@ uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes) /// @brief Appends the string @p src to the string @p str. @p src is put to lower case. /// @param str The string to append to. -/// @param str_size The lengt of @p str +/// @param str_size The length of @p str /// @param src The string to append. void append_to_str_lower(char *str, size_t str_size, const char *src) { char *dest = strchr(str, '\0'); diff --git a/windowsce/COMPILE.md b/windowsce/COMPILE.md index b41dcb7bac..6ed5abc4cd 100644 --- a/windowsce/COMPILE.md +++ b/windowsce/COMPILE.md @@ -10,7 +10,7 @@ We support the following scenario regarding the build machine: - Build running on Microsoft Windows. - The C Software Develepment Kit of the target Windows CE **device** installed. - Only for Windows CE 7: - - C compiler toolchain installed, targetting **Windows Embedded Compact 7** on **ARMv7**. We recommend the toolchain provided with [Windows Embedded Compact 7 toolkit](https://msdn.microsoft.com/en-us/library/jj200349%28v=winembedded.70%29.aspx), as the toolchain originally provided with **Visual Studio 2008** is relatively old. + - C compiler toolchain installed, targeting **Windows Embedded Compact 7** on **ARMv7**. We recommend the toolchain provided with [Windows Embedded Compact 7 toolkit](https://msdn.microsoft.com/en-us/library/jj200349%28v=winembedded.70%29.aspx), as the toolchain originally provided with **Visual Studio 2008** is relatively old. Before building Capstone for Windows CE 7 (respectively, Windows CE 8), the build script `windowsce/make_windowsce7-armv7.bat` (respectively, `windowsce/make_windowsce8-armv7.bat`) needs to be modified. The variables specified in the rest of this section are set in this script file. From 8f9a337dfaad6bddec3fb8dc1cccae17a3736b93 Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Wed, 1 May 2024 04:04:27 +0000 Subject: [PATCH 19/26] Fix clang tidy (#2347) --- .github/workflows/clang-tidy.yml | 11 ++++++++--- run-clang-tidy.sh | 30 ++++++++++++++++++++++++++---- suite/cstest/src/ppc_detail.c | 2 +- 3 files changed, 35 insertions(+), 8 deletions(-) diff --git a/.github/workflows/clang-tidy.yml b/.github/workflows/clang-tidy.yml index 1a814caee0..b06d802ae8 100644 --- a/.github/workflows/clang-tidy.yml +++ b/.github/workflows/clang-tidy.yml @@ -10,9 +10,11 @@ jobs: analyze: runs-on: ubuntu-latest - name: Install clang-tidy + name: clang-tidy steps: - uses: actions/checkout@v3 + with: + fetch-depth: 0 - name: Install clang-tidy run: | sudo apt install clang-tidy @@ -20,10 +22,13 @@ jobs: - name: Build run: | mkdir build && cd build - cmake -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DBUILD_SHARED_LIBS=1 .. - sudo cmake --build . --config Release + CC=clang cmake -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DBUILD_SHARED_LIBS=1 .. + CC=clang sudo cmake --build . --config Release cd .. - name: Check for warnings + env: + base_sha: ${{ github.event.pull_request.base.sha }} + head_sha: ${{ github.event.pull_request.head.sha }} run: | ./run-clang-tidy.sh build diff --git a/run-clang-tidy.sh b/run-clang-tidy.sh index 4617884a00..3abd4f469b 100755 --- a/run-clang-tidy.sh +++ b/run-clang-tidy.sh @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/sh -x if [ $# -ne 1 ] || [ "$1" = "-h" ] || [ "$1" = "--help" ]; then echo "$0 " @@ -7,7 +7,11 @@ fi BUILD_PATH="$1" -clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks=clang-analyzer-*,-clang-analyzer-cplusplus* | tee ct-warnings.txt +clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks=clang-analyzer-*,-clang-analyzer-cplusplus* > ct-warnings.txt +if [ $? -ne 0 ]; then + echo "clang-tidy failed" + exit 1 +fi tmp=$(mktemp) grep ": warning" ct-warnings.txt | grep -oE "^[/a-zA-Z0-9]*\.[ch]" | sort | uniq > $tmp @@ -15,16 +19,34 @@ top_level=$(git rev-parse --show-toplevel) echo "\n\n###### REPORT\n\n" -for modified in $(git diff --name-only origin/next); do +changed_files=$(git diff --name-only $base_sha..$head_sha) +if [ $? -ne 0 ]; then + echo "Failed to get changed files." + exit 1 +fi + +faulty_files="" +for modified in $changed_files; do + files_changed=1 full_path="$top_level/$modified" if grep -q "$full_path" $tmp; then + faulty_files="$faulty_files $modified" echo "$full_path as warnings. Please fix them." needs_fixes=1 fi done +if [ -z $files_changed ]; then + echo "No files changed." + exit 0 +fi + if [ -z $needs_fixes ]; then - echo "All good" + echo "None of the changed files has clang-tidy warnings." exit 0 fi + +echo -e "\n\nclang-tidy warnings for: $faulty_files\n" +echo "Please fix them. Or, if completely unrelated, let us know." + exit 1 diff --git a/suite/cstest/src/ppc_detail.c b/suite/cstest/src/ppc_detail.c index e215cef6b4..53660e50f4 100644 --- a/suite/cstest/src/ppc_detail.c +++ b/suite/cstest/src/ppc_detail.c @@ -78,7 +78,7 @@ char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins) } if (ppc->bc.pred_ctr != PPC_PRED_INVALID) printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr)); - if (ppc->bc.hint != PPC_BH_INVALID) + if (ppc->bc.hint != PPC_BR_NOT_GIVEN) printf("\t\thint: %u\n", ppc->bc.hint); } From f81eb3affaa04a66411af12cf75522cb9649cf83 Mon Sep 17 00:00:00 2001 From: Riccardo Schirone <562321+ret2libc@users.noreply.github.com> Date: Thu, 2 May 2024 19:07:00 +0200 Subject: [PATCH 20/26] Fix pkgconfig file to make #include work (#2307) --- capstone.pc.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/capstone.pc.in b/capstone.pc.in index ed82c3caa4..b8cfebd0c1 100644 --- a/capstone.pc.in +++ b/capstone.pc.in @@ -10,5 +10,5 @@ URL: https://www.capstone-engine.org/ archive=${libdir}/libcapstone.a Libs: -L${libdir} -lcapstone Libs.private: -L${libdir} -l:libcapstone.a -Cflags: -I${includedir}/capstone +Cflags: -I${includedir} -I${includedir}/capstone archs=@CAPSTONE_ARCHITECTURES@ From 9378216492356915b0cd02e8065de3a2219155df Mon Sep 17 00:00:00 2001 From: Chen Date: Wed, 8 May 2024 22:23:23 +0800 Subject: [PATCH 21/26] Rewrite str_replace using snprintf for security and fix clang-tidy (#2350) --- cs.c | 17 +++++++++++------ 1 file changed, 11 insertions(+), 6 deletions(-) diff --git a/cs.c b/cs.c index 65f89b8e5b..e619effcc5 100644 --- a/cs.c +++ b/cs.c @@ -776,18 +776,23 @@ cs_err CAPSTONE_API cs_close(csh *handle) return CS_ERR_OK; } -// replace str1 in target with str2; target starts with str1 -// output is put into result (which is array of char with size CS_MNEMONIC_SIZE) -// return 0 on success, -1 on failure +/// replace str1 in target with str2; target starts with str1 +/// output is put into result (which is array of char with size CS_MNEMONIC_SIZE) +/// return 0 on success, -1 on failure #ifndef CAPSTONE_DIET static int str_replace(char *result, char *target, const char *str1, char *str2) { + size_t target_len = strlen(target); + size_t str1_len = strlen(str1); + if (target_len < str1_len) { + return -1; + } + // only perform replacement if the output fits into result - if (strlen(target) - strlen(str1) + strlen(str2) < CS_MNEMONIC_SIZE - 1) { + if (target_len - str1_len + strlen(str2) <= CS_MNEMONIC_SIZE - 1) { // copy str2 to beginning of result - strcpy(result, str2); // skip str1 - already replaced by str2 - strcat(result, target + strlen(str1)); + snprintf(result, CS_MNEMONIC_SIZE, "%s%s", str2, target + str1_len); return 0; } else From 0002f10c9979f6211eda532625c0c486c1d2df4b Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Wed, 8 May 2024 14:24:01 +0000 Subject: [PATCH 22/26] Clang tidy quality of life (#2348) --- run-clang-tidy.sh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/run-clang-tidy.sh b/run-clang-tidy.sh index 3abd4f469b..662ef949d0 100755 --- a/run-clang-tidy.sh +++ b/run-clang-tidy.sh @@ -1,10 +1,16 @@ -#!/bin/sh -x +#!/bin/sh if [ $# -ne 1 ] || [ "$1" = "-h" ] || [ "$1" = "--help" ]; then echo "$0 " + echo "Set env var 'base_sha' to upstream/next hash and 'head_sha' and your current HEAD hash." exit 1 fi +if [ -z $base_sha ] || [ -z $head_sha ]; then + echo "Set env var 'base_sha' to upstream/next hash and 'head_sha' and your current HEAD hash." + exit 0 +fi + BUILD_PATH="$1" clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks=clang-analyzer-*,-clang-analyzer-cplusplus* > ct-warnings.txt @@ -46,6 +52,8 @@ if [ -z $needs_fixes ]; then exit 0 fi +cat ct-warnings.txt + echo -e "\n\nclang-tidy warnings for: $faulty_files\n" echo "Please fix them. Or, if completely unrelated, let us know." From 1a65b8db9e67a9cfb9b7798b5e001e295d892baa Mon Sep 17 00:00:00 2001 From: Rot127 <45763064+Rot127@users.noreply.github.com> Date: Wed, 8 May 2024 14:25:14 +0000 Subject: [PATCH 23/26] Fix #2244: The offset for pseudo-instr. IDs was incorrectly applied for vcmp. (#2331) --- cs.c | 2 +- suite/cstest/issues.cs | 4 ++++ suite/cstest/src/x86_detail.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/cs.c b/cs.c index e619effcc5..aac3d4c758 100644 --- a/cs.c +++ b/cs.c @@ -1214,7 +1214,7 @@ size_t CAPSTONE_API cs_disasm(csh ud, const uint8_t *buffer, size_t size, uint64 fill_insn(handle, insn_cache, ss.buffer, &mci, handle->post_printer, buffer); // adjust for pseudo opcode (X86) - if (handle->arch == CS_ARCH_X86) + if (handle->arch == CS_ARCH_X86 && insn_cache->id != X86_INS_VCMP) insn_cache->id += mci.popcode_adjust; next_offset = insn_size; diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs index 614470c958..d5da72c21e 100644 --- a/suite/cstest/issues.cs +++ b/suite/cstest/issues.cs @@ -1074,3 +1074,7 @@ !# issue 2079 !# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL 0x0: 0xd1,0x10 == rcl dword ptr [eax] ; operands[1].type: IMM = 0x1 + +!# issue 2244 +!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL +0x0: 0xc5,0xfb,0xc2,0xda,0x06 == vcmpnlesd xmm3, xmm0, xmm2 ; ID: 797 diff --git a/suite/cstest/src/x86_detail.c b/suite/cstest/src/x86_detail.c index f5456877c2..9d02bf7cc1 100644 --- a/suite/cstest/src/x86_detail.c +++ b/suite/cstest/src/x86_detail.c @@ -203,6 +203,7 @@ char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins) x86 = &(ins->detail->x86); + add_str(&result, " ; ID: %" PRIu32 , ins->id); print_string_hex(&result, " ; Prefix:", x86->prefix, 4); print_string_hex(&result, " ; Opcode:", x86->opcode, 4); add_str(&result, " ; rex: 0x%x", x86->rex); From 3b18d7d2a47ac01509b93e555b25cbcc1a60688d Mon Sep 17 00:00:00 2001 From: Snoppy Date: Sun, 12 May 2024 21:16:24 +0800 Subject: [PATCH 24/26] chore: fix typos (#2328) Signed-off-by: snoppy Co-authored-by: Rot127 <45763064+Rot127@users.noreply.github.com> --- suite/synctools/tablegen/include/llvm/Target/TargetOptions.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h b/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h index 19968c83e0..86211abfbc 100644 --- a/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h +++ b/suite/synctools/tablegen/include/llvm/Target/TargetOptions.h @@ -191,7 +191,7 @@ namespace llvm { /// EnableAIXExtendedAltivecABI - This flag returns true when -vec-extabi is /// specified. The code generator is then able to use both volatile and - /// nonvolitle vector registers. When false, the code generator only uses + /// nonvolatile vector registers. When false, the code generator only uses /// volatile vector registers which is the default setting on AIX. unsigned EnableAIXExtendedAltivecABI : 1; From 972bd066bb2ef455459d2837b9c55b31d9b774fc Mon Sep 17 00:00:00 2001 From: RainRat Date: Sun, 12 May 2024 06:17:20 -0700 Subject: [PATCH 25/26] fix typos (#2346) * fix typos * fix typos * fix typos --- ChangeLog | 2 +- MCInst.h | 2 +- MCInstPrinter.h | 2 +- arch/AArch64/AArch64Mapping.c | 6 +++--- arch/TriCore/TriCoreInstPrinter.c | 2 +- arch/XCore/XCoreDisassembler.c | 6 +++--- bindings/python/pyx/ccapstone.pyx | 2 +- bindings/vb6/CX86Inst.cls | 2 +- .../tablegen/include/llvm/CodeGen/TargetInstrInfo.h | 4 ++-- .../tablegen/include/llvm/ProfileData/SampleProfReader.h | 2 +- xcode/README.md | 2 +- 11 files changed, 16 insertions(+), 16 deletions(-) diff --git a/ChangeLog b/ChangeLog index fb4c214bdc..ee4e3fb748 100644 --- a/ChangeLog +++ b/ChangeLog @@ -194,7 +194,7 @@ Improvements: - Fix eflags effects for adc/sbb (#1798) - Update x86 operand access information (#1801) - CI automatically build release tarball (#1802) -- Dont format sstreams when there's nothing to format (#1805) +- Don't format sstreams when there's nothing to format (#1805) - Fix warning about Unused variables (#1815) - Fix insn initialization when instruction have no operands or have a prefix (#1816) - Avoid abort() if x86 not supported (#1818) diff --git a/MCInst.h b/MCInst.h index 08a4f5891d..3c4bd34ad6 100644 --- a/MCInst.h +++ b/MCInst.h @@ -124,7 +124,7 @@ struct MCInst { // operand access index for list of registers sharing the same access right (for ARM) uint8_t ac_idx; uint8_t popcode_adjust; // Pseudo X86 instruction adjust - char assembly[8]; // for special instruction, so that we dont need printer + char assembly[8]; // for special instruction, so that we don't need printer unsigned char evm_data[32]; // for EVM PUSH operand cs_wasm_op wasm_data; // for WASM operand MCRegisterInfo *MRI; diff --git a/MCInstPrinter.h b/MCInstPrinter.h index d8c69fc462..0ccbb3f083 100644 --- a/MCInstPrinter.h +++ b/MCInstPrinter.h @@ -10,7 +10,7 @@ /// Returned by getMnemonic() of the AsmPrinters. typedef struct { - const char *first; // Menmonic + const char *first; // Mnemonic uint64_t second; // Bits } MnemonicBitsInfo; diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c index 2a208e3bda..6db42a21f5 100644 --- a/arch/AArch64/AArch64Mapping.c +++ b/arch/AArch64/AArch64Mapping.c @@ -181,7 +181,7 @@ void AArch64_add_vas(MCInst *MI, const SStream *OS) { } vl |= (num << 8); - // Determine op index by searching for trainling commata after op string + // Determine op index by searching for trailing commata after op string uint32_t op_idx = 0; const char *comma_ptr = strchr(OS->buffer, ',');; while (comma_ptr && comma_ptr < vl_ptr) { @@ -1084,7 +1084,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group, const char *Dot = strstr(RegName, "."); AArch64Layout_VectorLayout vas = AArch64Layout_Invalid; if (!Dot) { - // The matrix dimensions are machine dependendent. + // The matrix dimensions are machine dependent. // Currently we do not support differentiation of machines. // So we just indicate the use of the complete matrix. vas = sme_reg_to_vas(MCInst_getOpVal(MI, OpNum)); @@ -1353,7 +1353,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group, const char *Dot = strstr(RegName, "."); AArch64Layout_VectorLayout vas = AArch64Layout_Invalid; if (!Dot) { - // The matrix dimensions are machine dependendent. + // The matrix dimensions are machine dependent. // Currently we do not support differentiation of machines. // So we just indicate the use of the complete matrix. vas = sme_reg_to_vas(MCInst_getOpVal(MI, OpNum)); diff --git a/arch/TriCore/TriCoreInstPrinter.c b/arch/TriCore/TriCoreInstPrinter.c index c205adf924..342ee89563 100644 --- a/arch/TriCore/TriCoreInstPrinter.c +++ b/arch/TriCore/TriCoreInstPrinter.c @@ -460,7 +460,7 @@ static void printOExtImm_4(MCInst *MI, int OpNum, SStream *O) /// Returned by getMnemonic() of the AsmPrinters. typedef struct { - const char *first; // Menmonic + const char *first; // Mnemonic uint64_t second; // Bits } MnemonicBitsInfo; diff --git a/arch/XCore/XCoreDisassembler.c b/arch/XCore/XCoreDisassembler.c index c095240a5b..a2849c739c 100644 --- a/arch/XCore/XCoreDisassembler.c +++ b/arch/XCore/XCoreDisassembler.c @@ -238,7 +238,7 @@ static DecodeStatus Decode3OpInstruction(unsigned Insn, static DecodeStatus Decode2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - // Try and decode as a 3R instruction. + // Try to decode as a 3R instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 11, 5); switch (Opcode) { case 0x0: @@ -409,7 +409,7 @@ static DecodeStatus DecodeRUSSrcDstBitpInstruction(MCInst *Inst, unsigned Insn, static DecodeStatus DecodeL2OpInstructionFail(MCInst *Inst, unsigned Insn, uint64_t Address, const void *Decoder) { - // Try and decode as a L3R / L2RUS instruction. + // Try to decode as a L3R / L2RUS instruction. unsigned Opcode = fieldFromInstruction_4(Insn, 16, 4) | fieldFromInstruction_4(Insn, 27, 5) << 4; switch (Opcode) { @@ -650,7 +650,7 @@ static DecodeStatus DecodeL5RInstructionFail(MCInst *Inst, unsigned Insn, uint64 { unsigned Opcode; - // Try and decode as a L6R instruction. + // Try to decode as a L6R instruction. MCInst_clear(Inst); Opcode = fieldFromInstruction_4(Insn, 27, 5); switch (Opcode) { diff --git a/bindings/python/pyx/ccapstone.pyx b/bindings/python/pyx/ccapstone.pyx index efdc8561ac..d1a9aceb07 100644 --- a/bindings/python/pyx/ccapstone.pyx +++ b/bindings/python/pyx/ccapstone.pyx @@ -335,7 +335,7 @@ cdef class Cs(object): # unlike disasm(), disasm_lite() only return tuples of (address, size, mnemonic, op_str), # rather than CsInsn objects. def disasm_lite(self, code, addr, count=0): - # TODO: dont need detail, so we might turn off detail, then turn on again when done + # TODO: don't need detail, so we might turn off detail, then turn on again when done cdef cc.cs_insn *allinsn if _diet: diff --git a/bindings/vb6/CX86Inst.cls b/bindings/vb6/CX86Inst.cls index 70e62258d4..f3a2229ae3 100644 --- a/bindings/vb6/CX86Inst.cls +++ b/bindings/vb6/CX86Inst.cls @@ -183,7 +183,7 @@ Friend Sub LoadDetails(lpStruct As Long, parent As CDisassembler) m_prefix = cs.prefix m_opcode = cs.opcode - ptr = lpStruct + LenB(cs) 'we dont include the operands in our vb struct.. + ptr = lpStruct + LenB(cs) 'we don't include the operands in our vb struct.. For i = 1 To cs.op_count Set o = New CX86Operand o.LoadDetails ptr, hEngine diff --git a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h index b937f2f284..c46328fdec 100644 --- a/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h +++ b/suite/synctools/tablegen/include/llvm/CodeGen/TargetInstrInfo.h @@ -981,7 +981,7 @@ class TargetInstrInfo : public MCInstrInfo { protected: /// Target-dependent implementation for IsCopyInstr. - /// If the specific machine instruction is a instruction that moves/copies + /// If the specific machine instruction is an instruction that moves/copies /// value from one register to another register return destination and source /// registers as machine operands. virtual Optional @@ -1001,7 +1001,7 @@ class TargetInstrInfo : public MCInstrInfo { } public: - /// If the specific machine instruction is a instruction that moves/copies + /// If the specific machine instruction is an instruction that moves/copies /// value from one register to another register return destination and source /// registers as machine operands. /// For COPY-instruction the method naturally returns destination and source diff --git a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h index db9ce345c4..959754bad4 100644 --- a/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h +++ b/suite/synctools/tablegen/include/llvm/ProfileData/SampleProfReader.h @@ -129,7 +129,7 @@ // a. CFG Checksum (a.k.a. function hash): // !CFGChecksum: 12345 // b. CFG Checksum (see ContextAttributeMask): -// !Atribute: 1 +// !Attribute: 1 // // // Binary format diff --git a/xcode/README.md b/xcode/README.md index 7f21900eab..64b44d77b7 100644 --- a/xcode/README.md +++ b/xcode/README.md @@ -1,7 +1,7 @@ Xcode Project for Capstone ================================================================================ -The *Capstone.xcodeproj* project is an Xcode project that mimicks the Visual +The *Capstone.xcodeproj* project is an Xcode project that mimics the Visual Studio solution for Capstone. It embeds nicely into Xcode workspaces. It has 13 targets, two of which are the most likely to be of interest: From 2ef45f2a739df0126e5a4f45d0b863aa66989998 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Florian=20M=C3=A4rkl?= Date: Sun, 12 May 2024 15:19:11 +0200 Subject: [PATCH 26/26] Replace non-standard 0b(...) literals (#2314) Despite being widely implemented and part of C++, the 0b prefix is not part of any C standard and will be rejected by some compilers such as Apple GCC 4.0.1 (5493). --- arch/AArch64/AArch64Disassembler.c | 8 +++---- arch/PowerPC/PPCMapping.c | 8 +++---- bindings/python/capstone/arm_const.py | 30 +++++++++++++-------------- bindings/python/capstone/ppc_const.py | 20 +++++++++--------- include/capstone/arm.h | 30 +++++++++++++-------------- include/capstone/ppc.h | 20 +++++++++--------- 6 files changed, 58 insertions(+), 58 deletions(-) diff --git a/arch/AArch64/AArch64Disassembler.c b/arch/AArch64/AArch64Disassembler.c index 1f5ff17a4b..31248c1ef8 100644 --- a/arch/AArch64/AArch64Disassembler.c +++ b/arch/AArch64/AArch64Disassembler.c @@ -1871,9 +1871,9 @@ static DecodeStatus DecodeUnconditionalBranch(MCInst *Inst, uint32_t insn, static bool isInvalidPState(uint64_t Op1, uint64_t Op2) { - return Op1 == 0b000 && (Op2 == 0b000 || // CFINV - Op2 == 0b001 || // XAFlag - Op2 == 0b010); // AXFlag + return Op1 == 0 && (Op2 == 0 || // CFINV + Op2 == 1 || // XAFlag + Op2 == 2); // AXFlag } static DecodeStatus DecodeSystemPStateImm0_15Instruction(MCInst *Inst, @@ -1988,7 +1988,7 @@ static DecodeStatus DecodeSyspXzrInstruction(MCInst *Inst, uint32_t insn, unsigned CRm = fieldFromInstruction_4(insn, 8, 4); unsigned op2 = fieldFromInstruction_4(insn, 5, 3); unsigned Rt = fieldFromInstruction_4(insn, 0, 5); - if (Rt != 0b11111) + if (Rt != 0x1f) return Fail; MCOperand_CreateImm0(Inst, (op1)); diff --git a/arch/PowerPC/PPCMapping.c b/arch/PowerPC/PPCMapping.c index f3e4503f73..2d11674389 100644 --- a/arch/PowerPC/PPCMapping.c +++ b/arch/PowerPC/PPCMapping.c @@ -171,18 +171,18 @@ static void PPC_add_branch_predicates(MCInst *MI, const uint8_t *Bytes, switch (bh) { default: assert(0 && "Invalid BH value."); - case 0b00: + case 0: PPC_get_detail(MI)->bc.bh = cond ? PPC_BH_NO_SUBROUTINE_RET : PPC_BH_SUBROUTINE_RET; break; - case 0b01: + case 1: PPC_get_detail(MI)->bc.bh = cond ? PPC_BH_RESERVED : PPC_BH_NO_SUBROUTINE_RET; break; - case 0b10: + case 2: PPC_get_detail(MI)->bc.bh = PPC_BH_RESERVED; break; - case 0b11: + case 3: PPC_get_detail(MI)->bc.bh = PPC_BH_NOT_PREDICTABLE; break; } diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py index df4f119e97..3e9d868566 100644 --- a/bindings/python/capstone/arm_const.py +++ b/bindings/python/capstone/arm_const.py @@ -21,21 +21,21 @@ ARMVCC_None = 0 ARMVCC_Then = 1 ARMVCC_Else = 2 -ARM_T = 0b1000 -ARM_TT = 0b0100 -ARM_TE = 0b1100 -ARM_TTT = 0b0010 -ARM_TTE = 0b0110 -ARM_TEE = 0b1110 -ARM_TET = 0b1010 -ARM_TTTT = 0b0001 -ARM_TTTE = 0b0011 -ARM_TTEE = 0b0111 -ARM_TTET = 0b0101 -ARM_TEEE = 0b1111 -ARM_TEET = 0b1101 -ARM_TETT = 0b1001 -ARM_TETE = 0b1011 +ARM_T = 0x8 +ARM_TT = 0x4 +ARM_TE = 0xc +ARM_TTT = 0x2 +ARM_TTE = 0x6 +ARM_TEE = 0xe +ARM_TET = 0xa +ARM_TTTT = 0x1 +ARM_TTTE = 0x3 +ARM_TTEE = 0x7 +ARM_TTET = 0x5 +ARM_TEEE = 0xf +ARM_TEET = 0xd +ARM_TETT = 0x9 +ARM_TETE = 0xb ARM_SFT_INVALID = 0 ARM_SFT_ASR = 1 diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py index f74a693e44..48676de4e2 100644 --- a/bindings/python/capstone/ppc_const.py +++ b/bindings/python/capstone/ppc_const.py @@ -52,16 +52,16 @@ PPC_BI_Z = 2 PPC_BI_SO = 3 PPC_BI_INVALID = 0xff -PPC_BO_TEST_CR = 0b10000 -PPC_BO_CR_CMP = 0b01000 -PPC_BO_DECR_CTR = 0b00100 -PPC_BO_CTR_CMP = 0b00010 -PPC_BO_T = 0b00001 -PPC_BR_NOT_GIVEN = 0b00 -PPC_BR_RESERVED = 0b01 -PPC_BR_NOT_TAKEN = 0b10 -PPC_BR_TAKEN = 0b11 -PPC_BR_HINT_MASK = 0b11 +PPC_BO_TEST_CR = (1<<4) +PPC_BO_CR_CMP = (1<<3) +PPC_BO_DECR_CTR = (1<<2) +PPC_BO_CTR_CMP = (1<<1) +PPC_BO_T = 1 +PPC_BR_NOT_GIVEN = 0x0 +PPC_BR_RESERVED = 0x1 +PPC_BR_NOT_TAKEN = 0x2 +PPC_BR_TAKEN = 0x3 +PPC_BR_HINT_MASK = 0x3 PPC_BH_INVALID = 0 PPC_BH_SUBROUTINE_RET = 1 diff --git a/include/capstone/arm.h b/include/capstone/arm.h index dfc69944cf..1fc608eb0b 100644 --- a/include/capstone/arm.h +++ b/include/capstone/arm.h @@ -125,21 +125,21 @@ typedef enum VPTCodes { /// Txy = xy10 /// Txyz = xyz1 typedef enum PredBlockMask { - ARM_T = 0b1000, - ARM_TT = 0b0100, - ARM_TE = 0b1100, - ARM_TTT = 0b0010, - ARM_TTE = 0b0110, - ARM_TEE = 0b1110, - ARM_TET = 0b1010, - ARM_TTTT = 0b0001, - ARM_TTTE = 0b0011, - ARM_TTEE = 0b0111, - ARM_TTET = 0b0101, - ARM_TEEE = 0b1111, - ARM_TEET = 0b1101, - ARM_TETT = 0b1001, - ARM_TETE = 0b1011 + ARM_T = 0x8, // 0b1000 + ARM_TT = 0x4, // 0b0100 + ARM_TE = 0xc, // 0b1100 + ARM_TTT = 0x2, // 0b0010 + ARM_TTE = 0x6, // 0b0110 + ARM_TEE = 0xe, // 0b1110 + ARM_TET = 0xa, // 0b1010 + ARM_TTTT = 0x1, // 0b0001 + ARM_TTTE = 0x3, // 0b0011 + ARM_TTEE = 0x7, // 0b0111 + ARM_TTET = 0x5, // 0b0101 + ARM_TEEE = 0xf, // 0b1111 + ARM_TEET = 0xd, // 0b1101 + ARM_TETT = 0x9, // 0b1001 + ARM_TETE = 0xb, // 0b1011 } ARM_PredBlockMask; // Expands a PredBlockMask by adding an E or a T at the end, depending on Kind. diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h index b38c4eee97..820dc06a1a 100644 --- a/include/capstone/ppc.h +++ b/include/capstone/ppc.h @@ -124,11 +124,11 @@ typedef enum { /// Masks of flags in the BO field. typedef enum { - PPC_BO_TEST_CR = 0b10000, ///< Flag mask: Test CR bit. - PPC_BO_CR_CMP = 0b01000, ///< Flag mask: Compare CR bit to 0 or 1. - PPC_BO_DECR_CTR = 0b00100, ///< Flag mask: Decrement counter. - PPC_BO_CTR_CMP = 0b00010, ///< Flag mask: Compare CTR to 0 or 1. - PPC_BO_T = 0b00001, ///< Either ignored (z) or hint bit t + PPC_BO_TEST_CR = (1 << 4), ///< Flag mask: Test CR bit. + PPC_BO_CR_CMP = (1 << 3), ///< Flag mask: Compare CR bit to 0 or 1. + PPC_BO_DECR_CTR = (1 << 2), ///< Flag mask: Decrement counter. + PPC_BO_CTR_CMP = (1 << 1), ///< Flag mask: Compare CTR to 0 or 1. + PPC_BO_T = 1, ///< Either ignored (z) or hint bit t } ppc_bo_mask; /// Bit for branch taken (plus) or not-taken (minus) hint @@ -136,11 +136,11 @@ typedef enum { /// Bit: | 0 | 1 | /// Name: | a | t | typedef enum { - PPC_BR_NOT_GIVEN = 0b00, - PPC_BR_RESERVED = 0b01, - PPC_BR_NOT_TAKEN = 0b10, ///< Minus - PPC_BR_TAKEN = 0b11, ///< Plus - PPC_BR_HINT_MASK = 0b11, + PPC_BR_NOT_GIVEN = 0x0, + PPC_BR_RESERVED = 0x1, + PPC_BR_NOT_TAKEN = 0x2, ///< Minus + PPC_BR_TAKEN = 0x3, ///< Plus + PPC_BR_HINT_MASK = 0x3, } ppc_br_hint; /// Encodes the different meanings of the BH field.