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Setting the ROB size config parameter to a low value (usually 4 or less, but could be much higher) while micro-operations are enabled can cause the simulation to not progress. This leads to a memory leak, but is not caused by one.
This is a highly unlikely case for a realistic CPU design, hence not finding this until now.
The issue occurs when we have an instruction with more micro-operations than we have space in the ROB. A solution to this would be to halt and provide a useful error when we detect an instruction has more micro-operations than the ROB size, stating that the chosen architecture can not support the micro-operation setup.
The text was updated successfully, but these errors were encountered:
Setting the ROB size config parameter to a low value (usually 4 or less, but could be much higher) while micro-operations are enabled can cause the simulation to not progress. This leads to a memory leak, but is not caused by one.
This is a highly unlikely case for a realistic CPU design, hence not finding this until now.
The issue occurs when we have an instruction with more micro-operations than we have space in the ROB. A solution to this would be to halt and provide a useful error when we detect an instruction has more micro-operations than the ROB size, stating that the chosen architecture can not support the micro-operation setup.
The text was updated successfully, but these errors were encountered: