Payload handoff: PCI root bridge, redundant + not general enough

[ArthurHeymans]

https://universalscalablefirmware.github.io/documentation/2_universal_payload.html#pci-root-bridges

This section talks about handing of information about PCI root bridge and what resources (IO & MEM) it is decoding.

It has the following issues:

1. There is a complete overlap with ACPI on this information.
2. It does not accurately represent PCI root bridges. On AMD hardware more than one, non-continuous range above and below 4G can decode memory. I haven't really checked to be sure but I vaguely remember that xeon_sp hardware can actually do the same but is typically not configured that way (or FSP at least never does that). Even on client hardware you have the flexibility to put for instance PCI memory below and above the MMCONF space.