From f63921c4b5c1a64dad46b88aa671f561886b0b9a Mon Sep 17 00:00:00 2001 From: TinyTapeoutBot <139130078+TinyTapeoutBot@users.noreply.github.com> Date: Sun, 10 Nov 2024 19:35:30 +0200 Subject: [PATCH] feat: update project tt_um_alf19185_ALU from alf19185/TT09-ALU Commit: abde9d435b8aeaeff40794bfd8309368b26d1dae Workflow: https://github.com/alf19185/TT09-ALU/actions/runs/11767049416 --- projects/tt_um_alf19185_ALU/commit_id.json | 6 ++--- projects/tt_um_alf19185_ALU/docs/info.md | 22 +++++++++++------- projects/tt_um_alf19185_ALU/info.yaml | 14 +++++------ projects/tt_um_alf19185_ALU/stats/metrics.csv | 2 +- .../tt_um_alf19185_ALU/tt_um_alf19185_ALU.gds | Bin 1129450 -> 1129450 bytes 5 files changed, 24 insertions(+), 20 deletions(-) diff --git a/projects/tt_um_alf19185_ALU/commit_id.json b/projects/tt_um_alf19185_ALU/commit_id.json index 3512c8ea..a9c04d91 100644 --- a/projects/tt_um_alf19185_ALU/commit_id.json +++ b/projects/tt_um_alf19185_ALU/commit_id.json @@ -1,8 +1,8 @@ { - "app": "Tiny Tapeout tt09 b176ed7c", + "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/alf19185/TT09-ALU", - "commit": "d122a56b5bc7c024a8f6a8c9f5ae8025c10ec137", - "workflow_url": "https://github.com/alf19185/TT09-ALU/actions/runs/11648943287", + "commit": "abde9d435b8aeaeff40794bfd8309368b26d1dae", + "workflow_url": "https://github.com/alf19185/TT09-ALU/actions/runs/11767049416", "sort_id": 1730613446440, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_alf19185_ALU/docs/info.md b/projects/tt_um_alf19185_ALU/docs/info.md index 42ad2218..8a5be8f8 100644 --- a/projects/tt_um_alf19185_ALU/docs/info.md +++ b/projects/tt_um_alf19185_ALU/docs/info.md @@ -1,18 +1,22 @@ - +The 4-bit ALU (Arithmetic Logic Unit) is designed to perform a range of arithmetic and logical operations on two 4-bit inputs, A and B. The operation is determined by a 3-bit control signal, Opcode, which specifies the function to execute, such as addition, subtraction, multiplication, division, and bitwise operations (AND, OR, NOT, XOR). -## How it works +When an arithmetic operation like addition is selected, the ALU outputs an 8-bit result, ALU_Result, to accommodate larger sums or products, and it sets a Carry flag if there’s an overflow. For logical operations like AND or OR, the ALU applies the operation bit-by-bit between A and B. The Zero flag is activated when the result is zero, providing a useful condition for further logic. This flexibility allows the ALU to handle various computational tasks, making it a crucial part of digital systems that require multi-functional data processing. -The 4 bit ALU (Arithmetic Logic Unit) has 2 inputs of 4 bits for each operand, 1 input of 3 bits to select the operational mode, 1 output of 8 bits with the result of the selected operation and 2 outputs of 1 bit each to identify an overflow or zero. +## How to test? -To test the design, the opcode was configured for addition (000), substraction (001), multiplication (010), division (011) and for zero (100). +To test the design, the operation codes are: +- Addition (000) +- Substraction (001) +- Multiplication (010) +- Division (011) +- Logic AND (100) +- Logic OR (101) +- Logic NOT (110) +- Logic XOR (111) diff --git a/projects/tt_um_alf19185_ALU/info.yaml b/projects/tt_um_alf19185_ALU/info.yaml index 1220f419..b2cfde7e 100644 --- a/projects/tt_um_alf19185_ALU/info.yaml +++ b/projects/tt_um_alf19185_ALU/info.yaml @@ -3,7 +3,7 @@ project: title: "4 bit ALU " # Project title author: "Gabriela Alfaro" # Your name discord: "N/A" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) - description: "A simple design of an Arithmetic Logic Unit capable of basic operations: addition, substraction , multiplication and division." # One line description of what your project does + description: "A simple design of an Arithmetic Logic Unit capable of basic operations: addition, substraction , multiplication, division and some logic operations." # One line description of what your project does language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) @@ -36,14 +36,14 @@ pinout: uo[1]: "ALU_Out[1]" uo[2]: "ALU_Out[2]" uo[3]: "ALU_Out[3]" - uo[4]: "ZeroFlag" - uo[5]: "CarryOut" - uo[6]: "" - uo[7]: "" + uo[4]: "ALU_Out[4]" + uo[5]: "ALU_Out[5]" + uo[6]: "ALU_Out[6]" + uo[7]: "ALU_Out[7]" # Bidirectional pins - uio[0]: "" - uio[1]: "" + uio[0]: "ZeroFlag" + uio[1]: "CarryOut" uio[2]: "" uio[3]: "" uio[4]: "" diff --git a/projects/tt_um_alf19185_ALU/stats/metrics.csv b/projects/tt_um_alf19185_ALU/stats/metrics.csv index f666845a..0f51944d 100644 --- a/projects/tt_um_alf19185_ALU/stats/metrics.csv +++ b/projects/tt_um_alf19185_ALU/stats/metrics.csv @@ -92,8 +92,8 @@ design__instance__count__macros,0 design__instance__area__macros,0 design__instance__utilization,0.10044 design__instance__utilization__stdcell,0.10044 -design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count__net:VPWR,0 +design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count,0 timing__drv__floating__nets,0 timing__drv__floating__pins,0 diff --git a/projects/tt_um_alf19185_ALU/tt_um_alf19185_ALU.gds b/projects/tt_um_alf19185_ALU/tt_um_alf19185_ALU.gds index e876657b04fb0a7b46bcdf4dd474895e4ecd2203..cd3a02372a3c1ded755f27478844b325eda3c9f9 100644 GIT binary patch delta 1475 zcmZ8hTWm~G6rKAx_ufv;bf!9Y?sVE3r35LHh(uBpl@N`LSI{4iplMXJ5k!3;f+j*3 z6OKnEg78yPj@ThVgft$d9@T~r^Fbs;+8`<-seNzVb8h;vKhDZNYwx|*KIcpSoG<-z zj>P?bU)Y!LQ+%dO!;Qx9^we=2D$(e@sanz1=5s;)e;P~Xt@68vOfoM*Q#G2wSS+jZ zYo!{UHAPFX+a-0HCpFIImOb#^jkEIP=wY6W2(4_;4YqaKYT`lTtbf*pfD6#w2Z>3q zFkNSNQym3fxRAB3D~`Abd*0L>a}PAzE5%t;W`3TFWS%#fEPIX&cLCaWRI-?Q<2`4v zFPU_A8cE!p8o*$gkS$bmwDT&ybE{2>PX)aZzWNV$s#F zbpl_@q#aQgx39pS>C!jLMQGnHB?^a@N!_B7JqPS-ln(H|!Q3mo;>`h0akbFP5QqDh zrL4u>Db(nT-+BSuYnN7rc%nTMOz)9ecy+*1oy9x>d$HhIKwh3NpreurvlH@?A}@Km z%CG>Y$*1^awz4K{S}NCYa*B#Y;nPNWyMS!{>C9Y%&{qL@8Lg~VH)m2(kX9z;dV01) z)-#=wL3_I-0^R%N@-Xki;Tm~D4wZWQIK0m=VbLvlgGhAz3|1LBe0U<)iQ(lB6a=auVa01{ z!8aeU*B@d<@Dzvj^Hqy;I-7W^Rz1UOQmh$+<$KjyZYn0l;QeX!xX{39Ki#Ib@T9?s zsvoK=IJxaSD)mwAOYj+NXi(IbguD@cxws!+(Y$nL0LEBkJzsT)iK6B@Tp2?$6F42( z9D_BBNiaObivl>bmXr+P$5u3Wx`njzt^vQ8OWYOblN;D<7*O3t{_^k2S!%jz4+>v@ zn_M%!)tyg6g&AGsjMyCK0sZME4I|xDXbfv7OWad)D5+uS7zRcTh94srV;DvNBZ!fQ L5rR-M{5JO=Ii**d delta 1475 zcmZ8hU2F_d6z=@ond#PUcj?Z~cH6Z|34%>TNQ$BoqLKBN;)M#DMukQY^`K2tnh0TS zxPB@Tgcqb-aYBL!Y5bJ>sWybz2O=TT22l|SXQt-fiHGxWznuG>bH4A~`)OeAr-8W# zV?HH^WyLPX=6DQ*XW&TTG8d!(*gZo8cXJ{_PK{lGCxdHD>Z|$XjbLd zN;Eoqik4tEsx|-(Ihp@#(Y1=uiET%*F#;;kj`QV_@wJGQKwO{X!T2- zz~@qFXT-(rE6_Yc`eL~V?Qc{fu)j*`5tZyYV0XQ=m-h{3i}Zpw2ROy$LN7xM?p~C# z7I&vmqtAZo1#qWBS{3Ap_DnFNS8C(c0ZVli^91b0f+v1?`A`8Jl1!MBke3#D$5>fE*DVp~*&|N~@je``5l7`Vz7RJYH?0y6OY%ZCwWbZHKVY+MXlkcVp0^|o=}en4V?DV?P?oO8l0%| zzPf^w+s>m>@74YUpTUL(MSV`lE8&-m`|uUbPj~rYv_;nQRd<*uYOcej(IhjT)1l2# zShIu#LjQSD0Q=XH_<#J^iUyCjk_)_Rz%S-Jcg6YS{%kP}sB9;{`FG_kHQm&V!q?p- zS4?kp=hIMOW;Z!0Hph8Dzxv4L5pF8fhqPmH_tY9pY8X0(fsu>h!^p!Jg5k#qVB}*2 KA(#xk&if0tz+G+t