From e406cb35846176b1ddc1d6e999b93e719d6e2660 Mon Sep 17 00:00:00 2001 From: TinyTapeoutBot <139130078+TinyTapeoutBot@users.noreply.github.com> Date: Sun, 10 Nov 2024 20:02:04 +0200 Subject: [PATCH] feat: update project tt_um_wokwi_414120201832165377 from Eliana00S/IC Commit: f6f1a1019f98348a1e3ef5c217eadf540cdeddac Workflow: https://github.com/Eliana00S/IC/actions/runs/11767305617 --- .../commit_id.json | 4 +- .../docs/info.md | 4 +- .../tt_um_wokwi_414120201832165377/info.yaml | 16 +- .../stats/metrics.csv | 112 +++--- .../stats/synthesis-stats.txt | 54 +-- .../tt_um_wokwi_414120201832165377.gds | Bin 387704 -> 388460 bytes .../tt_um_wokwi_414120201832165377.lef | 38 +- .../tt_um_wokwi_414120201832165377.v | 328 +++++++++++------- .../wokwi-diagram.json | 72 ++-- 9 files changed, 346 insertions(+), 282 deletions(-) diff --git a/projects/tt_um_wokwi_414120201832165377/commit_id.json b/projects/tt_um_wokwi_414120201832165377/commit_id.json index bb3fb1cc..b1f52fea 100644 --- a/projects/tt_um_wokwi_414120201832165377/commit_id.json +++ b/projects/tt_um_wokwi_414120201832165377/commit_id.json @@ -1,8 +1,8 @@ { "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/Eliana00S/IC", - "commit": "5c117a1c90c1bfffc53dcb146d65fe0303741b61", - "workflow_url": "https://github.com/Eliana00S/IC/actions/runs/11760818152", + "commit": "f6f1a1019f98348a1e3ef5c217eadf540cdeddac", + "workflow_url": "https://github.com/Eliana00S/IC/actions/runs/11767305617", "sort_id": 1731202083305, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_wokwi_414120201832165377/docs/info.md b/projects/tt_um_wokwi_414120201832165377/docs/info.md index 08152e4d..57888e22 100644 --- a/projects/tt_um_wokwi_414120201832165377/docs/info.md +++ b/projects/tt_um_wokwi_414120201832165377/docs/info.md @@ -9,10 +9,10 @@ You can also include images in this folder and reference them in the markdown. E ## How it works -The letter E. +Depending on weather the input is odd or even the green LED will light up for odd and the red for even. ## How to test -Turn all inputs on. +Turn on different outputs to see if they are odd or even with the different LEDs. ## External hardware None diff --git a/projects/tt_um_wokwi_414120201832165377/info.yaml b/projects/tt_um_wokwi_414120201832165377/info.yaml index 256e9cd0..c023c636 100644 --- a/projects/tt_um_wokwi_414120201832165377/info.yaml +++ b/projects/tt_um_wokwi_414120201832165377/info.yaml @@ -1,10 +1,10 @@ # Tiny Tapeout project information (Wokwi project) project: wokwi_id: 414120201832165377 # Set this to the ID of your Wokwi project (the number from the project's URL) - title: "Initial" # Project title + title: "Odd or even" # Project title author: "Eliana" # Your name discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) - description: "e" # One line description of what your project does + description: "odd or even input" # One line description of what your project does language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) @@ -26,12 +26,12 @@ pinout: # Outputs uo[0]: "OUT0" - uo[1]: "OUT1" - uo[2]: "OUT2" - uo[3]: "OUT3" - uo[4]: "OUT4" - uo[5]: "OUT5" - uo[6]: "OUT6" + uo[1]: "" + uo[2]: "" + uo[3]: "" + uo[4]: "" + uo[5]: "" + uo[6]: "" uo[7]: "OUT7" # Bidirectional pins diff --git a/projects/tt_um_wokwi_414120201832165377/stats/metrics.csv b/projects/tt_um_wokwi_414120201832165377/stats/metrics.csv index c4f8438d..78d86a83 100644 --- a/projects/tt_um_wokwi_414120201832165377/stats/metrics.csv +++ b/projects/tt_um_wokwi_414120201832165377/stats/metrics.csv @@ -1,23 +1,23 @@ Metric,Value design__lint_error__count,0 design__lint_timing_construct__count,0 -design__lint_warning__count,2 +design__lint_warning__count,4 design__inferred_latch__count,0 -design__instance__count,253 -design__instance__area,401.635 +design__instance__count,263 +design__instance__area,446.678 design__instance_unmapped__count,0 synthesis__check_error__count,0 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 -power__internal__total,8.74460170052771E-7 -power__switching__total,0.0000027653868528432213 -power__leakage__total,1.3719878566575971E-9 -power__total,0.000003641218881966779 +power__internal__total,7.550403893219482E-7 +power__switching__total,5.862190164407366E-7 +power__leakage__total,1.3054839431703158E-9 +power__total,0.0000013425648148768232 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0 -timing__hold__ws__corner:nom_tt_025C_1v80,7.93361043760663 -timing__setup__ws__corner:nom_tt_025C_1v80,11.44261873197206 +timing__hold__ws__corner:nom_tt_025C_1v80,8.165797158472905 +timing__setup__ws__corner:nom_tt_025C_1v80,11.077431729886284 timing__hold__tns__corner:nom_tt_025C_1v80,0.0 timing__setup__tns__corner:nom_tt_025C_1v80,0.0 timing__hold__wns__corner:nom_tt_025C_1v80,0 @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0 -timing__hold__ws__corner:nom_ss_100C_1v60,8.093013599455281 -timing__setup__ws__corner:nom_ss_100C_1v60,11.188837728576885 +timing__hold__ws__corner:nom_ss_100C_1v60,8.497735200476862 +timing__setup__ws__corner:nom_ss_100C_1v60,10.325319558277773 timing__hold__tns__corner:nom_ss_100C_1v60,0.0 timing__setup__tns__corner:nom_ss_100C_1v60,0.0 timing__hold__wns__corner:nom_ss_100C_1v60,0 @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0 -timing__hold__ws__corner:nom_ff_n40C_1v95,7.869721985713872 -timing__setup__ws__corner:nom_ff_n40C_1v95,11.538793358512452 +timing__hold__ws__corner:nom_ff_n40C_1v95,8.032794212718072 +timing__setup__ws__corner:nom_ff_n40C_1v95,11.332485492992882 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 timing__hold__wns__corner:nom_ff_n40C_1v95,0 @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0 design__max_cap_violation__count,0 clock__skew__worst_hold,0.0 clock__skew__worst_setup,0.0 -timing__hold__ws,7.868489194032462 -timing__setup__ws,11.187646681282382 +timing__hold__ws,8.031381120812364 +timing__setup__ws,10.323029834247029 timing__hold__tns,0.0 timing__setup__tns,0.0 timing__hold__wns,0 @@ -86,12 +86,12 @@ flow__errors__count,0 design__io,45 design__die__area,17954.7 design__core__area,16493.3 -design__instance__count__stdcell,253 -design__instance__area__stdcell,401.635 +design__instance__count__stdcell,263 +design__instance__area__stdcell,446.678 design__instance__count__macros,0 design__instance__area__macros,0 -design__instance__utilization,0.0243514 -design__instance__utilization__stdcell,0.0243514 +design__instance__utilization,0.0270824 +design__instance__utilization__stdcell,0.0270824 design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count__net:VPWR,0 design__power_grid_violation__count,0 @@ -100,40 +100,38 @@ timing__drv__floating__pins,0 design__instance__displacement__total,0 design__instance__displacement__mean,0 design__instance__displacement__max,0 -route__wirelength__estimated,498.961 +route__wirelength__estimated,327.252 design__violations,0 design__instance__count__setup_buffer,0 design__instance__count__hold_buffer,0 antenna__violating__nets,0 antenna__violating__pins,0 route__antenna_violation__count,0 -route__net,47 +route__net,57 route__net__special,2 -route__drc_errors__iter:1,26 -route__wirelength__iter:1,506 -route__drc_errors__iter:2,0 -route__wirelength__iter:2,471 +route__drc_errors__iter:1,0 +route__wirelength__iter:1,294 route__drc_errors,0 -route__wirelength,471 -route__vias,144 -route__vias__singlecut,144 +route__wirelength,294 +route__vias,172 +route__vias__singlecut,172 route__vias__multicut,0 design__disconnected_pin__count,11 design__critical_disconnected_pin__count,0 -route__wirelength__max,50.05 -timing__unannotated_net__count__corner:nom_tt_025C_1v80,31 +route__wirelength__max,63.43 +timing__unannotated_net__count__corner:nom_tt_025C_1v80,47 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 -timing__unannotated_net__count__corner:nom_ss_100C_1v60,31 +timing__unannotated_net__count__corner:nom_ss_100C_1v60,47 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 -timing__unannotated_net__count__corner:nom_ff_n40C_1v95,31 +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,47 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count__corner:min_tt_025C_1v80,0 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0 design__max_cap_violation__count__corner:min_tt_025C_1v80,0 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0 -timing__hold__ws__corner:min_tt_025C_1v80,7.931925563096807 -timing__setup__ws__corner:min_tt_025C_1v80,11.443456284245524 +timing__hold__ws__corner:min_tt_025C_1v80,8.164028795189271 +timing__setup__ws__corner:min_tt_025C_1v80,11.078460240525384 timing__hold__tns__corner:min_tt_025C_1v80,0.0 timing__setup__tns__corner:min_tt_025C_1v80,0.0 timing__hold__wns__corner:min_tt_025C_1v80,0 @@ -144,15 +142,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 timing__setup_vio__count__corner:min_tt_025C_1v80,0 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 -timing__unannotated_net__count__corner:min_tt_025C_1v80,31 +timing__unannotated_net__count__corner:min_tt_025C_1v80,47 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 design__max_slew_violation__count__corner:min_ss_100C_1v60,0 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0 design__max_cap_violation__count__corner:min_ss_100C_1v60,0 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0 -timing__hold__ws__corner:min_ss_100C_1v60,8.088729026637472 -timing__setup__ws__corner:min_ss_100C_1v60,11.190051868510954 +timing__hold__ws__corner:min_ss_100C_1v60,8.495105304101752 +timing__setup__ws__corner:min_ss_100C_1v60,10.326928937619787 timing__hold__tns__corner:min_ss_100C_1v60,0.0 timing__setup__tns__corner:min_ss_100C_1v60,0.0 timing__hold__wns__corner:min_ss_100C_1v60,0 @@ -163,15 +161,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 timing__setup_vio__count__corner:min_ss_100C_1v60,0 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 -timing__unannotated_net__count__corner:min_ss_100C_1v60,31 +timing__unannotated_net__count__corner:min_ss_100C_1v60,47 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0 -timing__hold__ws__corner:min_ff_n40C_1v95,7.868489194032462 -timing__setup__ws__corner:min_ff_n40C_1v95,11.539438176063392 +timing__hold__ws__corner:min_ff_n40C_1v95,8.031381120812364 +timing__setup__ws__corner:min_ff_n40C_1v95,11.333313275303455 timing__hold__tns__corner:min_ff_n40C_1v95,0.0 timing__setup__tns__corner:min_ff_n40C_1v95,0.0 timing__hold__wns__corner:min_ff_n40C_1v95,0 @@ -182,15 +180,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:min_ff_n40C_1v95,31 +timing__unannotated_net__count__corner:min_ff_n40C_1v95,47 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 design__max_slew_violation__count__corner:max_tt_025C_1v80,0 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0 design__max_cap_violation__count__corner:max_tt_025C_1v80,0 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0 -timing__hold__ws__corner:max_tt_025C_1v80,7.934981785125431 -timing__setup__ws__corner:max_tt_025C_1v80,11.441827364977724 +timing__hold__ws__corner:max_tt_025C_1v80,8.167379892461573 +timing__setup__ws__corner:max_tt_025C_1v80,11.075984887199672 timing__hold__tns__corner:max_tt_025C_1v80,0.0 timing__setup__tns__corner:max_tt_025C_1v80,0.0 timing__hold__wns__corner:max_tt_025C_1v80,0 @@ -201,15 +199,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 timing__setup_vio__count__corner:max_tt_025C_1v80,0 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 -timing__unannotated_net__count__corner:max_tt_025C_1v80,31 +timing__unannotated_net__count__corner:max_tt_025C_1v80,47 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 design__max_slew_violation__count__corner:max_ss_100C_1v60,0 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0 design__max_cap_violation__count__corner:max_ss_100C_1v60,0 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0 -timing__hold__ws__corner:max_ss_100C_1v60,8.095231381031995 -timing__setup__ws__corner:max_ss_100C_1v60,11.187646681282382 +timing__hold__ws__corner:max_ss_100C_1v60,8.49999206190515 +timing__setup__ws__corner:max_ss_100C_1v60,10.323029834247029 timing__hold__tns__corner:max_ss_100C_1v60,0.0 timing__setup__tns__corner:max_ss_100C_1v60,0.0 timing__hold__wns__corner:max_ss_100C_1v60,0 @@ -220,15 +218,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 timing__setup_vio__count__corner:max_ss_100C_1v60,0 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 -timing__unannotated_net__count__corner:max_ss_100C_1v60,31 +timing__unannotated_net__count__corner:max_ss_100C_1v60,47 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0 -timing__hold__ws__corner:max_ff_n40C_1v95,7.870815333379444 -timing__setup__ws__corner:max_ff_n40C_1v95,11.53805794676014 +timing__hold__ws__corner:max_ff_n40C_1v95,8.034078518749281 +timing__setup__ws__corner:max_ff_n40C_1v95,11.331384151721306 timing__hold__tns__corner:max_ff_n40C_1v95,0.0 timing__setup__tns__corner:max_ff_n40C_1v95,0.0 timing__hold__wns__corner:max_ff_n40C_1v95,0 @@ -239,19 +237,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:max_ff_n40C_1v95,31 +timing__unannotated_net__count__corner:max_ff_n40C_1v95,47 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count,31 +timing__unannotated_net__count,47 timing__unannotated_net_filtered__count,0 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8 -design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000392941 -design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000395864 -design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,7.01886E-8 -design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000395864 +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000014815 +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000166809 +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,2.58364E-8 +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000166809 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 -ir__drop__avg,6.560000000000000507828913469399179092533813673071563243865966796875E-8 -ir__drop__worst,0.000003929999999999999642165578184194174582444247789680957794189453125 +ir__drop__avg,2.6099999999999998792455939053934466098638722542091272771358489990234375E-8 +ir__drop__worst,0.000001480000000000000017730500227741696761540879379026591777801513671875 magic__drc_error__count,0 magic__illegal_overlap__count,0 design__lvs_device_difference__count,0 diff --git a/projects/tt_um_wokwi_414120201832165377/stats/synthesis-stats.txt b/projects/tt_um_wokwi_414120201832165377/stats/synthesis-stats.txt index 10db2f0e..47c04f79 100644 --- a/projects/tt_um_wokwi_414120201832165377/stats/synthesis-stats.txt +++ b/projects/tt_um_wokwi_414120201832165377/stats/synthesis-stats.txt @@ -1,53 +1,53 @@ 62. Printing statistics. -=== not_cell === +=== or_cell === - Number of wires: 2 - Number of wire bits: 2 - Number of public wires: 2 - Number of public wire bits: 2 + Number of wires: 3 + Number of wire bits: 3 + Number of public wires: 3 + Number of public wire bits: 3 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 1 - sky130_fd_sc_hd__inv_2 1 + sky130_fd_sc_hd__or2_2 1 - Chip area for module '\not_cell': 3.753600 + Chip area for module '\or_cell': 6.256000 === tt_um_wokwi_414120201832165377 === - Number of wires: 10 - Number of wire bits: 45 - Number of public wires: 10 - Number of public wire bits: 45 + Number of wires: 14 + Number of wire bits: 49 + Number of public wires: 14 + Number of public wire bits: 49 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - not_cell 2 - sky130_fd_sc_hd__buf_2 8 - sky130_fd_sc_hd__conb_1 16 + Number of cells: 30 + or_cell 6 + sky130_fd_sc_hd__buf_2 2 + sky130_fd_sc_hd__conb_1 22 - Area for cell type \not_cell is unknown! + Area for cell type \or_cell is unknown! - Chip area for module '\tt_um_wokwi_414120201832165377': 100.096000 + Chip area for module '\tt_um_wokwi_414120201832165377': 92.588800 === design hierarchy === tt_um_wokwi_414120201832165377 1 - not_cell 2 + or_cell 6 - Number of wires: 14 - Number of wire bits: 49 - Number of public wires: 14 - Number of public wire bits: 49 + Number of wires: 32 + Number of wire bits: 67 + Number of public wires: 32 + Number of public wire bits: 67 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - sky130_fd_sc_hd__buf_2 8 - sky130_fd_sc_hd__conb_1 16 - sky130_fd_sc_hd__inv_2 2 + Number of cells: 30 + sky130_fd_sc_hd__buf_2 2 + sky130_fd_sc_hd__conb_1 22 + sky130_fd_sc_hd__or2_2 6 - Chip area for top module '\tt_um_wokwi_414120201832165377': 107.603200 + Chip area for top module '\tt_um_wokwi_414120201832165377': 130.124800 diff --git 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zk8SfQoO49-nUMNqjn*UiQv>}WCa=vpiAhL*t#QN}(dV)~n0K6Nbito(jFj*f0VA4* zRGaQHOPeOC&+i|Rukkk%`_iqa$k2Fgo{z|IXg6kt=p(%#es@Mh4%xS`8`o|M%622v cxyZt=B0Ikok*COh*p2gFt;^e+xT4Gd0y=5KwEzGB diff --git a/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.lef b/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.lef index 17c612ec..0aef020f 100644 --- a/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.lef +++ b/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.lef @@ -74,7 +74,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN ui_in[0] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.213000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 138.310 110.520 138.610 111.520 ; @@ -101,7 +101,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN ui_in[3] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 130.030 110.520 130.330 111.520 ; @@ -110,7 +110,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN ui_in[4] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 127.270 110.520 127.570 111.520 ; @@ -119,7 +119,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN ui_in[5] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 124.510 110.520 124.810 111.520 ; @@ -128,7 +128,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN ui_in[6] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 121.750 110.520 122.050 111.520 ; @@ -137,7 +137,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN ui_in[7] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 118.990 110.520 119.290 111.520 ; @@ -347,7 +347,6 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[1] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.795200 ; PORT LAYER met4 ; RECT 91.390 110.520 91.690 111.520 ; @@ -356,7 +355,6 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[2] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 88.630 110.520 88.930 111.520 ; @@ -365,7 +363,6 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[3] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 85.870 110.520 86.170 111.520 ; @@ -374,7 +371,6 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[4] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 83.110 110.520 83.410 111.520 ; @@ -383,7 +379,6 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[5] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 80.350 110.520 80.650 111.520 ; @@ -392,7 +387,6 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[6] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 77.590 110.520 77.890 111.520 ; @@ -401,7 +395,7 @@ MACRO tt_um_wokwi_414120201832165377 PIN uo_out[7] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; + ANTENNADIFFAREA 0.795200 ; PORT LAYER met4 ; RECT 74.830 110.520 75.130 111.520 ; @@ -413,11 +407,11 @@ MACRO tt_um_wokwi_414120201832165377 LAYER li1 ; RECT 2.760 2.635 158.240 108.885 ; LAYER met1 ; - RECT 2.760 2.480 158.240 109.440 ; + RECT 2.760 2.480 158.240 109.040 ; LAYER met2 ; - RECT 18.310 2.535 139.760 110.685 ; + RECT 18.310 2.535 139.760 111.365 ; LAYER met3 ; - RECT 18.290 2.555 139.780 111.330 ; + RECT 18.290 2.555 139.780 111.345 ; LAYER met4 ; RECT 31.370 110.120 33.030 110.665 ; RECT 34.130 110.120 35.790 110.665 ; @@ -459,12 +453,12 @@ MACRO tt_um_wokwi_414120201832165377 RECT 133.490 110.120 135.150 110.665 ; RECT 136.250 110.120 137.910 110.665 ; RECT 30.655 109.440 138.625 110.120 ; - RECT 30.655 102.855 56.750 109.440 ; - RECT 59.150 102.855 60.050 109.440 ; - RECT 62.450 102.855 95.620 109.440 ; - RECT 98.020 102.855 98.920 109.440 ; - RECT 101.320 102.855 134.490 109.440 ; - RECT 136.890 102.855 137.790 109.440 ; + RECT 30.655 96.055 56.750 109.440 ; + RECT 59.150 96.055 60.050 109.440 ; + RECT 62.450 96.055 95.620 109.440 ; + RECT 98.020 96.055 98.920 109.440 ; + RECT 101.320 96.055 134.490 109.440 ; + RECT 136.890 96.055 137.790 109.440 ; END END tt_um_wokwi_414120201832165377 END LIBRARY diff --git a/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.v b/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.v index 2ce1a33a..214a3e9d 100644 --- a/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.v +++ b/projects/tt_um_wokwi_414120201832165377/tt_um_wokwi_414120201832165377.v @@ -20,165 +20,205 @@ module tt_um_wokwi_414120201832165377 (clk, output [7:0] uo_out; wire net10; + wire net17; + wire net18; + wire net19; + wire net20; wire net9; - wire net4; - wire net5; - wire net6; - wire net7; - wire net8; - wire net11; wire net12; wire net13; wire net14; wire net15; wire net16; - wire net17; - wire net18; - wire net19; - wire net20; + wire net21; + wire net22; + wire net23; + wire net24; + wire net25; + wire net26; + wire net27; + wire net28; + wire net29; + wire net30; + wire net31; + wire net32; + wire net33; + wire net34; + wire net35; + wire net36; wire net1; wire net2; wire net3; + wire net4; + wire net5; + wire net6; + wire net7; + wire net8; + wire net11; - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_4 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_10 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net4)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_5 (.VGND(VGND), + .LO(net12)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_11 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net5)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_6 (.VGND(VGND), + .LO(net13)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_12 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net6)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_7 (.VGND(VGND), + .LO(net14)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_13 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net7)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_8 (.VGND(VGND), + .LO(net15)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_14 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net8)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_9 (.VGND(VGND), + .LO(net16)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_15 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net11)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_10 (.VGND(VGND), + .LO(net21)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_16 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net12)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_11 (.VGND(VGND), + .LO(net22)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_17 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net13)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_12 (.VGND(VGND), + .LO(net23)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_18 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net14)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_13 (.VGND(VGND), + .LO(net24)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_19 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net15)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_14 (.VGND(VGND), + .LO(net25)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_20 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net16)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_15 (.VGND(VGND), + .LO(net26)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_21 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net17)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_16 (.VGND(VGND), + .LO(net27)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_22 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net18)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_17 (.VGND(VGND), + .LO(net28)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_23 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net19)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_18 (.VGND(VGND), + .LO(net29)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_24 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net20)); - sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), - .VGND(VGND), + .LO(net30)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_25 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__clkbuf_4 _16_ (.A(ui_in[0]), - .VGND(VGND), + .VPWR(VPWR), + .LO(net31)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_26 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[0])); - sky130_fd_sc_hd__clkbuf_4 _17_ (.A(net9), - .VGND(VGND), + .LO(net32)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_27 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net33)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_28 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net34)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_29 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net35)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_30 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[1])); - sky130_fd_sc_hd__buf_2 _18_ (.A(net10), + .LO(net36)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__clkbuf_4 _22_ (.A(net9), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[2])); - sky130_fd_sc_hd__buf_2 _19_ (.A(ui_in[3]), + .X(uo_out[0])); + sky130_fd_sc_hd__clkbuf_4 _23_ (.A(net10), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[3])); - sky130_fd_sc_hd__buf_2 _20_ (.A(ui_in[4]), + .X(uo_out[7])); + sky130_fd_sc_hd__or2_1 \or2/_0_ (.A(net18), + .B(net17), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[4])); - sky130_fd_sc_hd__buf_2 _21_ (.A(ui_in[5]), + .X(net10)); + sky130_fd_sc_hd__or2_1 \or4/_0_ (.A(net7), + .B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[5])); - sky130_fd_sc_hd__buf_2 _22_ (.A(ui_in[6]), + .X(net19)); + sky130_fd_sc_hd__or2_1 \or5/_0_ (.A(net3), + .B(net1), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[6])); - sky130_fd_sc_hd__buf_2 _23_ (.A(ui_in[7]), + .X(net20)); + sky130_fd_sc_hd__or2_1 \or6/_0_ (.A(net19), + .B(net20), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[7])); - sky130_fd_sc_hd__inv_2 \not1/_0_ (.A(net1), + .X(net9)); + sky130_fd_sc_hd__or2_1 \or7/_0_ (.A(net8), + .B(net6), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(net9)); - sky130_fd_sc_hd__inv_2 \not2/_0_ (.A(net2), + .X(net18)); + sky130_fd_sc_hd__or2_1 \or8/_0_ (.A(net4), + .B(net2), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(net10)); + .X(net17)); sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_0_Right_0 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -941,23 +981,59 @@ module tt_um_wokwi_414120201832165377 (clk, .VPWR(VPWR)); sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_302 (.VGND(VGND), .VPWR(VPWR)); - sky130_fd_sc_hd__buf_1 input1 (.A(ui_in[1]), + sky130_fd_sc_hd__clkbuf_1 input1 (.A(ui_in[0]), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(net1)); - sky130_fd_sc_hd__buf_1 input2 (.A(ui_in[2]), + sky130_fd_sc_hd__clkbuf_1 input2 (.A(ui_in[1]), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(net2)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_3 (.VGND(VGND), + sky130_fd_sc_hd__clkbuf_1 input3 (.A(ui_in[2]), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net3)); + .X(net3)); + sky130_fd_sc_hd__clkbuf_1 input4 (.A(ui_in[3]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net4)); + sky130_fd_sc_hd__clkbuf_1 input5 (.A(ui_in[4]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net5)); + sky130_fd_sc_hd__clkbuf_1 input6 (.A(ui_in[5]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net6)); + sky130_fd_sc_hd__clkbuf_1 input7 (.A(ui_in[6]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net7)); + sky130_fd_sc_hd__clkbuf_1 input8 (.A(ui_in[7]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net8)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120201832165377_9 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net11)); sky130_ef_sc_hd__decap_12 FILLER_0_0_15 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -6294,19 +6370,15 @@ module tt_um_wokwi_414120201832165377 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_4 FILLER_0_37_205 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_209 (.VGND(VGND), - .VNB(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_37_205 (.VPWR(VPWR), + .VGND(VGND), .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_8 FILLER_0_37_213 (.VGND(VGND), + .VNB(VGND)); + sky130_fd_sc_hd__decap_6 FILLER_0_37_217 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_37_221 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_223 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6318,15 +6390,15 @@ module tt_um_wokwi_414120201832165377 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_249 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_37_249 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_261 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_37_257 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_273 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_37_265 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6446,71 +6518,71 @@ module tt_um_wokwi_414120201832165377 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_38_162 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_162 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_6 FILLER_0_38_181 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_166 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_187 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_172 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_38_192 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_178 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_204 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_184 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_38_213 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_190 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_221 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_225 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_197 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_237 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_209 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_249 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_221 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_253 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_225 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_265 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_237 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_277 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_38_245 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_38_281 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_251 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_286 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_256 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_292 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_279 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_4 FILLER_0_38_304 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_38_298 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_38_306 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6526,20 +6598,26 @@ module tt_um_wokwi_414120201832165377 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - assign uio_oe[0] = net3; - assign uio_oe[1] = net4; - assign uio_oe[2] = net5; - assign uio_oe[3] = net6; - assign uio_oe[4] = net7; - assign uio_oe[5] = net8; - assign uio_oe[6] = net11; - assign uio_oe[7] = net12; - assign uio_out[0] = net13; - assign uio_out[1] = net14; - assign uio_out[2] = net15; - assign uio_out[3] = net16; - assign uio_out[4] = net17; - assign uio_out[5] = net18; - assign uio_out[6] = net19; - assign uio_out[7] = net20; + assign uio_oe[0] = net36; + assign uio_oe[1] = net11; + assign uio_oe[2] = net12; + assign uio_oe[3] = net13; + assign uio_oe[4] = net14; + assign uio_oe[5] = net15; + assign uio_oe[6] = net16; + assign uio_oe[7] = net21; + assign uio_out[0] = net22; + assign uio_out[1] = net23; + assign uio_out[2] = net24; + assign uio_out[3] = net25; + assign uio_out[4] = net26; + assign uio_out[5] = net27; + assign uio_out[6] = net28; + assign uio_out[7] = net29; + assign uo_out[1] = net30; + assign uo_out[2] = net31; + assign uo_out[3] = net32; + assign uo_out[4] = net33; + assign uo_out[5] = net34; + assign uo_out[6] = net35; endmodule diff --git a/projects/tt_um_wokwi_414120201832165377/wokwi-diagram.json b/projects/tt_um_wokwi_414120201832165377/wokwi-diagram.json index 71410c06..71e1cac3 100644 --- a/projects/tt_um_wokwi_414120201832165377/wokwi-diagram.json +++ b/projects/tt_um_wokwi_414120201832165377/wokwi-diagram.json @@ -18,15 +18,8 @@ "left": -115.2, "attrs": { "frequency": "10000" } }, - { "type": "wokwi-gnd", "id": "pwr2", "top": -76.8, "left": 565.8, "attrs": {} }, + { "type": "wokwi-gnd", "id": "pwr2", "top": -96, "left": 594.6, "attrs": {} }, { "type": "wokwi-vcc", "id": "pwr1", "top": -229.64, "left": -115.2, "attrs": {} }, - { - "type": "wokwi-7segment", - "id": "sevseg1", - "top": -196.62, - "left": 533.08, - "attrs": { "common": "cathode" } - }, { "type": "wokwi-slide-switch", "id": "sw2", @@ -136,15 +129,22 @@ "attrs": { "text": "Bidirectional I/O pins" } }, { "type": "wokwi-gate-or-2", "id": "or1", "top": -364.8, "left": -307.2, "attrs": {} }, + { "type": "wokwi-led", "id": "led1", "top": -234, "left": 627.8, "attrs": { "color": "red" } }, { "type": "wokwi-led", - "id": "led1", - "top": -272.4, - "left": 243.8, - "attrs": { "color": "red" } - }, - { "type": "wokwi-gate-not", "id": "not1", "top": -172.8, "left": 144, "attrs": {} }, - { "type": "wokwi-gate-not", "id": "not2", "top": -163.2, "left": 153.6, "attrs": {} } + "id": "led2", + "top": -234, + "left": 589.4, + "attrs": { "color": "green" } + }, + { "type": "wokwi-gnd", "id": "pwr4", "top": -96, "left": 633, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or2", "top": -115.2, "left": 288, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or3", "top": -372.41, "left": 157.42, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or4", "top": -201.6, "left": 182.4, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or5", "top": -249.6, "left": 182.4, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or6", "top": -182.4, "left": 297.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or7", "top": -76.8, "left": 182.4, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or8", "top": -124.8, "left": 182.4, "attrs": {} } ], "connections": [ [ "pwr1:VCC", "sw1:8a", "red", [ "v0" ] ], @@ -155,20 +155,6 @@ [ "pwr1:VCC", "sw1:1a", "red", [ "v0" ] ], [ "pwr1:VCC", "sw1:2a", "red", [ "v0" ] ], [ "pwr1:VCC", "sw1:3a", "red", [ "v0" ] ], - [ "ttout:EXTOUT0", "sevseg1:A", "green", [ "h21.01", "v-28.8", "h96" ] ], - [ "ttout:EXTOUT1", "sevseg1:B", "green", [ "h11.41", "v-48", "h122.99", "v41.34" ] ], - [ - "ttout:EXTOUT2", - "sevseg1:C", - "green", - [ "h30.61", "v-38.4", "h115.2", "v105.6", "h-28.8" ] - ], - [ "ttout:EXTOUT3", "sevseg1:D", "green", [ "h57.6", "v57.6", "h48" ] ], - [ "sevseg1:E", "ttout:EXTOUT4", "green", [ "v9.6", "h-48", "v-38.4" ] ], - [ "ttout:EXTOUT5", "sevseg1:F", "green", [ "h69.01", "v-57.6", "h28.8" ] ], - [ "ttout:EXTOUT6", "sevseg1:G", "green", [ "h78.61", "v-57.6" ] ], - [ "ttout:EXTOUT7", "sevseg1:DP", "green", [ "v28.8", "h136.21" ] ], - [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v0" ] ], [ "sw2:1", "clock1:CLK", "blue", [ "h-19.2", "v-57.6" ] ], [ "sw1:1b", "ttin:EXTIN0", "green", [ "h0" ] ], [ "sw1:2b", "ttin:EXTIN1", "green", [ "h0" ] ], @@ -185,16 +171,24 @@ [ "ttin:EXTRST_N", "btn2:1.r", "orange", [ "h-38.4", "v-96" ] ], [ "btn2:1.l", "r2:2", "green", [ "h0" ] ], [ "pwr5:VCC", "r2:1", "red", [ "v0" ] ], - [ "ttin:IN0", "ttout:OUT0", "green", [ "h0" ] ], - [ "ttin:IN3", "ttout:OUT3", "green", [ "h0" ] ], - [ "ttin:IN4", "ttout:OUT4", "green", [ "h0" ] ], - [ "ttin:IN5", "ttout:OUT5", "green", [ "h0" ] ], - [ "ttin:IN6", "ttout:OUT6", "green", [ "h307.2", "v-9.6" ] ], - [ "ttin:IN7", "ttout:OUT7", "green", [ "h0" ] ], - [ "ttin:IN1", "not1:IN", "green", [ "h0" ] ], - [ "not1:OUT", "ttout:OUT1", "green", [ "v0", "h163.2" ] ], - [ "ttin:IN2", "not2:IN", "green", [ "h0" ] ], - [ "not2:OUT", "ttout:OUT2", "green", [ "v0" ] ] + [ "led2:C", "pwr2:GND", "green", [ "v0" ] ], + [ "led1:C", "pwr4:GND", "green", [ "v0" ] ], + [ "ttout:EXTOUT0", "led2:A", "green", [ "v0", "h115.2" ] ], + [ "ttout:EXTOUT7", "led1:A", "green", [ "h153.6", "v-9.6" ] ], + [ "or2:OUT", "ttout:OUT7", "red", [ "v0" ] ], + [ "or7:OUT", "or2:B", "red", [ "v0", "h9.6" ] ], + [ "or8:OUT", "or2:A", "red", [ "v0" ] ], + [ "ttin:IN7", "or7:B", "red", [ "h9.6", "v48" ] ], + [ "or7:A", "ttin:IN5", "red", [ "h-57.6", "v-48", "h-28.8" ] ], + [ "ttin:IN3", "or8:B", "red", [ "h48", "v38.4", "h38.4" ] ], + [ "or8:A", "ttin:IN1", "red", [ "h-19.2", "v-38.4" ] ], + [ "or6:OUT", "ttout:OUT0", "green", [ "v0" ] ], + [ "or5:OUT", "or6:A", "green", [ "v0", "h19.2" ] ], + [ "or4:OUT", "or6:B", "green", [ "v0", "h9.6", "v28.8" ] ], + [ "ttin:IN0", "or5:A", "green", [ "h9.6", "v-76.8" ] ], + [ "ttin:IN2", "or5:B", "green", [ "h19.2", "v-76.8", "h9.6" ] ], + [ "ttin:IN4", "or4:A", "green", [ "h28.8", "v-67.2", "h9.6" ] ], + [ "ttin:IN6", "or4:B", "green", [ "h57.6", "v-67.2" ] ] ], "dependencies": {} } \ No newline at end of file