diff --git a/projects/tt_um_wokwi_413923150973445121/commit_id.json b/projects/tt_um_wokwi_413923150973445121/commit_id.json
index 342bd84b..e4192124 100644
--- a/projects/tt_um_wokwi_413923150973445121/commit_id.json
+++ b/projects/tt_um_wokwi_413923150973445121/commit_id.json
@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/MarianoMunoz/tt00-wowki-design",
-  "commit": "d0a76e4311028c478f725d4c6854c3f4a047324a",
-  "workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11761518106",
+  "commit": "efb92d8a8ff5def23657bc929f13ac7b45e5dc24",
+  "workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11764430515",
   "sort_id": 1731012978166,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
diff --git a/projects/tt_um_wokwi_413923150973445121/docs/info.md b/projects/tt_um_wokwi_413923150973445121/docs/info.md
index ed39fa1c..96358d57 100644
--- a/projects/tt_um_wokwi_413923150973445121/docs/info.md
+++ b/projects/tt_um_wokwi_413923150973445121/docs/info.md
@@ -9,12 +9,12 @@ You can also include images in this folder and reference them in the markdown. E
 
 ## How it works
 
-Logic test
+Binary counter using flip flops connected to clock line. Displays numbers on the seven segment display.
 
 ## How to test
 
-Have fun and play
+Use the step button to count from zero to nine.
 
 ## External hardware
 
-number led array and buttons
+number led array and step button
diff --git a/projects/tt_um_wokwi_413923150973445121/info.yaml b/projects/tt_um_wokwi_413923150973445121/info.yaml
index a468a85b..0dcc204a 100644
--- a/projects/tt_um_wokwi_413923150973445121/info.yaml
+++ b/projects/tt_um_wokwi_413923150973445121/info.yaml
@@ -1,10 +1,10 @@
 # Tiny Tapeout project information (Wokwi project)
 project:
   wokwi_id:     413923150973445121       # Set this to the ID of your Wokwi project (the number from the project's URL)
-  title:        "design00"      # Project title
+  title:        "Zero to Nine Display Count"      # Project title
   author:       "Mariano"      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "First Design"      # One line description of what your project does
+  description:  "First Design. Display numbers on seven segment display using flip flop counter."      # One line description of what your project does
   language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -15,24 +15,24 @@ project:
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs
-  ui[0]: "IN0"
-  ui[1]: "IN1"
-  ui[2]: "IN2"
-  ui[3]: "IN3"
-  ui[4]: "IN4"
-  ui[5]: "IN5"
-  ui[6]: "IN6"
-  ui[7]: "IN7"
+  ui[0]: ""
+  ui[1]: ""
+  ui[2]: ""
+  ui[3]: ""
+  ui[4]: ""
+  ui[5]: ""
+  ui[6]: ""
+  ui[7]: ""
 
   # Outputs
   uo[0]: "OUT0"
   uo[1]: "OUT1"
   uo[2]: "OUT2"
-  uo[3]: ""
-  uo[4]: ""
-  uo[5]: ""
-  uo[6]: ""
-  uo[7]: ""
+  uo[3]: "OUT3"
+  uo[4]: "OUT4"
+  uo[5]: "OUT5"
+  uo[6]: "OUT6"
+  uo[7]: "OUT7"
 
   # Bidirectional pins
   uio[0]: ""
diff --git a/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv b/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv
index ae8e3f9a..c77cdb05 100644
--- a/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv
+++ b/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv
@@ -3,8 +3,8 @@ design__lint_error__count,0
 design__lint_timing_construct__count,0
 design__lint_warning__count,0
 design__inferred_latch__count,0
-design__instance__count,287
-design__instance__area,659.382
+design__instance__count,315
+design__instance__area,820.787
 design__instance_unmapped__count,0
 synthesis__check_error__count,0
 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
@@ -12,12 +12,12 @@ design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
 power__internal__total,0.0000023479888113797642
 power__switching__total,0.0
-power__leakage__total,1.6269392499879132E-9
-power__total,0.0000023496156700275606
+power__leakage__total,1.7734165247418332E-9
+power__total,0.0000023497623260482214
 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
-timing__hold__ws__corner:nom_tt_025C_1v80,0.6856978512409907
-timing__setup__ws__corner:nom_tt_025C_1v80,14.092686527742975
+timing__hold__ws__corner:nom_tt_025C_1v80,0.7285897646982152
+timing__setup__ws__corner:nom_tt_025C_1v80,13.846090887966392
 timing__hold__tns__corner:nom_tt_025C_1v80,0.0
 timing__setup__tns__corner:nom_tt_025C_1v80,0.0
 timing__hold__wns__corner:nom_tt_025C_1v80,0
@@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
-timing__hold__ws__corner:nom_ss_100C_1v60,1.6259736239867688
-timing__setup__ws__corner:nom_ss_100C_1v60,12.27398040167648
+timing__hold__ws__corner:nom_ss_100C_1v60,1.6943389393306398
+timing__setup__ws__corner:nom_ss_100C_1v60,11.850050165428787
 timing__hold__tns__corner:nom_ss_100C_1v60,0.0
 timing__setup__tns__corner:nom_ss_100C_1v60,0.0
 timing__hold__wns__corner:nom_ss_100C_1v60,0
@@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
-timing__hold__ws__corner:nom_ff_n40C_1v95,0.3602139799509259
-timing__setup__ws__corner:nom_ff_n40C_1v95,14.693426447000894
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.39918122714952786
+timing__setup__ws__corner:nom_ff_n40C_1v95,14.523472613406232
 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
 timing__hold__wns__corner:nom_ff_n40C_1v95,0
@@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
 design__max_cap_violation__count,0
 clock__skew__worst_hold,0.0
 clock__skew__worst_setup,0.0
-timing__hold__ws,0.3602139799509259
-timing__setup__ws,12.273434171932918
+timing__hold__ws,0.39918122714952786
+timing__setup__ws,11.849390248844285
 timing__hold__tns,0.0
 timing__setup__tns,0.0
 timing__hold__wns,0
@@ -86,12 +86,12 @@ flow__errors__count,0
 design__io,45
 design__die__area,17954.7
 design__core__area,16493.3
-design__instance__count__stdcell,287
-design__instance__area__stdcell,659.382
+design__instance__count__stdcell,315
+design__instance__area__stdcell,820.787
 design__instance__count__macros,0
 design__instance__area__macros,0
-design__instance__utilization,0.0399788
-design__instance__utilization__stdcell,0.0399788
+design__instance__utilization,0.0497648
+design__instance__utilization__stdcell,0.0497648
 design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
 design__power_grid_violation__count,0
@@ -100,42 +100,42 @@ timing__drv__floating__pins,0
 design__instance__displacement__total,0
 design__instance__displacement__mean,0
 design__instance__displacement__max,0
-route__wirelength__estimated,574.535
+route__wirelength__estimated,773.934
 design__violations,0
 design__instance__count__setup_buffer,0
 design__instance__count__hold_buffer,1
 antenna__violating__nets,0
 antenna__violating__pins,0
 route__antenna_violation__count,0
-route__net,81
+route__net,109
 route__net__special,2
-route__drc_errors__iter:1,36
-route__wirelength__iter:1,594
-route__drc_errors__iter:2,1
-route__wirelength__iter:2,548
+route__drc_errors__iter:1,49
+route__wirelength__iter:1,832
+route__drc_errors__iter:2,7
+route__wirelength__iter:2,821
 route__drc_errors__iter:3,0
-route__wirelength__iter:3,544
+route__wirelength__iter:3,802
 route__drc_errors,0
-route__wirelength,544
-route__vias,302
-route__vias__singlecut,302
+route__wirelength,802
+route__vias,433
+route__vias__singlecut,433
 route__vias__multicut,0
 design__disconnected_pin__count,18
 design__critical_disconnected_pin__count,0
-route__wirelength__max,45.28
-timing__unannotated_net__count__corner:nom_tt_025C_1v80,74
+route__wirelength__max,82.225
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,102
 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,1
-timing__unannotated_net__count__corner:nom_ss_100C_1v60,74
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,102
 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,1
-timing__unannotated_net__count__corner:nom_ff_n40C_1v95,74
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,102
 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,1
 design__max_slew_violation__count__corner:min_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
 design__max_cap_violation__count__corner:min_tt_025C_1v80,0
 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
-timing__hold__ws__corner:min_tt_025C_1v80,0.6856978512409907
-timing__setup__ws__corner:min_tt_025C_1v80,14.092873045216388
+timing__hold__ws__corner:min_tt_025C_1v80,0.7285897646982152
+timing__setup__ws__corner:min_tt_025C_1v80,13.8463724405334
 timing__hold__tns__corner:min_tt_025C_1v80,0.0
 timing__setup__tns__corner:min_tt_025C_1v80,0.0
 timing__hold__wns__corner:min_tt_025C_1v80,0
@@ -146,15 +146,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_vio__count__corner:min_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
-timing__unannotated_net__count__corner:min_tt_025C_1v80,74
+timing__unannotated_net__count__corner:min_tt_025C_1v80,102
 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,1
 design__max_slew_violation__count__corner:min_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
 design__max_cap_violation__count__corner:min_ss_100C_1v60,0
 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
-timing__hold__ws__corner:min_ss_100C_1v60,1.6259736239867688
-timing__setup__ws__corner:min_ss_100C_1v60,12.27428415870461
+timing__hold__ws__corner:min_ss_100C_1v60,1.6943389393306398
+timing__setup__ws__corner:min_ss_100C_1v60,11.850398331379155
 timing__hold__tns__corner:min_ss_100C_1v60,0.0
 timing__setup__tns__corner:min_ss_100C_1v60,0.0
 timing__hold__wns__corner:min_ss_100C_1v60,0
@@ -165,15 +165,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_vio__count__corner:min_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
-timing__unannotated_net__count__corner:min_ss_100C_1v60,74
+timing__unannotated_net__count__corner:min_ss_100C_1v60,102
 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,1
 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
-timing__hold__ws__corner:min_ff_n40C_1v95,0.3602139799509259
-timing__setup__ws__corner:min_ff_n40C_1v95,14.693610299938971
+timing__hold__ws__corner:min_ff_n40C_1v95,0.39918122714952786
+timing__setup__ws__corner:min_ff_n40C_1v95,14.523731073333675
 timing__hold__tns__corner:min_ff_n40C_1v95,0.0
 timing__setup__tns__corner:min_ff_n40C_1v95,0.0
 timing__hold__wns__corner:min_ff_n40C_1v95,0
@@ -184,15 +184,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_vio__count__corner:min_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:min_ff_n40C_1v95,74
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,102
 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,1
 design__max_slew_violation__count__corner:max_tt_025C_1v80,0
 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
 design__max_cap_violation__count__corner:max_tt_025C_1v80,0
 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
-timing__hold__ws__corner:max_tt_025C_1v80,0.6856978512409907
-timing__setup__ws__corner:max_tt_025C_1v80,14.09233569725727
+timing__hold__ws__corner:max_tt_025C_1v80,0.7285897646982152
+timing__setup__ws__corner:max_tt_025C_1v80,13.845551763650386
 timing__hold__tns__corner:max_tt_025C_1v80,0.0
 timing__setup__tns__corner:max_tt_025C_1v80,0.0
 timing__hold__wns__corner:max_tt_025C_1v80,0
@@ -203,15 +203,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_vio__count__corner:max_tt_025C_1v80,0
 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
 timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
-timing__unannotated_net__count__corner:max_tt_025C_1v80,74
+timing__unannotated_net__count__corner:max_tt_025C_1v80,102
 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,1
 design__max_slew_violation__count__corner:max_ss_100C_1v60,0
 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
 design__max_cap_violation__count__corner:max_ss_100C_1v60,0
 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
-timing__hold__ws__corner:max_ss_100C_1v60,1.6259736239867688
-timing__setup__ws__corner:max_ss_100C_1v60,12.273434171932918
+timing__hold__ws__corner:max_ss_100C_1v60,1.6943389393306398
+timing__setup__ws__corner:max_ss_100C_1v60,11.849390248844285
 timing__hold__tns__corner:max_ss_100C_1v60,0.0
 timing__setup__tns__corner:max_ss_100C_1v60,0.0
 timing__hold__wns__corner:max_ss_100C_1v60,0
@@ -222,15 +222,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_vio__count__corner:max_ss_100C_1v60,0
 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
 timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
-timing__unannotated_net__count__corner:max_ss_100C_1v60,74
+timing__unannotated_net__count__corner:max_ss_100C_1v60,102
 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,1
 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
-timing__hold__ws__corner:max_ff_n40C_1v95,0.3602139799509259
-timing__setup__ws__corner:max_ff_n40C_1v95,14.693068511087631
+timing__hold__ws__corner:max_ff_n40C_1v95,0.39918122714952786
+timing__setup__ws__corner:max_ff_n40C_1v95,14.522913060985996
 timing__hold__tns__corner:max_ff_n40C_1v95,0.0
 timing__setup__tns__corner:max_ff_n40C_1v95,0.0
 timing__hold__wns__corner:max_ff_n40C_1v95,0
@@ -241,19 +241,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_vio__count__corner:max_ff_n40C_1v95,0
 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
 timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
-timing__unannotated_net__count__corner:max_ff_n40C_1v95,74
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,102
 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,1
-timing__unannotated_net__count,74
+timing__unannotated_net__count,102
 timing__unannotated_net_filtered__count,1
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
-design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000292441
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000246238
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.46096E-8
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000246238
+design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000321882
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000250537
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.34089E-8
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000250537
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
-ir__drop__avg,3.759999999999999919850151111101743683917675298289395868778228759765625E-8
-ir__drop__worst,0.0000029199999999999999949194286197329262222410761751234531402587890625
+ir__drop__avg,3.360000000000000308527820804503638552063193856156431138515472412109375E-8
+ir__drop__worst,0.00000322000000000000008722298057428634621146557037718594074249267578125
 magic__drc_error__count,0
 magic__illegal_overlap__count,0
 design__lvs_device_difference__count,0
diff --git a/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt b/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt
index 843a19e2..af04be7d 100644
--- a/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt
+++ b/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt
@@ -59,50 +59,68 @@
 
 === tt_um_wokwi_413923150973445121 ===
 
-   Number of wires:                 44
-   Number of wire bits:             79
-   Number of public wires:          44
-   Number of public wire bits:      79
+   Number of wires:                 71
+   Number of wire bits:            106
+   Number of public wires:          71
+   Number of public wire bits:     106
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 57
-     and_cell                        9
+   Number of cells:                 84
+     and_cell                       37
      dff_cell                        4
-     not_cell                        3
-     or_cell                        17
+     not_cell                       10
+     or_cell                         7
      sky130_fd_sc_hd__buf_2          7
      sky130_fd_sc_hd__conb_1        17
+     xor_cell                        2
 
    Area for cell type \dff_cell is unknown!
-   Area for cell type \and_cell is unknown!
    Area for cell type \not_cell is unknown!
+   Area for cell type \and_cell is unknown!
+   Area for cell type \xor_cell is unknown!
    Area for cell type \or_cell is unknown!
 
    Chip area for module '\tt_um_wokwi_413923150973445121': 98.844800
 
+=== xor_cell ===
+
+   Number of wires:                  3
+   Number of wire bits:              3
+   Number of public wires:           3
+   Number of public wire bits:       3
+   Number of memories:               0
+   Number of memory bits:            0
+   Number of processes:              0
+   Number of cells:                  1
+     sky130_fd_sc_hd__xor2_2         1
+
+   Chip area for module '\xor_cell': 16.265600
+
 === design hierarchy ===
 
    tt_um_wokwi_413923150973445121      1
-     and_cell                        9
+     and_cell                       37
      dff_cell                        4
-     not_cell                        3
-     or_cell                        17
-
-   Number of wires:                144
-   Number of wire bits:            179
-   Number of public wires:         144
-   Number of public wire bits:     179
+     not_cell                       10
+     or_cell                         7
+     xor_cell                        2
+
+   Number of wires:                245
+   Number of wire bits:            280
+   Number of public wires:         245
+   Number of public wire bits:     280
    Number of memories:               0
    Number of memory bits:            0
    Number of processes:              0
-   Number of cells:                 61
-     sky130_fd_sc_hd__and2_2         9
+   Number of cells:                 88
+     sky130_fd_sc_hd__and2_2        37
      sky130_fd_sc_hd__buf_2          7
      sky130_fd_sc_hd__conb_1        17
      sky130_fd_sc_hd__dfxtp_2        4
-     sky130_fd_sc_hd__inv_2          7
-     sky130_fd_sc_hd__or2_2         17
+     sky130_fd_sc_hd__inv_2         14
+     sky130_fd_sc_hd__or2_2          7
+     sky130_fd_sc_hd__xor2_2         2
 
-   Chip area for top module '\tt_um_wokwi_413923150973445121': 384.118400
+   Chip area for top module '\tt_um_wokwi_413923150973445121': 590.566400
 
diff --git a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.gds b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.gds
index bf81d078..d846d418 100644
Binary files a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.gds and b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.gds differ
diff --git a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef
index e42b9d1b..d58cb8b6 100644
--- a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef
+++ b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef
@@ -453,13 +453,13 @@ MACRO tt_um_wokwi_413923150973445121
         RECT 139.010 110.120 140.670 110.520 ;
         RECT 141.770 110.120 143.430 110.520 ;
         RECT 30.655 109.440 144.145 110.120 ;
-        RECT 30.655 107.615 56.750 109.440 ;
-        RECT 59.150 107.615 60.050 109.440 ;
-        RECT 62.450 107.615 95.620 109.440 ;
-        RECT 98.020 107.615 98.920 109.440 ;
-        RECT 101.320 107.615 134.490 109.440 ;
-        RECT 136.890 107.615 137.790 109.440 ;
-        RECT 140.190 107.615 144.145 109.440 ;
+        RECT 30.655 105.575 56.750 109.440 ;
+        RECT 59.150 105.575 60.050 109.440 ;
+        RECT 62.450 105.575 95.620 109.440 ;
+        RECT 98.020 105.575 98.920 109.440 ;
+        RECT 101.320 105.575 134.490 109.440 ;
+        RECT 136.890 105.575 137.790 109.440 ;
+        RECT 140.190 105.575 144.145 109.440 ;
   END
 END tt_um_wokwi_413923150973445121
 END LIBRARY
diff --git a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v
index fde5d5c3..8ea28c92 100644
--- a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v
+++ b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v
@@ -51,15 +51,6 @@ module tt_um_wokwi_413923150973445121 (clk,
  wire net40;
  wire net41;
  wire net42;
- wire net5;
- wire net6;
- wire net7;
- wire net8;
- wire net9;
- wire net10;
- wire net11;
- wire net12;
- wire net13;
  wire net43;
  wire net44;
  wire net45;
@@ -67,19 +58,51 @@ module tt_um_wokwi_413923150973445121 (clk,
  wire net47;
  wire net48;
  wire net49;
+ wire net5;
  wire net50;
  wire net51;
  wire net52;
  wire net53;
  wire net54;
+ wire net55;
+ wire net56;
+ wire net57;
+ wire net58;
+ wire net59;
+ wire net6;
+ wire net60;
+ wire net61;
+ wire net62;
+ wire net63;
+ wire net64;
+ wire net65;
+ wire net66;
+ wire net67;
+ wire net68;
+ wire net69;
+ wire net7;
+ wire net8;
+ wire net10;
+ wire net11;
+ wire net12;
+ wire net13;
+ wire net70;
+ wire net71;
+ wire net72;
+ wire net73;
+ wire net74;
+ wire net75;
+ wire net76;
+ wire net77;
+ wire net78;
+ wire net79;
+ wire net80;
+ wire net81;
+ wire net82;
  wire \flop4/q ;
  wire net1;
+ wire net9;
 
- sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_2 (.VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR),
-    .LO(net9));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_3 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
@@ -104,63 +127,68 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net43));
+    .LO(net70));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_8 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net44));
+    .LO(net71));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_9 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net45));
+    .LO(net72));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_10 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net46));
+    .LO(net73));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_11 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net47));
+    .LO(net74));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_12 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net48));
+    .LO(net75));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_13 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net49));
+    .LO(net76));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_14 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net50));
+    .LO(net77));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_15 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net51));
+    .LO(net78));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_16 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net52));
+    .LO(net79));
  sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_17 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net53));
+    .LO(net80));
+ sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_18 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .LO(net81));
  sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(net18),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net54));
+    .X(net82));
  sky130_fd_sc_hd__buf_2 _17_ (.A(net2),
     .VGND(VGND),
     .VNB(VGND),
@@ -203,69 +231,265 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VPB(VPWR),
     .VPWR(VPWR),
     .X(uo_out[6]));
- sky130_fd_sc_hd__and2_1 \and1/_0_  (.A(net20),
+ sky130_fd_sc_hd__and2_1 \and1/_0_  (.A(net22),
+    .B(net24),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net25));
+ sky130_fd_sc_hd__and2_1 \and10/_0_  (.A(net23),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net39));
+ sky130_fd_sc_hd__and2_1 \and11/_0_  (.A(net19),
+    .B(net22),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net40));
+ sky130_fd_sc_hd__and2_1 \and12/_0_  (.A(net14),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net41));
+ sky130_fd_sc_hd__and2_1 \and13/_0_  (.A(net21),
+    .B(net22),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net42));
+ sky130_fd_sc_hd__and2_1 \and14/_0_  (.A(net44),
+    .B(net43),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net34));
+ sky130_fd_sc_hd__and2_1 \and15/_0_  (.A(net14),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net43));
+ sky130_fd_sc_hd__and2_1 \and16/_0_  (.A(net19),
+    .B(net17),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net44));
+ sky130_fd_sc_hd__and2_1 \and17/_0_  (.A(net46),
+    .B(net45),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net47));
+ sky130_fd_sc_hd__and2_1 \and18/_0_  (.A(net14),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net45));
+ sky130_fd_sc_hd__and2_1 \and19/_0_  (.A(net21),
     .B(net17),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net21));
- sky130_fd_sc_hd__and2_1 \and2/_0_  (.A(net24),
+    .X(net46));
+ sky130_fd_sc_hd__and2_1 \and2/_0_  (.A(net26),
+    .B(net25),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net27));
+ sky130_fd_sc_hd__and2_1 \and20/_0_  (.A(net49),
+    .B(net48),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net50));
+ sky130_fd_sc_hd__and2_1 \and21/_0_  (.A(net23),
+    .B(net20),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net48));
+ sky130_fd_sc_hd__and2_1 \and22/_0_  (.A(net21),
     .B(net22),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net25));
- sky130_fd_sc_hd__and2_1 \and3/_0_  (.A(net23),
+    .X(net49));
+ sky130_fd_sc_hd__and2_1 \and23/_0_  (.A(net21),
+    .B(net51),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net52));
+ sky130_fd_sc_hd__and2_1 \and24/_0_  (.A(net23),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net51));
+ sky130_fd_sc_hd__and2_1 \and25/_0_  (.A(net55),
+    .B(net54),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net56));
+ sky130_fd_sc_hd__and2_1 \and26/_0_  (.A(net23),
     .B(net24),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net26));
- sky130_fd_sc_hd__and2_1 \and4/_0_  (.A(net20),
-    .B(net14),
+    .X(net54));
+ sky130_fd_sc_hd__and2_1 \and27/_0_  (.A(net19),
+    .B(net22),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net27));
- sky130_fd_sc_hd__and2_1 \and5/_0_  (.A(net24),
-    .B(net14),
+    .X(net55));
+ sky130_fd_sc_hd__and2_1 \and28/_0_  (.A(net58),
+    .B(net57),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net59));
+ sky130_fd_sc_hd__and2_1 \and29/_0_  (.A(net14),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net57));
+ sky130_fd_sc_hd__and2_1 \and3/_0_  (.A(net14),
+    .B(net24),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
     .X(net28));
- sky130_fd_sc_hd__and2_1 \and6/_0_  (.A(net14),
-    .B(net22),
+ sky130_fd_sc_hd__and2_1 \and30/_0_  (.A(net19),
+    .B(net17),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net29));
- sky130_fd_sc_hd__and2_1 \and7/_0_  (.A(net17),
-    .B(net23),
+    .X(net58));
+ sky130_fd_sc_hd__and2_1 \and31/_0_  (.A(net17),
+    .B(net60),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net61));
+ sky130_fd_sc_hd__and2_1 \and32/_0_  (.A(net23),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net60));
+ sky130_fd_sc_hd__and2_1 \and33/_0_  (.A(net22),
+    .B(net64),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net65));
+ sky130_fd_sc_hd__and2_1 \and34/_0_  (.A(net23),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net64));
+ sky130_fd_sc_hd__and2_1 \and35/_0_  (.A(net67),
+    .B(net66),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net68));
+ sky130_fd_sc_hd__and2_1 \and36/_0_  (.A(net14),
+    .B(net1),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net66));
+ sky130_fd_sc_hd__and2_1 \and37/_0_  (.A(net19),
+    .B(net17),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net67));
+ sky130_fd_sc_hd__and2_1 \and4/_0_  (.A(net29),
+    .B(net28),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
     .X(net30));
- sky130_fd_sc_hd__and2_1 \and8/_0_  (.A(net17),
-    .B(net24),
+ sky130_fd_sc_hd__and2_1 \and5/_0_  (.A(net23),
+    .B(net1),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
     .X(net31));
- sky130_fd_sc_hd__and2_1 \and9/_0_  (.A(net30),
-    .B(net24),
+ sky130_fd_sc_hd__and2_1 \and6/_0_  (.A(net21),
+    .B(net17),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
     .X(net32));
+ sky130_fd_sc_hd__and2_1 \and7/_0_  (.A(net32),
+    .B(net31),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net33));
+ sky130_fd_sc_hd__and2_1 \and8/_0_  (.A(net40),
+    .B(net39),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net37));
+ sky130_fd_sc_hd__and2_1 \and9/_0_  (.A(net42),
+    .B(net41),
+    .VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .X(net38));
  sky130_fd_sc_hd__inv_2 \flop1/_0_  (.A(net16),
     .VGND(VGND),
     .VNB(VGND),
@@ -292,7 +516,7 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VPB(VPWR),
     .VPWR(VPWR),
     .Q(net15));
- sky130_fd_sc_hd__inv_2 \flop3/_0_  (.A(net54),
+ sky130_fd_sc_hd__inv_2 \flop3/_0_  (.A(net82),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
@@ -318,143 +542,129 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VPB(VPWR),
     .VPWR(VPWR),
     .Q(\flop4/q ));
- sky130_fd_sc_hd__inv_2 \not1/_0_  (.A(net17),
+ sky130_fd_sc_hd__inv_2 \not1/_0_  (.A(net19),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .Y(net22));
- sky130_fd_sc_hd__inv_2 \not2/_0_  (.A(net14),
+    .Y(net21));
+ sky130_fd_sc_hd__inv_2 \not10/_0_  (.A(net69),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .Y(net23));
- sky130_fd_sc_hd__inv_2 \not3/_0_  (.A(net20),
+    .Y(net8));
+ sky130_fd_sc_hd__inv_2 \not2/_0_  (.A(net17),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .Y(net24));
- sky130_fd_sc_hd__or2_1 \or1/_0_  (.A(net34),
-    .B(net33),
+    .Y(net22));
+ sky130_fd_sc_hd__inv_2 \not3/_0_  (.A(net14),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net2));
- sky130_fd_sc_hd__or2_1 \or10/_0_  (.A(net27),
-    .B(net26),
+    .Y(net23));
+ sky130_fd_sc_hd__inv_2 \not4/_0_  (.A(net20),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net35));
- sky130_fd_sc_hd__or2_1 \or11/_0_  (.A(net23),
-    .B(net17),
+    .Y(net24));
+ sky130_fd_sc_hd__inv_2 \not5/_0_  (.A(net27),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net36));
- sky130_fd_sc_hd__or2_1 \or12/_0_  (.A(net29),
-    .B(net19),
+    .Y(net2));
+ sky130_fd_sc_hd__inv_2 \not6/_0_  (.A(net30),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net42));
- sky130_fd_sc_hd__or2_1 \or13/_0_  (.A(net31),
-    .B(net30),
+    .Y(net3));
+ sky130_fd_sc_hd__inv_2 \not7/_0_  (.A(net33),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net39));
- sky130_fd_sc_hd__or2_1 \or14/_0_  (.A(net30),
-    .B(net19),
+    .Y(net4));
+ sky130_fd_sc_hd__inv_2 \not8/_0_  (.A(net36),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net40));
- sky130_fd_sc_hd__or2_1 \or15/_0_  (.A(net28),
-    .B(net29),
+    .Y(net5));
+ sky130_fd_sc_hd__inv_2 \not9/_0_  (.A(net63),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net41));
- sky130_fd_sc_hd__or2_1 \or16/_0_  (.A(net42),
-    .B(net6),
+    .Y(net7));
+ sky130_fd_sc_hd__or2_1 \or1/_0_  (.A(net35),
+    .B(net34),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net37));
- sky130_fd_sc_hd__or2_1 \or17/_0_  (.A(net26),
-    .B(net19),
-    .VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR),
-    .X(net38));
- sky130_fd_sc_hd__or2_1 \or2/_0_  (.A(net22),
-    .B(net35),
+    .X(net36));
+ sky130_fd_sc_hd__or2_1 \or2/_0_  (.A(net38),
+    .B(net37),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net3));
- sky130_fd_sc_hd__or2_1 \or3/_0_  (.A(net20),
-    .B(net36),
+    .X(net35));
+ sky130_fd_sc_hd__or2_1 \or3/_0_  (.A(net50),
+    .B(net47),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net4));
- sky130_fd_sc_hd__or2_1 \or4/_0_  (.A(net32),
-    .B(net37),
+    .X(net53));
+ sky130_fd_sc_hd__or2_1 \or4/_0_  (.A(net52),
+    .B(net53),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net5));
- sky130_fd_sc_hd__or2_1 \or5/_0_  (.A(net39),
-    .B(net38),
+    .X(net6));
+ sky130_fd_sc_hd__or2_1 \or5/_0_  (.A(net59),
+    .B(net56),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net7));
- sky130_fd_sc_hd__or2_1 \or6/_0_  (.A(net41),
-    .B(net40),
+    .X(net62));
+ sky130_fd_sc_hd__or2_1 \or6/_0_  (.A(net61),
+    .B(net62),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net8));
- sky130_fd_sc_hd__or2_1 \or7/_0_  (.A(net14),
-    .B(net19),
+    .X(net63));
+ sky130_fd_sc_hd__or2_1 \or7/_0_  (.A(net68),
+    .B(net65),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net33));
- sky130_fd_sc_hd__or2_1 \or8/_0_  (.A(net25),
-    .B(net21),
+    .X(net69));
+ sky130_fd_sc_hd__xor2_1 \xor2/_0_  (.A(net19),
+    .B(net14),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net34));
- sky130_fd_sc_hd__or2_1 \or9/_0_  (.A(net28),
-    .B(net25),
+    .X(net26));
+ sky130_fd_sc_hd__xor2_1 \xor3/_0_  (.A(net19),
+    .B(net17),
     .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .X(net6));
+    .X(net29));
  sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_0_Right_0 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
@@ -1217,11 +1427,17 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VPWR(VPWR));
  sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_302 (.VGND(VGND),
     .VPWR(VPWR));
- sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_1 (.VGND(VGND),
+ sky130_fd_sc_hd__clkbuf_2 fanout1 (.A(net24),
+    .VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR),
-    .LO(net1));
+    .X(net1));
+ sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_2 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR),
+    .LO(net9));
  sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
@@ -5830,47 +6046,47 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_153 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_32_153 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_165 (.VPWR(VPWR),
-    .VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_32_161 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_177 (.VPWR(VPWR),
-    .VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_32_179 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_32_189 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_3 FILLER_0_32_186 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_32_195 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_32_194 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_197 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_32_197 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_209 (.VPWR(VPWR),
+    .VPWR(VPWR));
+ sky130_ef_sc_hd__decap_12 FILLER_0_32_201 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_221 (.VPWR(VPWR),
+ sky130_fd_sc_hd__decap_4 FILLER_0_32_213 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_ef_sc_hd__decap_12 FILLER_0_32_220 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_32_233 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_32_232 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_32_245 (.VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_32_251 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_8 FILLER_0_32_244 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -5962,75 +6178,71 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_125 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__decap_4 FILLER_0_33_125 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_137 (.VPWR(VPWR),
-    .VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_33_129 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_149 (.VPWR(VPWR),
-    .VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_4 FILLER_0_33_148 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_33_161 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_33_152 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_33_167 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_4 FILLER_0_33_163 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_169 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_33_167 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_181 (.VPWR(VPWR),
-    .VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_33_169 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_193 (.VPWR(VPWR),
-    .VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_33_175 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_8 FILLER_0_33_205 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_8 FILLER_0_33_181 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_33_213 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_33_189 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_6 FILLER_0_33_217 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_6 FILLER_0_33_196 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_33_223 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_33_207 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_225 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_33_228 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_237 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_33_240 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_249 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_33_252 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_33_261 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_33_264 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_33_273 (.VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_33_279 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_4 FILLER_0_33_276 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6106,51 +6318,43 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_34_133 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_34_138 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_34_139 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_6 FILLER_0_34_149 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_34_141 (.VPWR(VPWR),
-    .VGND(VGND),
-    .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__fill_1 FILLER_0_34_153 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_34_155 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_34_159 (.VPWR(VPWR),
-    .VGND(VGND),
-    .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__fill_2 FILLER_0_34_171 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_8 FILLER_0_34_159 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_3 FILLER_0_34_181 (.VGND(VGND),
-    .VNB(VGND),
+ sky130_ef_sc_hd__decap_12 FILLER_0_34_172 (.VPWR(VPWR),
+    .VGND(VGND),
     .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__decap_4 FILLER_0_34_192 (.VGND(VGND),
+    .VNB(VGND));
+ sky130_fd_sc_hd__decap_6 FILLER_0_34_184 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_8 FILLER_0_34_197 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_34_195 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_2 FILLER_0_34_205 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_6 FILLER_0_34_212 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_8 FILLER_0_34_242 (.VGND(VGND),
-    .VNB(VGND),
+ sky130_ef_sc_hd__decap_12 FILLER_0_34_234 (.VPWR(VPWR),
+    .VGND(VGND),
     .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__fill_2 FILLER_0_34_250 (.VGND(VGND),
+    .VNB(VGND));
+ sky130_fd_sc_hd__decap_6 FILLER_0_34_246 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6242,71 +6446,67 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_35_125 (.VPWR(VPWR),
-    .VGND(VGND),
-    .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_35_137 (.VPWR(VPWR),
-    .VGND(VGND),
-    .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_4 FILLER_0_35_149 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_6 FILLER_0_35_125 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_3 FILLER_0_35_169 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_6 FILLER_0_35_136 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_4 FILLER_0_35_177 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_35_142 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_2 FILLER_0_35_191 (.VGND(VGND),
+ sky130_ef_sc_hd__decap_12 FILLER_0_35_153 (.VPWR(VPWR),
+    .VGND(VGND),
+    .VPB(VPWR),
+    .VNB(VGND));
+ sky130_fd_sc_hd__decap_3 FILLER_0_35_165 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_6 FILLER_0_35_196 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_35_169 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_6 FILLER_0_35_207 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_35_176 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_35_213 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_6 FILLER_0_35_193 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_6 FILLER_0_35_217 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_35_199 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_35_223 (.VGND(VGND),
+ sky130_ef_sc_hd__decap_12 FILLER_0_35_209 (.VPWR(VPWR),
+    .VGND(VGND),
+    .VPB(VPWR),
+    .VNB(VGND));
+ sky130_fd_sc_hd__decap_3 FILLER_0_35_221 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_35_225 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_35_228 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_35_237 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_35_240 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_35_249 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_35_252 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_35_261 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_35_264 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_35_273 (.VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_35_279 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_4 FILLER_0_35_276 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6382,7 +6582,7 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_36_133 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_36_133 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6390,39 +6590,43 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_36_141 (.VPWR(VPWR),
-    .VGND(VGND),
-    .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_4 FILLER_0_36_153 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_36_146 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_8 FILLER_0_36_167 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_36_174 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_6 FILLER_0_36_180 (.VGND(VGND),
-    .VNB(VGND),
+ sky130_ef_sc_hd__decap_12 FILLER_0_36_179 (.VPWR(VPWR),
+    .VGND(VGND),
     .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_36_202 (.VGND(VGND),
+    .VNB(VGND));
+ sky130_fd_sc_hd__decap_4 FILLER_0_36_191 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_6 FILLER_0_36_208 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_36_195 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_36_214 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_36_212 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_36_234 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_36_223 (.VPWR(VPWR),
+    .VGND(VGND),
+    .VPB(VPWR),
+    .VNB(VGND));
+ sky130_ef_sc_hd__decap_12 FILLER_0_36_235 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_36_246 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_4 FILLER_0_36_247 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_36_251 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6518,55 +6722,55 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_37_137 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__decap_8 FILLER_0_37_155 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_37_149 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_2 FILLER_0_37_163 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_37_155 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_37_169 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_2 FILLER_0_37_166 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_37_174 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_37_184 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_37_178 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_37_196 (.VGND(VGND),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__decap_6 FILLER_0_37_187 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_37_223 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_37_201 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_ef_sc_hd__decap_12 FILLER_0_37_225 (.VPWR(VPWR),
-    .VGND(VGND),
+ sky130_fd_sc_hd__decap_8 FILLER_0_37_207 (.VGND(VGND),
+    .VNB(VGND),
     .VPB(VPWR),
-    .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_37_237 (.VPWR(VPWR),
+    .VPWR(VPWR));
+ sky130_fd_sc_hd__fill_1 FILLER_0_37_223 (.VGND(VGND),
+    .VNB(VGND),
+    .VPB(VPWR),
+    .VPWR(VPWR));
+ sky130_ef_sc_hd__decap_12 FILLER_0_37_241 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_37_249 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_37_253 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_ef_sc_hd__decap_12 FILLER_0_37_261 (.VPWR(VPWR),
+ sky130_ef_sc_hd__decap_12 FILLER_0_37_265 (.VPWR(VPWR),
     .VGND(VGND),
     .VPB(VPWR),
     .VNB(VGND));
- sky130_fd_sc_hd__decap_6 FILLER_0_37_273 (.VGND(VGND),
-    .VNB(VGND),
-    .VPB(VPWR),
-    .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_37_279 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_37_277 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6670,31 +6874,35 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_2 FILLER_0_38_166 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_1 FILLER_0_38_144 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_3 FILLER_0_38_169 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_38_148 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_2 FILLER_0_38_181 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_38_154 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_4 FILLER_0_38_191 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_4 FILLER_0_38_164 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__fill_1 FILLER_0_38_195 (.VGND(VGND),
+ sky130_fd_sc_hd__decap_3 FILLER_0_38_169 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_3 FILLER_0_38_201 (.VGND(VGND),
+ sky130_ef_sc_hd__decap_12 FILLER_0_38_184 (.VPWR(VPWR),
+    .VGND(VGND),
+    .VPB(VPWR),
+    .VNB(VGND));
+ sky130_fd_sc_hd__fill_1 FILLER_0_38_201 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- sky130_fd_sc_hd__decap_3 FILLER_0_38_209 (.VGND(VGND),
+ sky130_fd_sc_hd__fill_2 FILLER_0_38_206 (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
@@ -6746,21 +6954,21 @@ module tt_um_wokwi_413923150973445121 (clk,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
- assign uio_oe[0] = net1;
- assign uio_oe[1] = net9;
- assign uio_oe[2] = net10;
- assign uio_oe[3] = net11;
- assign uio_oe[4] = net12;
- assign uio_oe[5] = net13;
- assign uio_oe[6] = net43;
- assign uio_oe[7] = net44;
- assign uio_out[0] = net45;
- assign uio_out[1] = net46;
- assign uio_out[2] = net47;
- assign uio_out[3] = net48;
- assign uio_out[4] = net49;
- assign uio_out[5] = net50;
- assign uio_out[6] = net51;
- assign uio_out[7] = net52;
- assign uo_out[7] = net53;
+ assign uio_oe[0] = net9;
+ assign uio_oe[1] = net10;
+ assign uio_oe[2] = net11;
+ assign uio_oe[3] = net12;
+ assign uio_oe[4] = net13;
+ assign uio_oe[5] = net70;
+ assign uio_oe[6] = net71;
+ assign uio_oe[7] = net72;
+ assign uio_out[0] = net73;
+ assign uio_out[1] = net74;
+ assign uio_out[2] = net75;
+ assign uio_out[3] = net76;
+ assign uio_out[4] = net77;
+ assign uio_out[5] = net78;
+ assign uio_out[6] = net79;
+ assign uio_out[7] = net80;
+ assign uo_out[7] = net81;
 endmodule
diff --git a/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json b/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json
index 77ce5a1d..38f11e95 100644
--- a/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json
+++ b/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json
@@ -18,13 +18,13 @@
       "left": -115.2,
       "attrs": { "frequency": "10000" }
     },
-    { "type": "wokwi-gnd", "id": "pwr2", "top": 19.2, "left": 1151.4, "attrs": {} },
+    { "type": "wokwi-gnd", "id": "pwr2", "top": -124.8, "left": 2159.4, "attrs": {} },
     { "type": "wokwi-vcc", "id": "pwr1", "top": -229.64, "left": -115.2, "attrs": {} },
     {
       "type": "wokwi-7segment",
       "id": "sevseg1",
-      "top": -235.02,
-      "left": 1406.68,
+      "top": -254.22,
+      "left": 2069.08,
       "attrs": { "common": "cathode" }
     },
     {
@@ -60,8 +60,8 @@
     {
       "type": "board-tt-block-output",
       "id": "ttout",
-      "top": -247.33,
-      "left": 1147.2,
+      "top": -266.53,
+      "left": 1809.6,
       "attrs": { "verilogRole": "output" }
     },
     {
@@ -135,74 +135,94 @@
       "left": -103.45,
       "attrs": { "text": "Bidirectional I/O pins" }
     },
-    { "type": "wokwi-junction", "id": "j1", "top": -254.4, "left": 388.8, "attrs": {} },
-    { "type": "wokwi-junction", "id": "j2", "top": -187.2, "left": 388.8, "attrs": {} },
-    { "type": "wokwi-junction", "id": "j3", "top": -129.6, "left": 388.8, "attrs": {} },
-    { "type": "wokwi-junction", "id": "j4", "top": -72, "left": 388.8, "attrs": {} },
     {
       "type": "wokwi-flip-flop-d",
       "id": "flop1",
-      "top": -134.2,
-      "left": 268.6,
+      "top": -67,
+      "left": 191.8,
       "rotate": 270,
       "attrs": {}
     },
     {
       "type": "wokwi-flip-flop-d",
       "id": "flop2",
-      "top": 9.8,
-      "left": 268.6,
+      "top": 86.6,
+      "left": 191.8,
       "rotate": 270,
       "attrs": {}
     },
     {
       "type": "wokwi-flip-flop-d",
       "id": "flop3",
-      "top": 163.4,
-      "left": 259,
+      "top": 259.4,
+      "left": 191.8,
       "rotate": 270,
-      "attrs": { "color": "white", "label": "Flop3" }
+      "attrs": {}
     },
     {
       "type": "wokwi-flip-flop-d",
       "id": "flop4",
-      "top": -297.4,
-      "left": 268.6,
+      "top": -220.6,
+      "left": 191.8,
       "rotate": 270,
       "attrs": {}
     },
-    { "type": "wokwi-gate-and-2", "id": "and1", "top": -307.2, "left": 566.4, "attrs": {} },
-    { "type": "wokwi-gate-not", "id": "not1", "top": -201.6, "left": 432, "attrs": {} },
-    { "type": "wokwi-gate-not", "id": "not2", "top": -144, "left": 432, "attrs": {} },
-    { "type": "wokwi-gate-not", "id": "not3", "top": -86.4, "left": 432, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and2", "top": -230.4, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not1", "top": 192, "left": 316.8, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not2", "top": 38.4, "left": 316.8, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not3", "top": -115.2, "left": 316.8, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not4", "top": -268.8, "left": 316.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and1", "top": -316.8, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and2", "top": -288, "left": 691.2, "attrs": {} },
+    { "type": "wokwi-gate-xor-2", "id": "xor2", "top": -249.6, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not5", "top": -288, "left": 835.2, "attrs": {} },
     { "type": "wokwi-gate-and-2", "id": "and3", "top": -163.2, "left": 566.4, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and4", "top": -96, "left": 566.4, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and5", "top": -28.8, "left": 566.4, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and6", "top": 38.4, "left": 566.4, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and7", "top": 105.6, "left": 566.4, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and8", "top": 172.8, "left": 556.8, "attrs": {} },
-    { "type": "wokwi-gate-and-2", "id": "and9", "top": 76.8, "left": 681.6, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or1", "top": -316.8, "left": 1008, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or2", "top": -240, "left": 883.2, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or3", "top": -163.2, "left": 892.8, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or4", "top": -76.8, "left": 969.6, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or5", "top": -19.2, "left": 969.6, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or6", "top": 182.4, "left": 979.2, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or7", "top": -355.2, "left": 883.2, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or8", "top": -297.6, "left": 883.2, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or9", "top": -105.6, "left": 710.4, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or10", "top": -249.6, "left": 691.2, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or11", "top": -192, "left": 691.2, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or12", "top": -19.2, "left": 720, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or13", "top": 124.8, "left": 729.6, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or14", "top": 144, "left": 854.4, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or15", "top": 220.8, "left": 844.8, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or16", "top": -86.4, "left": 854.4, "attrs": {} },
-    { "type": "wokwi-gate-or-2", "id": "or17", "top": -28.8, "left": 864, "attrs": {} },
-    { "type": "wokwi-junction", "id": "j5", "top": -350.4, "left": 840, "attrs": {} },
-    { "type": "wokwi-junction", "id": "j6", "top": 72, "left": 936, "attrs": {} },
-    { "type": "wokwi-junction", "id": "j7", "top": 100.8, "left": 974.4, "attrs": {} }
+    { "type": "wokwi-gate-and-2", "id": "and4", "top": -144, "left": 691.2, "attrs": {} },
+    { "type": "wokwi-gate-xor-2", "id": "xor3", "top": -105.6, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not6", "top": -144, "left": 825.6, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and5", "top": 0, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and6", "top": 86.4, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and7", "top": 38.4, "left": 710.4, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not7", "top": 38.4, "left": 835.2, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or1", "top": 211.2, "left": 864, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not8", "top": 211.2, "left": 1008, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or2", "top": 441.6, "left": 912, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and8", "top": 412.8, "left": 748.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and9", "top": 499.2, "left": 748.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and10", "top": 355.2, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and11", "top": 441.6, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and12", "top": 508.8, "left": 576, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and13", "top": 595.2, "left": 576, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and14", "top": 192, "left": 729.6, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and15", "top": 182.4, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and16", "top": 240, "left": 566.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and17", "top": -336, "left": 1296, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and18", "top": -345.6, "left": 1132.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and19", "top": -288, "left": 1132.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and20", "top": -182.4, "left": 1296, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and21", "top": -230.4, "left": 1132.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and22", "top": -172.8, "left": 1132.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and23", "top": 9.6, "left": 1315.2, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and24", "top": -76.8, "left": 1152, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or3", "top": -288, "left": 1468.8, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or4", "top": -278.4, "left": 1584, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and25", "top": 105.6, "left": 1305.6, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and26", "top": 96, "left": 1142.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and27", "top": 153.6, "left": 1142.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and28", "top": 259.2, "left": 1305.6, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and29", "top": 249.6, "left": 1142.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and30", "top": 307.2, "left": 1142.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and31", "top": 403.2, "left": 1334.4, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and32", "top": 393.6, "left": 1161.6, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or5", "top": 182.4, "left": 1420.8, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or6", "top": 192, "left": 1536, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and33", "top": 508.8, "left": 1219.2, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and34", "top": 470.4, "left": 1036.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and35", "top": 576, "left": 1219.2, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and36", "top": 566.4, "left": 1036.8, "attrs": {} },
+    { "type": "wokwi-gate-and-2", "id": "and37", "top": 624, "left": 1036.8, "attrs": {} },
+    { "type": "wokwi-gate-or-2", "id": "or7", "top": 518.4, "left": 1372.8, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not9", "top": 192, "left": 1651.2, "attrs": {} },
+    { "type": "wokwi-gate-not", "id": "not10", "top": 518.4, "left": 1488, "attrs": {} }
   ],
   "connections": [
     [ "pwr1:VCC", "sw1:8a", "red", [ "v0" ] ],
@@ -213,21 +233,16 @@
     [ "pwr1:VCC", "sw1:1a", "red", [ "v0" ] ],
     [ "pwr1:VCC", "sw1:2a", "red", [ "v0" ] ],
     [ "pwr1:VCC", "sw1:3a", "red", [ "v0" ] ],
-    [ "ttout:EXTOUT0", "sevseg1:A", "green", [ "h21.01", "v-28.8", "h96" ] ],
-    [ "ttout:EXTOUT1", "sevseg1:B", "green", [ "h11.41", "v-48", "h122.99", "v41.34" ] ],
-    [
-      "ttout:EXTOUT2",
-      "sevseg1:C",
-      "green",
-      [ "h30.61", "v-38.4", "h115.2", "v105.6", "h-28.8" ]
-    ],
-    [ "ttout:EXTOUT3", "sevseg1:D", "green", [ "h57.6", "v57.6", "h48" ] ],
-    [ "sevseg1:E", "ttout:EXTOUT4", "green", [ "v9.6", "h-48", "v-38.4" ] ],
-    [ "ttout:EXTOUT5", "sevseg1:F", "green", [ "h69.01", "v-57.6", "h28.8" ] ],
-    [ "ttout:EXTOUT6", "sevseg1:G", "green", [ "h78.61", "v-57.6" ] ],
-    [ "ttout:EXTOUT7", "sevseg1:DP", "green", [ "v28.8", "h136.21" ] ],
-    [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v-76.8", "h268.8" ] ],
-    [ "sw2:1", "clock1:CLK", "blue", [ "h-19.2", "v-57.6" ] ],
+    [ "ttout:EXTOUT0", "sevseg1:A", "green", [ "v0" ] ],
+    [ "ttout:EXTOUT1", "sevseg1:B", "green", [ "v0" ] ],
+    [ "ttout:EXTOUT2", "sevseg1:C", "green", [ "v0" ] ],
+    [ "ttout:EXTOUT3", "sevseg1:D", "green", [ "v0" ] ],
+    [ "sevseg1:E", "ttout:EXTOUT4", "green", [ "v0" ] ],
+    [ "ttout:EXTOUT5", "sevseg1:F", "green", [ "v0" ] ],
+    [ "ttout:EXTOUT6", "sevseg1:G", "green", [ "v0" ] ],
+    [ "ttout:EXTOUT7", "sevseg1:DP", "green", [ "v0" ] ],
+    [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v0" ] ],
+    [ "sw2:1", "clock1:CLK", "blue", [ "v0" ] ],
     [ "sw1:1b", "ttin:EXTIN0", "green", [ "h0" ] ],
     [ "sw1:2b", "ttin:EXTIN1", "green", [ "h0" ] ],
     [ "ttin:EXTIN2", "sw1:3b", "green", [ "h0" ] ],
@@ -240,84 +255,126 @@
     [ "btn1:1.l", "sw2:3", "blue", [ "h0" ] ],
     [ "pwr3:VCC", "btn1:2.r", "red", [ "v0" ] ],
     [ "btn2:2.l", "gnd1:GND", "black", [ "h0" ] ],
-    [ "ttin:EXTRST_N", "btn2:1.r", "orange", [ "h-38.4", "v-96" ] ],
+    [ "ttin:EXTRST_N", "btn2:1.r", "orange", [ "v0" ] ],
     [ "btn2:1.l", "r2:2", "green", [ "h0" ] ],
     [ "pwr5:VCC", "r2:1", "red", [ "v0" ] ],
-    [ "flop3:Q", "flop2:CLK", "green", [ "v-38.4", "h28.8" ] ],
-    [ "flop3:NOTQ", "flop3:D", "green", [ "v-19.2", "h-48", "v115.2" ] ],
-    [ "flop2:NOTQ", "flop2:D", "green", [ "v-9.6", "h-48", "v105.6" ] ],
-    [ "flop2:Q", "flop1:CLK", "green", [ "v-28.8", "h19.2" ] ],
-    [ "flop1:Q", "flop4:CLK", "green", [ "v-28.8", "h19.2" ] ],
-    [ "flop1:NOTQ", "flop1:D", "green", [ "h-48", "v96" ] ],
-    [ "flop4:NOTQ", "flop4:D", "green", [ "v-28.8", "h-48", "v124.8" ] ],
-    [ "flop3:CLK", "ttin:CLK", "green", [ "v28.8", "h-86.4", "v-220.8", "h-38.4", "v-240" ] ],
-    [ "ttout:OUT0", "or1:OUT", "green", [ "h-38.4", "v-67.2" ] ],
-    [ "ttout:OUT1", "or2:OUT", "green", [ "h-76.8", "v-9.6" ] ],
-    [ "ttout:OUT2", "or3:OUT", "green", [ "h-76.8", "v28.8" ] ],
-    [ "ttout:OUT3", "or4:OUT", "green", [ "h-67.2", "v76.8" ] ],
-    [ "ttout:OUT5", "or5:OUT", "green", [ "h-48", "v172.8" ] ],
-    [ "ttout:OUT6", "or6:OUT", "green", [ "h-38.4", "v220.8" ] ],
-    [ "flop3:NOTQ", "j1:J", "magenta", [ "h48", "v-384" ] ],
-    [ "flop2:NOTQ", "j2:J", "cyan", [ "h28.8", "v-163.2" ] ],
-    [ "flop1:NOTQ", "j3:J", "gold", [ "h48", "v38.4" ] ],
-    [ "flop4:NOTQ", "j4:J", "green", [ "h19.2", "v259.2" ] ],
-    [ "j2:J", "not1:IN", "cyan", [ "v0" ] ],
-    [ "j3:J", "not2:IN", "gold", [ "v0" ] ],
-    [ "j4:J", "not3:IN", "green", [ "v0" ] ],
-    [ "or1:A", "or7:OUT", "green", [ "h-9.6", "v-38.4" ] ],
-    [ "or1:B", "or8:OUT", "green", [ "h0" ] ],
-    [ "ttout:OUT4", "or9:OUT", "green", [ "h-57.6", "v124.8" ] ],
-    [ "and1:OUT", "or8:A", "green", [ "v0" ] ],
-    [ "j3:J", "or7:B", "gold", [ "h9.6", "v-201.6" ] ],
-    [ "or10:OUT", "or2:A", "green", [ "v0" ] ],
-    [ "or3:A", "or11:OUT", "green", [ "h-28.8", "v-19.2" ] ],
-    [ "or6:A", "or14:OUT", "green", [ "h0" ] ],
-    [ "or6:B", "or15:OUT", "green", [ "h0" ] ],
-    [ "or13:OUT", "or5:B", "green", [ "v-134.4", "h76.8" ] ],
-    [ "and9:OUT", "or4:B", "green", [ "h57.6", "v-144" ] ],
-    [ "or4:A", "or16:OUT", "green", [ "h0" ] ],
-    [ "or16:A", "or9:OUT", "green", [ "h0" ] ],
-    [ "or16:B", "or12:OUT", "green", [ "h0" ] ],
-    [ "or5:A", "or17:OUT", "green", [ "h0" ] ],
-    [ "or17:B", "and3:OUT", "green", [ "h-28.8", "v-144" ] ],
-    [ "or8:B", "and2:OUT", "green", [ "h0" ] ],
-    [ "j1:J", "j5:J", "magenta", [ "v0" ] ],
-    [ "j5:J", "or7:A", "magenta", [ "v0" ] ],
-    [ "or17:A", "j5:J", "magenta", [ "h0" ] ],
-    [ "or14:A", "j5:J", "magenta", [ "h0" ] ],
-    [ "and7:OUT", "and9:B", "green", [ "v0" ] ],
-    [ "and8:OUT", "or13:B", "green", [ "v0" ] ],
-    [ "or13:A", "and7:OUT", "green", [ "h0" ] ],
-    [ "or14:B", "and7:OUT", "green", [ "h0" ] ],
-    [ "and6:OUT", "or12:B", "green", [ "v0" ] ],
-    [ "and6:OUT", "or15:A", "green", [ "v0", "h153.6", "v172.8" ] ],
-    [ "and5:OUT", "or15:B", "green", [ "v0", "h38.4", "v259.2" ] ],
-    [ "and9:A", "not3:OUT", "green", [ "h-153.6" ] ],
-    [ "or2:B", "not1:OUT", "green", [ "h-48", "v9.6", "h-153.6", "v19.2", "h-9.6" ] ],
-    [ "or3:B", "j4:J", "green", [ "h-211.2", "v19.2", "h-163.2", "v19.2", "h-124.8" ] ],
-    [ "or12:A", "j5:J", "magenta", [ "h0", "v-28.8", "h76.8", "v-307.2" ] ],
-    [ "and5:OUT", "or9:B", "green", [ "v-28.8", "h28.8" ] ],
-    [ "or9:A", "and2:OUT", "green", [ "h0" ] ],
-    [ "or11:B", "not2:OUT", "green", [ "h0", "v38.4" ] ],
-    [ "or11:A", "j2:J", "cyan", [ "h-19.2", "v9.6", "h-278.4" ] ],
-    [ "or10:B", "and4:OUT", "green", [ "h0" ] ],
-    [ "or10:A", "and3:OUT", "green", [ "h0" ] ],
-    [ "j2:J", "and1:A", "cyan", [ "v0" ] ],
-    [ "j4:J", "and1:B", "green", [ "v0" ] ],
-    [ "and2:A", "not1:OUT", "green", [ "h0" ] ],
-    [ "and2:B", "not3:OUT", "green", [ "h0" ] ],
-    [ "and3:A", "not3:OUT", "green", [ "h0" ] ],
-    [ "and3:B", "not2:OUT", "green", [ "h0" ] ],
-    [ "j3:J", "and4:A", "gold", [ "v0" ] ],
-    [ "j4:J", "and4:B", "green", [ "v0" ] ],
-    [ "j3:J", "and5:A", "gold", [ "v0" ] ],
-    [ "and5:B", "not3:OUT", "green", [ "h0" ] ],
-    [ "and6:A", "not1:OUT", "green", [ "h0" ] ],
-    [ "j3:J", "and6:B", "gold", [ "v0" ] ],
-    [ "and7:A", "not2:OUT", "green", [ "h0" ] ],
-    [ "j2:J", "and7:B", "cyan", [ "v0" ] ],
-    [ "and8:A", "not3:OUT", "green", [ "h0" ] ],
-    [ "j2:J", "and8:B", "cyan", [ "v0" ] ]
+    [ "flop3:Q", "flop2:CLK", "green", [ "v0" ] ],
+    [ "flop3:NOTQ", "flop3:D", "green", [ "v0" ] ],
+    [ "flop2:NOTQ", "flop2:D", "green", [ "v0" ] ],
+    [ "flop2:Q", "flop1:CLK", "green", [ "v0" ] ],
+    [ "flop1:Q", "flop4:CLK", "green", [ "v0" ] ],
+    [ "flop1:NOTQ", "flop1:D", "green", [ "v0" ] ],
+    [ "flop4:NOTQ", "flop4:D", "green", [ "v0" ] ],
+    [ "flop3:NOTQ", "not1:IN", "green", [ "v0" ] ],
+    [ "flop2:NOTQ", "not2:IN", "green", [ "v0" ] ],
+    [ "flop1:NOTQ", "not3:IN", "green", [ "v0" ] ],
+    [ "not4:IN", "flop4:NOTQ", "green", [ "v0" ] ],
+    [ "not4:OUT", "and1:A", "green", [ "v0" ] ],
+    [ "and1:OUT", "and2:A", "green", [ "v0" ] ],
+    [ "xor2:OUT", "and2:B", "green", [ "v0" ] ],
+    [ "flop1:NOTQ", "xor2:A", "green", [ "v0" ] ],
+    [ "flop3:NOTQ", "xor2:B", "green", [ "v0" ] ],
+    [ "and2:OUT", "not5:IN", "green", [ "v0" ] ],
+    [ "not2:OUT", "and1:B", "green", [ "v0" ] ],
+    [ "and3:OUT", "and4:A", "green", [ "v0" ] ],
+    [ "xor3:OUT", "and4:B", "green", [ "v0" ] ],
+    [ "and4:OUT", "not6:IN", "green", [ "v0" ] ],
+    [ "not4:OUT", "and3:A", "green", [ "v0" ] ],
+    [ "and3:B", "flop1:NOTQ", "green", [ "h0" ] ],
+    [ "flop2:NOTQ", "xor3:A", "green", [ "v0" ] ],
+    [ "flop3:NOTQ", "xor3:B", "green", [ "v0" ] ],
+    [ "and5:OUT", "and7:A", "green", [ "v0" ] ],
+    [ "and6:OUT", "and7:B", "green", [ "v0" ] ],
+    [ "and7:OUT", "not7:IN", "green", [ "v0" ] ],
+    [ "not4:OUT", "and5:A", "green", [ "v0" ] ],
+    [ "not3:OUT", "and5:B", "green", [ "v0" ] ],
+    [ "flop2:NOTQ", "and6:A", "green", [ "v0" ] ],
+    [ "not1:OUT", "and6:B", "green", [ "v0" ] ],
+    [ "or1:OUT", "not8:IN", "green", [ "v0" ] ],
+    [ "or2:OUT", "or1:B", "green", [ "v0" ] ],
+    [ "and8:OUT", "or2:A", "green", [ "v0" ] ],
+    [ "and9:OUT", "or2:B", "green", [ "v0" ] ],
+    [ "and12:OUT", "and9:A", "green", [ "v0" ] ],
+    [ "and13:OUT", "and9:B", "green", [ "v0" ] ],
+    [ "and11:OUT", "and8:B", "green", [ "v0" ] ],
+    [ "and8:A", "and10:OUT", "green", [ "v0" ] ],
+    [ "not4:OUT", "and10:A", "green", [ "v0" ] ],
+    [ "not3:OUT", "and10:B", "green", [ "v0" ] ],
+    [ "not2:OUT", "and11:A", "green", [ "v0" ] ],
+    [ "flop3:NOTQ", "and11:B", "green", [ "v0" ] ],
+    [ "not4:OUT", "and12:A", "green", [ "v0" ] ],
+    [ "flop1:NOTQ", "and12:B", "green", [ "v0" ] ],
+    [ "not2:OUT", "and13:A", "green", [ "v0" ] ],
+    [ "not1:OUT", "and13:B", "green", [ "v0" ] ],
+    [ "and16:OUT", "and14:B", "green", [ "v0" ] ],
+    [ "and14:A", "and15:OUT", "green", [ "v0" ] ],
+    [ "not4:OUT", "and15:A", "green", [ "v0" ] ],
+    [ "and15:B", "flop1:NOTQ", "green", [ "h0" ] ],
+    [ "and16:A", "flop2:NOTQ", "green", [ "h0" ] ],
+    [ "and16:B", "flop3:NOTQ", "green", [ "h0" ] ],
+    [ "and14:OUT", "or1:A", "green", [ "v0" ] ],
+    [ "and19:OUT", "and17:B", "green", [ "v0" ] ],
+    [ "and17:A", "and18:OUT", "green", [ "v0" ] ],
+    [ "and22:OUT", "and20:B", "green", [ "v0" ] ],
+    [ "and20:A", "and21:OUT", "green", [ "v0" ] ],
+    [ "and23:A", "and24:OUT", "green", [ "v0" ] ],
+    [ "not4:OUT", "and18:A", "green", [ "v0" ] ],
+    [ "flop4:NOTQ", "and21:A", "green", [ "v0" ] ],
+    [ "not4:OUT", "and24:A", "green", [ "v0" ] ],
+    [ "not3:OUT", "and24:B", "green", [ "v0" ] ],
+    [ "not1:OUT", "and23:B", "green", [ "v0" ] ],
+    [ "and20:OUT", "or3:B", "green", [ "v0" ] ],
+    [ "and17:OUT", "or3:A", "green", [ "v0" ] ],
+    [ "and23:OUT", "or4:B", "green", [ "v0" ] ],
+    [ "or4:A", "or3:OUT", "green", [ "h0" ] ],
+    [ "flop1:NOTQ", "and18:B", "green", [ "v0" ] ],
+    [ "and19:A", "flop2:NOTQ", "green", [ "h0" ] ],
+    [ "and19:B", "not1:OUT", "green", [ "h0" ] ],
+    [ "and21:B", "not3:OUT", "green", [ "h0" ] ],
+    [ "and22:A", "not2:OUT", "green", [ "h0" ] ],
+    [ "and22:B", "not1:OUT", "green", [ "h0" ] ],
+    [ "and27:OUT", "and25:B", "green", [ "v0" ] ],
+    [ "and25:A", "and26:OUT", "green", [ "v0" ] ],
+    [ "and30:OUT", "and28:B", "green", [ "v0" ] ],
+    [ "and28:A", "and29:OUT", "green", [ "v0" ] ],
+    [ "and31:A", "and32:OUT", "green", [ "v0" ] ],
+    [ "and28:OUT", "or5:B", "green", [ "v0" ] ],
+    [ "and25:OUT", "or5:A", "green", [ "v0" ] ],
+    [ "and31:OUT", "or6:B", "green", [ "v0" ] ],
+    [ "or6:A", "or5:OUT", "green", [ "h0" ] ],
+    [ "and32:A", "not4:OUT", "green", [ "v0" ] ],
+    [ "and26:A", "not4:OUT", "green", [ "h0" ] ],
+    [ "and29:A", "not4:OUT", "green", [ "v0" ] ],
+    [ "and32:B", "not3:OUT", "green", [ "v0" ] ],
+    [ "and31:B", "flop2:NOTQ", "green", [ "h0" ] ],
+    [ "and26:B", "not3:OUT", "green", [ "h0" ] ],
+    [ "and27:A", "not2:OUT", "green", [ "h0" ] ],
+    [ "and27:B", "flop3:NOTQ", "green", [ "v0" ] ],
+    [ "and30:A", "flop2:NOTQ", "green", [ "v0" ] ],
+    [ "and29:B", "flop1:NOTQ", "green", [ "h0" ] ],
+    [ "and30:B", "flop3:NOTQ", "green", [ "h0" ] ],
+    [ "and33:A", "and34:OUT", "green", [ "v0" ] ],
+    [ "not4:OUT", "and34:A", "green", [ "v0" ] ],
+    [ "and34:B", "not3:OUT", "green", [ "h0" ] ],
+    [ "and33:B", "not2:OUT", "green", [ "h0" ] ],
+    [ "and37:OUT", "and35:B", "green", [ "v0" ] ],
+    [ "and35:A", "and36:OUT", "green", [ "v0" ] ],
+    [ "and36:A", "not4:OUT", "green", [ "h0" ] ],
+    [ "and36:B", "flop1:NOTQ", "green", [ "h0" ] ],
+    [ "and37:A", "flop2:NOTQ", "green", [ "h0" ] ],
+    [ "and37:B", "flop3:NOTQ", "green", [ "h0" ] ],
+    [ "and33:OUT", "or7:A", "green", [ "v0" ] ],
+    [ "and35:OUT", "or7:B", "green", [ "v0" ] ],
+    [ "or6:OUT", "not9:IN", "green", [ "v0" ] ],
+    [ "not10:IN", "or7:OUT", "green", [ "v0" ] ],
+    [ "not5:OUT", "ttout:OUT0", "green", [ "v0" ] ],
+    [ "not6:OUT", "ttout:OUT1", "green", [ "v0" ] ],
+    [ "not7:OUT", "ttout:OUT2", "green", [ "v0" ] ],
+    [ "not8:OUT", "ttout:OUT3", "green", [ "v0" ] ],
+    [ "or4:OUT", "ttout:OUT4", "green", [ "v0" ] ],
+    [ "not9:OUT", "ttout:OUT5", "green", [ "v0" ] ],
+    [ "not10:OUT", "ttout:OUT6", "green", [ "v0" ] ],
+    [ "flop3:CLK", "ttin:CLK", "green", [ "v0" ] ]
   ],
   "dependencies": {}
 }
\ No newline at end of file