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feat: update project tt_um_wokwi_414120201832165377 from Eliana00S/IC
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Commit: f6f1a1019f98348a1e3ef5c217eadf540cdeddac
Workflow: https://github.com/Eliana00S/IC/actions/runs/11767305617
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TinyTapeoutBot authored and urish committed Nov 10, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_414120201832165377/commit_id.json
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/Eliana00S/IC",
"commit": "5c117a1c90c1bfffc53dcb146d65fe0303741b61",
"workflow_url": "https://github.com/Eliana00S/IC/actions/runs/11760818152",
"commit": "f6f1a1019f98348a1e3ef5c217eadf540cdeddac",
"workflow_url": "https://github.com/Eliana00S/IC/actions/runs/11767305617",
"sort_id": 1731202083305,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_414120201832165377/docs/info.md
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,10 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

The letter E.
Depending on weather the input is odd or even the green LED will light up for odd and the red for even.
## How to test

Turn all inputs on.
Turn on different outputs to see if they are odd or even with the different LEDs.
## External hardware

None
16 changes: 8 additions & 8 deletions projects/tt_um_wokwi_414120201832165377/info.yaml
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
# Tiny Tapeout project information (Wokwi project)
project:
wokwi_id: 414120201832165377 # Set this to the ID of your Wokwi project (the number from the project's URL)
title: "Initial" # Project title
title: "Odd or even" # Project title
author: "Eliana" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "e" # One line description of what your project does
description: "odd or even input" # One line description of what your project does
language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable)

Expand All @@ -26,12 +26,12 @@ pinout:

# Outputs
uo[0]: "OUT0"
uo[1]: "OUT1"
uo[2]: "OUT2"
uo[3]: "OUT3"
uo[4]: "OUT4"
uo[5]: "OUT5"
uo[6]: "OUT6"
uo[1]: ""
uo[2]: ""
uo[3]: ""
uo[4]: ""
uo[5]: ""
uo[6]: ""
uo[7]: "OUT7"

# Bidirectional pins
Expand Down
112 changes: 55 additions & 57 deletions projects/tt_um_wokwi_414120201832165377/stats/metrics.csv
Original file line number Diff line number Diff line change
@@ -1,23 +1,23 @@
Metric,Value
design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,2
design__lint_warning__count,4
design__inferred_latch__count,0
design__instance__count,253
design__instance__area,401.635
design__instance__count,263
design__instance__area,446.678
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,8.74460170052771E-7
power__switching__total,0.0000027653868528432213
power__leakage__total,1.3719878566575971E-9
power__total,0.000003641218881966779
power__internal__total,7.550403893219482E-7
power__switching__total,5.862190164407366E-7
power__leakage__total,1.3054839431703158E-9
power__total,0.0000013425648148768232
clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0
timing__hold__ws__corner:nom_tt_025C_1v80,7.93361043760663
timing__setup__ws__corner:nom_tt_025C_1v80,11.44261873197206
timing__hold__ws__corner:nom_tt_025C_1v80,8.165797158472905
timing__setup__ws__corner:nom_tt_025C_1v80,11.077431729886284
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
Expand All @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0
design__max_cap_violation__count__corner:nom_ss_100C_1v60,0
clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0
timing__hold__ws__corner:nom_ss_100C_1v60,8.093013599455281
timing__setup__ws__corner:nom_ss_100C_1v60,11.188837728576885
timing__hold__ws__corner:nom_ss_100C_1v60,8.497735200476862
timing__setup__ws__corner:nom_ss_100C_1v60,10.325319558277773
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
Expand All @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0
timing__hold__ws__corner:nom_ff_n40C_1v95,7.869721985713872
timing__setup__ws__corner:nom_ff_n40C_1v95,11.538793358512452
timing__hold__ws__corner:nom_ff_n40C_1v95,8.032794212718072
timing__setup__ws__corner:nom_ff_n40C_1v95,11.332485492992882
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
Expand All @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0
design__max_cap_violation__count,0
clock__skew__worst_hold,0.0
clock__skew__worst_setup,0.0
timing__hold__ws,7.868489194032462
timing__setup__ws,11.187646681282382
timing__hold__ws,8.031381120812364
timing__setup__ws,10.323029834247029
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
Expand All @@ -86,12 +86,12 @@ flow__errors__count,0
design__io,45
design__die__area,17954.7
design__core__area,16493.3
design__instance__count__stdcell,253
design__instance__area__stdcell,401.635
design__instance__count__stdcell,263
design__instance__area__stdcell,446.678
design__instance__count__macros,0
design__instance__area__macros,0
design__instance__utilization,0.0243514
design__instance__utilization__stdcell,0.0243514
design__instance__utilization,0.0270824
design__instance__utilization__stdcell,0.0270824
design__power_grid_violation__count__net:VGND,0
design__power_grid_violation__count__net:VPWR,0
design__power_grid_violation__count,0
Expand All @@ -100,40 +100,38 @@ timing__drv__floating__pins,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,498.961
route__wirelength__estimated,327.252
design__violations,0
design__instance__count__setup_buffer,0
design__instance__count__hold_buffer,0
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,47
route__net,57
route__net__special,2
route__drc_errors__iter:1,26
route__wirelength__iter:1,506
route__drc_errors__iter:2,0
route__wirelength__iter:2,471
route__drc_errors__iter:1,0
route__wirelength__iter:1,294
route__drc_errors,0
route__wirelength,471
route__vias,144
route__vias__singlecut,144
route__wirelength,294
route__vias,172
route__vias__singlecut,172
route__vias__multicut,0
design__disconnected_pin__count,11
design__critical_disconnected_pin__count,0
route__wirelength__max,50.05
timing__unannotated_net__count__corner:nom_tt_025C_1v80,31
route__wirelength__max,63.43
timing__unannotated_net__count__corner:nom_tt_025C_1v80,47
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,31
timing__unannotated_net__count__corner:nom_ss_100C_1v60,47
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,31
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,47
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,0
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0
timing__hold__ws__corner:min_tt_025C_1v80,7.931925563096807
timing__setup__ws__corner:min_tt_025C_1v80,11.443456284245524
timing__hold__ws__corner:min_tt_025C_1v80,8.164028795189271
timing__setup__ws__corner:min_tt_025C_1v80,11.078460240525384
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
Expand All @@ -144,15 +142,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,31
timing__unannotated_net__count__corner:min_tt_025C_1v80,47
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,0
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0
timing__hold__ws__corner:min_ss_100C_1v60,8.088729026637472
timing__setup__ws__corner:min_ss_100C_1v60,11.190051868510954
timing__hold__ws__corner:min_ss_100C_1v60,8.495105304101752
timing__setup__ws__corner:min_ss_100C_1v60,10.326928937619787
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
Expand All @@ -163,15 +161,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__unannotated_net__count__corner:min_ss_100C_1v60,31
timing__unannotated_net__count__corner:min_ss_100C_1v60,47
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0
timing__hold__ws__corner:min_ff_n40C_1v95,7.868489194032462
timing__setup__ws__corner:min_ff_n40C_1v95,11.539438176063392
timing__hold__ws__corner:min_ff_n40C_1v95,8.031381120812364
timing__setup__ws__corner:min_ff_n40C_1v95,11.333313275303455
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
Expand All @@ -182,15 +180,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_ff_n40C_1v95,31
timing__unannotated_net__count__corner:min_ff_n40C_1v95,47
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,0
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0
clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0
timing__hold__ws__corner:max_tt_025C_1v80,7.934981785125431
timing__setup__ws__corner:max_tt_025C_1v80,11.441827364977724
timing__hold__ws__corner:max_tt_025C_1v80,8.167379892461573
timing__setup__ws__corner:max_tt_025C_1v80,11.075984887199672
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
Expand All @@ -201,15 +199,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,31
timing__unannotated_net__count__corner:max_tt_025C_1v80,47
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,0
design__max_fanout_violation__count__corner:max_ss_100C_1v60,0
design__max_cap_violation__count__corner:max_ss_100C_1v60,0
clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0
clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0
timing__hold__ws__corner:max_ss_100C_1v60,8.095231381031995
timing__setup__ws__corner:max_ss_100C_1v60,11.187646681282382
timing__hold__ws__corner:max_ss_100C_1v60,8.49999206190515
timing__setup__ws__corner:max_ss_100C_1v60,10.323029834247029
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
Expand All @@ -220,15 +218,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,31
timing__unannotated_net__count__corner:max_ss_100C_1v60,47
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0
clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0
timing__hold__ws__corner:max_ff_n40C_1v95,7.870815333379444
timing__setup__ws__corner:max_ff_n40C_1v95,11.53805794676014
timing__hold__ws__corner:max_ff_n40C_1v95,8.034078518749281
timing__setup__ws__corner:max_ff_n40C_1v95,11.331384151721306
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
Expand All @@ -239,19 +237,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_ff_n40C_1v95,31
timing__unannotated_net__count__corner:max_ff_n40C_1v95,47
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,31
timing__unannotated_net__count,47
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000392941
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000395864
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,7.01886E-8
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000395864
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000014815
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000166809
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,2.58364E-8
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000166809
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,6.560000000000000507828913469399179092533813673071563243865966796875E-8
ir__drop__worst,0.000003929999999999999642165578184194174582444247789680957794189453125
ir__drop__avg,2.6099999999999998792455939053934466098638722542091272771358489990234375E-8
ir__drop__worst,0.000001480000000000000017730500227741696761540879379026591777801513671875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
Expand Down
54 changes: 27 additions & 27 deletions projects/tt_um_wokwi_414120201832165377/stats/synthesis-stats.txt
Original file line number Diff line number Diff line change
@@ -1,53 +1,53 @@
62. Printing statistics.

=== not_cell ===
=== or_cell ===

Number of wires: 2
Number of wire bits: 2
Number of public wires: 2
Number of public wire bits: 2
Number of wires: 3
Number of wire bits: 3
Number of public wires: 3
Number of public wire bits: 3
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 1
sky130_fd_sc_hd__inv_2 1
sky130_fd_sc_hd__or2_2 1

Chip area for module '\not_cell': 3.753600
Chip area for module '\or_cell': 6.256000

=== tt_um_wokwi_414120201832165377 ===

Number of wires: 10
Number of wire bits: 45
Number of public wires: 10
Number of public wire bits: 45
Number of wires: 14
Number of wire bits: 49
Number of public wires: 14
Number of public wire bits: 49
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 26
not_cell 2
sky130_fd_sc_hd__buf_2 8
sky130_fd_sc_hd__conb_1 16
Number of cells: 30
or_cell 6
sky130_fd_sc_hd__buf_2 2
sky130_fd_sc_hd__conb_1 22

Area for cell type \not_cell is unknown!
Area for cell type \or_cell is unknown!

Chip area for module '\tt_um_wokwi_414120201832165377': 100.096000
Chip area for module '\tt_um_wokwi_414120201832165377': 92.588800

=== design hierarchy ===

tt_um_wokwi_414120201832165377 1
not_cell 2
or_cell 6

Number of wires: 14
Number of wire bits: 49
Number of public wires: 14
Number of public wire bits: 49
Number of wires: 32
Number of wire bits: 67
Number of public wires: 32
Number of public wire bits: 67
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 26
sky130_fd_sc_hd__buf_2 8
sky130_fd_sc_hd__conb_1 16
sky130_fd_sc_hd__inv_2 2
Number of cells: 30
sky130_fd_sc_hd__buf_2 2
sky130_fd_sc_hd__conb_1 22
sky130_fd_sc_hd__or2_2 6

Chip area for top module '\tt_um_wokwi_414120201832165377': 107.603200
Chip area for top module '\tt_um_wokwi_414120201832165377': 130.124800

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