From bc7b9b8a58ff44a3636815ef9d525a3af35e4086 Mon Sep 17 00:00:00 2001 From: TinyTapeoutBot <139130078+TinyTapeoutBot@users.noreply.github.com> Date: Sun, 10 Nov 2024 06:37:43 +0200 Subject: [PATCH] feat: update project tt_um_wokwi_413923150973445121 from MarianoMunoz/tt00-wowki-design Commit: d0a76e4311028c478f725d4c6854c3f4a047324a Workflow: https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11761518106 --- .../commit_id.json | 4 +- .../stats/metrics.csv | 138 ++-- .../stats/synthesis-stats.txt | 93 ++- .../tt_um_wokwi_413923150973445121.gds | Bin 385822 -> 447358 bytes .../tt_um_wokwi_413923150973445121.lef | 117 ++-- .../tt_um_wokwi_413923150973445121.v | 642 ++++++++++++------ .../wokwi-diagram.json | 202 +++++- 7 files changed, 799 insertions(+), 397 deletions(-) diff --git a/projects/tt_um_wokwi_413923150973445121/commit_id.json b/projects/tt_um_wokwi_413923150973445121/commit_id.json index 08c9f397..342bd84b 100644 --- a/projects/tt_um_wokwi_413923150973445121/commit_id.json +++ b/projects/tt_um_wokwi_413923150973445121/commit_id.json @@ -1,8 +1,8 @@ { "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/MarianoMunoz/tt00-wowki-design", - "commit": "0a9fe0f8af23e73b83e2dbb88da4bd3c1b55d331", - "workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11729901102", + "commit": "d0a76e4311028c478f725d4c6854c3f4a047324a", + "workflow_url": "https://github.com/MarianoMunoz/tt00-wowki-design/actions/runs/11761518106", "sort_id": 1731012978166, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv b/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv index a0374cfd..ae8e3f9a 100644 --- a/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv +++ b/projects/tt_um_wokwi_413923150973445121/stats/metrics.csv @@ -3,21 +3,21 @@ design__lint_error__count,0 design__lint_timing_construct__count,0 design__lint_warning__count,0 design__inferred_latch__count,0 -design__instance__count,255 -design__instance__area,410.394 +design__instance__count,287 +design__instance__area,659.382 design__instance_unmapped__count,0 synthesis__check_error__count,0 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 -power__internal__total,7.980143550412322E-7 -power__switching__total,0.000001861507371359039 -power__leakage__total,1.3475258686668212E-9 -power__total,0.000002660869085957529 +power__internal__total,0.0000023479888113797642 +power__switching__total,0.0 +power__leakage__total,1.6269392499879132E-9 +power__total,0.0000023496156700275606 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0 -timing__hold__ws__corner:nom_tt_025C_1v80,7.932996706301259 -timing__setup__ws__corner:nom_tt_025C_1v80,11.357979767072983 +timing__hold__ws__corner:nom_tt_025C_1v80,0.6856978512409907 +timing__setup__ws__corner:nom_tt_025C_1v80,14.092686527742975 timing__hold__tns__corner:nom_tt_025C_1v80,0.0 timing__setup__tns__corner:nom_tt_025C_1v80,0.0 timing__hold__wns__corner:nom_tt_025C_1v80,0 @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0 -timing__hold__ws__corner:nom_ss_100C_1v60,8.10584156073381 -timing__setup__ws__corner:nom_ss_100C_1v60,10.98903399380873 +timing__hold__ws__corner:nom_ss_100C_1v60,1.6259736239867688 +timing__setup__ws__corner:nom_ss_100C_1v60,12.27398040167648 timing__hold__tns__corner:nom_ss_100C_1v60,0.0 timing__setup__tns__corner:nom_ss_100C_1v60,0.0 timing__hold__wns__corner:nom_ss_100C_1v60,0 @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0 -timing__hold__ws__corner:nom_ff_n40C_1v95,7.869280561026796 -timing__setup__ws__corner:nom_ff_n40C_1v95,11.492220833579895 +timing__hold__ws__corner:nom_ff_n40C_1v95,0.3602139799509259 +timing__setup__ws__corner:nom_ff_n40C_1v95,14.693426447000894 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 timing__hold__wns__corner:nom_ff_n40C_1v95,0 @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0 design__max_cap_violation__count,0 clock__skew__worst_hold,0.0 clock__skew__worst_setup,0.0 -timing__hold__ws,7.868014018564484 -timing__setup__ws,10.986471598995426 +timing__hold__ws,0.3602139799509259 +timing__setup__ws,12.273434171932918 timing__hold__tns,0.0 timing__setup__tns,0.0 timing__hold__wns,0 @@ -86,12 +86,12 @@ flow__errors__count,0 design__io,45 design__die__area,17954.7 design__core__area,16493.3 -design__instance__count__stdcell,255 -design__instance__area__stdcell,410.394 +design__instance__count__stdcell,287 +design__instance__area__stdcell,659.382 design__instance__count__macros,0 design__instance__area__macros,0 -design__instance__utilization,0.0248824 -design__instance__utilization__stdcell,0.0248824 +design__instance__utilization,0.0399788 +design__instance__utilization__stdcell,0.0399788 design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count__net:VPWR,0 design__power_grid_violation__count,0 @@ -100,40 +100,42 @@ timing__drv__floating__pins,0 design__instance__displacement__total,0 design__instance__displacement__mean,0 design__instance__displacement__max,0 -route__wirelength__estimated,378.852 +route__wirelength__estimated,574.535 design__violations,0 design__instance__count__setup_buffer,0 -design__instance__count__hold_buffer,0 +design__instance__count__hold_buffer,1 antenna__violating__nets,0 antenna__violating__pins,0 route__antenna_violation__count,0 -route__net,49 +route__net,81 route__net__special,2 -route__drc_errors__iter:1,31 -route__wirelength__iter:1,426 -route__drc_errors__iter:2,0 -route__wirelength__iter:2,386 +route__drc_errors__iter:1,36 +route__wirelength__iter:1,594 +route__drc_errors__iter:2,1 +route__wirelength__iter:2,548 +route__drc_errors__iter:3,0 +route__wirelength__iter:3,544 route__drc_errors,0 -route__wirelength,386 -route__vias,138 -route__vias__singlecut,138 +route__wirelength,544 +route__vias,302 +route__vias__singlecut,302 route__vias__multicut,0 -design__disconnected_pin__count,12 +design__disconnected_pin__count,18 design__critical_disconnected_pin__count,0 -route__wirelength__max,67.39 -timing__unannotated_net__count__corner:nom_tt_025C_1v80,37 -timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 -timing__unannotated_net__count__corner:nom_ss_100C_1v60,37 -timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 -timing__unannotated_net__count__corner:nom_ff_n40C_1v95,37 -timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 +route__wirelength__max,45.28 +timing__unannotated_net__count__corner:nom_tt_025C_1v80,74 +timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,1 +timing__unannotated_net__count__corner:nom_ss_100C_1v60,74 +timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,1 +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,74 +timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,1 design__max_slew_violation__count__corner:min_tt_025C_1v80,0 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0 design__max_cap_violation__count__corner:min_tt_025C_1v80,0 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0 -timing__hold__ws__corner:min_tt_025C_1v80,7.931241665694296 -timing__setup__ws__corner:min_tt_025C_1v80,11.359196571542386 +timing__hold__ws__corner:min_tt_025C_1v80,0.6856978512409907 +timing__setup__ws__corner:min_tt_025C_1v80,14.092873045216388 timing__hold__tns__corner:min_tt_025C_1v80,0.0 timing__setup__tns__corner:min_tt_025C_1v80,0.0 timing__hold__wns__corner:min_tt_025C_1v80,0 @@ -144,15 +146,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 timing__setup_vio__count__corner:min_tt_025C_1v80,0 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 -timing__unannotated_net__count__corner:min_tt_025C_1v80,37 -timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 +timing__unannotated_net__count__corner:min_tt_025C_1v80,74 +timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,1 design__max_slew_violation__count__corner:min_ss_100C_1v60,0 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0 design__max_cap_violation__count__corner:min_ss_100C_1v60,0 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0 -timing__hold__ws__corner:min_ss_100C_1v60,8.102571287699982 -timing__setup__ws__corner:min_ss_100C_1v60,10.990971999175326 +timing__hold__ws__corner:min_ss_100C_1v60,1.6259736239867688 +timing__setup__ws__corner:min_ss_100C_1v60,12.27428415870461 timing__hold__tns__corner:min_ss_100C_1v60,0.0 timing__setup__tns__corner:min_ss_100C_1v60,0.0 timing__hold__wns__corner:min_ss_100C_1v60,0 @@ -163,15 +165,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 timing__setup_vio__count__corner:min_ss_100C_1v60,0 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 -timing__unannotated_net__count__corner:min_ss_100C_1v60,37 -timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 +timing__unannotated_net__count__corner:min_ss_100C_1v60,74 +timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,1 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0 -timing__hold__ws__corner:min_ff_n40C_1v95,7.868014018564484 -timing__setup__ws__corner:min_ff_n40C_1v95,11.493163190909849 +timing__hold__ws__corner:min_ff_n40C_1v95,0.3602139799509259 +timing__setup__ws__corner:min_ff_n40C_1v95,14.693610299938971 timing__hold__tns__corner:min_ff_n40C_1v95,0.0 timing__setup__tns__corner:min_ff_n40C_1v95,0.0 timing__hold__wns__corner:min_ff_n40C_1v95,0 @@ -182,15 +184,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:min_ff_n40C_1v95,37 -timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 +timing__unannotated_net__count__corner:min_ff_n40C_1v95,74 +timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,1 design__max_slew_violation__count__corner:max_tt_025C_1v80,0 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0 design__max_cap_violation__count__corner:max_tt_025C_1v80,0 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0 -timing__hold__ws__corner:max_tt_025C_1v80,7.934230386161114 -timing__setup__ws__corner:max_tt_025C_1v80,11.35638903947831 +timing__hold__ws__corner:max_tt_025C_1v80,0.6856978512409907 +timing__setup__ws__corner:max_tt_025C_1v80,14.09233569725727 timing__hold__tns__corner:max_tt_025C_1v80,0.0 timing__setup__tns__corner:max_tt_025C_1v80,0.0 timing__hold__wns__corner:max_tt_025C_1v80,0 @@ -201,15 +203,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 timing__setup_vio__count__corner:max_tt_025C_1v80,0 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 -timing__unannotated_net__count__corner:max_tt_025C_1v80,37 -timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 +timing__unannotated_net__count__corner:max_tt_025C_1v80,74 +timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,1 design__max_slew_violation__count__corner:max_ss_100C_1v60,0 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0 design__max_cap_violation__count__corner:max_ss_100C_1v60,0 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0 -timing__hold__ws__corner:max_ss_100C_1v60,8.108038914206292 -timing__setup__ws__corner:max_ss_100C_1v60,10.986471598995426 +timing__hold__ws__corner:max_ss_100C_1v60,1.6259736239867688 +timing__setup__ws__corner:max_ss_100C_1v60,12.273434171932918 timing__hold__tns__corner:max_ss_100C_1v60,0.0 timing__setup__tns__corner:max_ss_100C_1v60,0.0 timing__hold__wns__corner:max_ss_100C_1v60,0 @@ -220,15 +222,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 timing__setup_vio__count__corner:max_ss_100C_1v60,0 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 -timing__unannotated_net__count__corner:max_ss_100C_1v60,37 -timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 +timing__unannotated_net__count__corner:max_ss_100C_1v60,74 +timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,1 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0 -timing__hold__ws__corner:max_ff_n40C_1v95,7.870254892780763 -timing__setup__ws__corner:max_ff_n40C_1v95,11.49101646360872 +timing__hold__ws__corner:max_ff_n40C_1v95,0.3602139799509259 +timing__setup__ws__corner:max_ff_n40C_1v95,14.693068511087631 timing__hold__tns__corner:max_ff_n40C_1v95,0.0 timing__setup__tns__corner:max_ff_n40C_1v95,0.0 timing__hold__wns__corner:max_ff_n40C_1v95,0 @@ -239,19 +241,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:max_ff_n40C_1v95,37 -timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count,37 -timing__unannotated_net_filtered__count,0 +timing__unannotated_net__count__corner:max_ff_n40C_1v95,74 +timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,1 +timing__unannotated_net__count,74 +timing__unannotated_net_filtered__count,1 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8 -design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000222258 -design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.000002214 -design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,5.0838E-8 -design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.000002214 +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000292441 +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000246238 +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.46096E-8 +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000246238 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 -ir__drop__avg,4.610000000000000251962960586861461909080617260769940912723541259765625E-8 -ir__drop__worst,0.0000022199999999999999207166319348250027587710064835846424102783203125 +ir__drop__avg,3.759999999999999919850151111101743683917675298289395868778228759765625E-8 +ir__drop__worst,0.0000029199999999999999949194286197329262222410761751234531402587890625 magic__drc_error__count,0 magic__illegal_overlap__count,0 design__lvs_device_difference__count,0 diff --git a/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt b/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt index 77b60fed..843a19e2 100644 --- a/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt +++ b/projects/tt_um_wokwi_413923150973445121/stats/synthesis-stats.txt @@ -14,40 +14,95 @@ Chip area for module '\and_cell': 7.507200 +=== dff_cell === + + Number of wires: 4 + Number of wire bits: 4 + Number of public wires: 4 + Number of public wire bits: 4 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 2 + sky130_fd_sc_hd__dfxtp_2 1 + sky130_fd_sc_hd__inv_2 1 + + Chip area for module '\dff_cell': 25.024000 + +=== not_cell === + + Number of wires: 2 + Number of wire bits: 2 + Number of public wires: 2 + Number of public wire bits: 2 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + sky130_fd_sc_hd__inv_2 1 + + Chip area for module '\not_cell': 3.753600 + +=== or_cell === + + Number of wires: 3 + Number of wire bits: 3 + Number of public wires: 3 + Number of public wire bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + sky130_fd_sc_hd__or2_2 1 + + Chip area for module '\or_cell': 6.256000 + === tt_um_wokwi_413923150973445121 === - Number of wires: 10 - Number of wire bits: 45 - Number of public wires: 10 - Number of public wire bits: 45 + Number of wires: 44 + Number of wire bits: 79 + Number of public wires: 44 + Number of public wire bits: 79 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - and_cell 2 - sky130_fd_sc_hd__buf_2 5 - sky130_fd_sc_hd__conb_1 19 + Number of cells: 57 + and_cell 9 + dff_cell 4 + not_cell 3 + or_cell 17 + sky130_fd_sc_hd__buf_2 7 + sky130_fd_sc_hd__conb_1 17 + Area for cell type \dff_cell is unknown! Area for cell type \and_cell is unknown! + Area for cell type \not_cell is unknown! + Area for cell type \or_cell is unknown! - Chip area for module '\tt_um_wokwi_413923150973445121': 96.342400 + Chip area for module '\tt_um_wokwi_413923150973445121': 98.844800 === design hierarchy === tt_um_wokwi_413923150973445121 1 - and_cell 2 + and_cell 9 + dff_cell 4 + not_cell 3 + or_cell 17 - Number of wires: 16 - Number of wire bits: 51 - Number of public wires: 16 - Number of public wire bits: 51 + Number of wires: 144 + Number of wire bits: 179 + Number of public wires: 144 + Number of public wire bits: 179 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - sky130_fd_sc_hd__and2_2 2 - sky130_fd_sc_hd__buf_2 5 - sky130_fd_sc_hd__conb_1 19 + Number of cells: 61 + sky130_fd_sc_hd__and2_2 9 + sky130_fd_sc_hd__buf_2 7 + sky130_fd_sc_hd__conb_1 17 + sky130_fd_sc_hd__dfxtp_2 4 + sky130_fd_sc_hd__inv_2 7 + sky130_fd_sc_hd__or2_2 17 - Chip area for top module '\tt_um_wokwi_413923150973445121': 111.356800 + Chip area for top module '\tt_um_wokwi_413923150973445121': 384.118400 diff --git a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.gds b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.gds index 1a17d23edf9ba718fe35f0b9eaae52cb6dbd3e36..bf81d078c404c4dc57eea9f2c047b7b36deaa98e 100644 GIT binary patch delta 64535 zcma%^2bfmH_5a^{w*pHq3kxi;$kJh#j-V`xiUNX)6%|laK&na;l#Y#ll}l3*6|qGW zz7VSL0_6gO~w)a0M z+WBmggV~9#BsXgHc*~tH7mv?PY{>iQ_M)9CFr z-llI<(L67Dc50hw+uco~XD7AE&2N;+~q(Ysqj2PQR$ z#$=6*DvI->cS>)M`m8O8ep~mLC?Bley7nnU>ttmz`AagHYIkKaxsyHfdcx;8RbgXTI0;%=giVMvbBa%UgHsM1Pqzu>S=8KRk0f ztKAs>6dml+Q1w|~t1kNoPwHqlLO-ojQAzF|gg+PmuJFungGPW|866x`TpCoM^z$`h zV~EITHwNb?9`pCBM`JZK7CkDXLxsg9!D(oZ?pmjW@8C1-!f4BA$mStuTNF~7;_Hyn zE{s}^EiMf|fC=$st@LDEv>Su-*A8mh3QfS`*aZnu9Giy4W_^ufTeNvz-Q-O1q?>Hm zjauE(?3d9{^R=&y)!IV}yD@)0TSlZZWUfZ*aOjY4s5D_mNSn68P-Ju*@(B?ghbW`W z`Ie1S%2^dIg_Az}qa7U^j=GRTF8n`ezX8wll%a+p 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zW6m2raVj>|TIjG1MA2`0J7`i|llPhUh()u5Wo!MZGB7!a2JDY1!Xc_uq^Wq);cJtCkCkMA*=5~=;zLYJ5!=+YWJXC~+PVVBhP80^ed zxFm0YOB(vr95XbLT>d!RC5A5C;2*AsuEaS){fVTzdd?*cP5#g>Bfir*P3WY5i`HpE zm$MN%`k5hdwfVV$NVUtT?@n*Tsr6sW;h~WrNh&)!3I;zcrIt+1Mpb2HBaI zR7^rzqf#xA5x=^mdGW)}gtUy7Y8Uok1Rj@BE@?>)!Okp=pruM{)Xzvxz2=f6Kf=z0 VwD2AOv+CBMzkTqhE&c^{{vX41s=NRI diff --git a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef index a53fa585..e42b9d1b 100644 --- a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef +++ b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.lef @@ -50,6 +50,7 @@ MACRO tt_um_wokwi_413923150973445121 PIN clk DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.159000 ; PORT LAYER met4 ; RECT 143.830 110.520 144.130 111.520 ; @@ -74,7 +75,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[0] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 138.310 110.520 138.610 111.520 ; @@ -83,7 +83,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[1] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 135.550 110.520 135.850 111.520 ; @@ -92,7 +91,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[2] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 132.790 110.520 133.090 111.520 ; @@ -101,7 +99,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[3] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 130.030 110.520 130.330 111.520 ; @@ -118,7 +115,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[5] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; PORT LAYER met4 ; RECT 124.510 110.520 124.810 111.520 ; @@ -127,7 +123,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[6] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; PORT LAYER met4 ; RECT 121.750 110.520 122.050 111.520 ; @@ -136,7 +131,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN ui_in[7] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; PORT LAYER met4 ; RECT 118.990 110.520 119.290 111.520 ; @@ -337,7 +331,7 @@ MACRO tt_um_wokwi_413923150973445121 PIN uo_out[0] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.795200 ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 94.150 110.520 94.450 111.520 ; @@ -346,7 +340,7 @@ MACRO tt_um_wokwi_413923150973445121 PIN uo_out[1] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.795200 ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 91.390 110.520 91.690 111.520 ; @@ -355,6 +349,7 @@ MACRO tt_um_wokwi_413923150973445121 PIN uo_out[2] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 88.630 110.520 88.930 111.520 ; @@ -363,6 +358,7 @@ MACRO tt_um_wokwi_413923150973445121 PIN uo_out[3] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 85.870 110.520 86.170 111.520 ; @@ -371,6 +367,7 @@ MACRO tt_um_wokwi_413923150973445121 PIN uo_out[4] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 83.110 110.520 83.410 111.520 ; @@ -397,7 +394,6 @@ MACRO tt_um_wokwi_413923150973445121 PIN uo_out[7] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 74.830 110.520 75.130 111.520 ; @@ -411,56 +407,59 @@ MACRO tt_um_wokwi_413923150973445121 LAYER met1 ; RECT 2.760 2.480 158.240 109.040 ; LAYER met2 ; - RECT 18.310 2.535 141.130 110.685 ; + RECT 18.310 2.535 143.890 110.005 ; LAYER met3 ; - RECT 18.290 2.555 141.155 110.665 ; - LAYER met4 ; - RECT 31.370 110.120 33.030 110.665 ; - RECT 34.130 110.120 35.790 110.665 ; - RECT 36.890 110.120 38.550 110.665 ; - RECT 39.650 110.120 41.310 110.665 ; - RECT 42.410 110.120 44.070 110.665 ; - RECT 45.170 110.120 46.830 110.665 ; - RECT 47.930 110.120 49.590 110.665 ; - RECT 50.690 110.120 52.350 110.665 ; - RECT 53.450 110.120 55.110 110.665 ; - RECT 56.210 110.120 57.870 110.665 ; - RECT 58.970 110.120 60.630 110.665 ; - RECT 61.730 110.120 63.390 110.665 ; - RECT 64.490 110.120 66.150 110.665 ; - RECT 67.250 110.120 68.910 110.665 ; - RECT 70.010 110.120 71.670 110.665 ; - RECT 72.770 110.120 74.430 110.665 ; - RECT 75.530 110.120 77.190 110.665 ; - RECT 78.290 110.120 79.950 110.665 ; - RECT 81.050 110.120 82.710 110.665 ; - RECT 83.810 110.120 85.470 110.665 ; - RECT 86.570 110.120 88.230 110.665 ; - RECT 89.330 110.120 90.990 110.665 ; - RECT 92.090 110.120 93.750 110.665 ; - RECT 94.850 110.120 96.510 110.665 ; - RECT 97.610 110.120 99.270 110.665 ; - RECT 100.370 110.120 102.030 110.665 ; - RECT 103.130 110.120 104.790 110.665 ; - RECT 105.890 110.120 107.550 110.665 ; - RECT 108.650 110.120 110.310 110.665 ; - RECT 111.410 110.120 113.070 110.665 ; - RECT 114.170 110.120 115.830 110.665 ; - RECT 116.930 110.120 118.590 110.665 ; - RECT 119.690 110.120 121.350 110.665 ; - RECT 122.450 110.120 124.110 110.665 ; - RECT 125.210 110.120 126.870 110.665 ; - RECT 127.970 110.120 129.630 110.665 ; - RECT 130.730 110.120 132.390 110.665 ; - RECT 133.490 110.120 135.150 110.665 ; - RECT 136.250 110.120 137.910 110.665 ; - RECT 30.655 109.440 138.625 110.120 ; - RECT 30.655 94.015 56.750 109.440 ; - RECT 59.150 94.015 60.050 109.440 ; - RECT 62.450 94.015 95.620 109.440 ; - RECT 98.020 94.015 98.920 109.440 ; - RECT 101.320 94.015 134.490 109.440 ; - RECT 136.890 94.015 137.790 109.440 ; + RECT 18.290 2.555 144.370 109.985 ; + LAYER met4 ; + RECT 31.370 110.120 33.030 110.520 ; + RECT 34.130 110.120 35.790 110.520 ; + RECT 36.890 110.120 38.550 110.520 ; + RECT 39.650 110.120 41.310 110.520 ; + RECT 42.410 110.120 44.070 110.520 ; + RECT 45.170 110.120 46.830 110.520 ; + RECT 47.930 110.120 49.590 110.520 ; + RECT 50.690 110.120 52.350 110.520 ; + RECT 53.450 110.120 55.110 110.520 ; + RECT 56.210 110.120 57.870 110.520 ; + RECT 58.970 110.120 60.630 110.520 ; + RECT 61.730 110.120 63.390 110.520 ; + RECT 64.490 110.120 66.150 110.520 ; + RECT 67.250 110.120 68.910 110.520 ; + RECT 70.010 110.120 71.670 110.520 ; + RECT 72.770 110.120 74.430 110.520 ; + RECT 75.530 110.120 77.190 110.520 ; + RECT 78.290 110.120 79.950 110.520 ; + RECT 81.050 110.120 82.710 110.520 ; + RECT 83.810 110.120 85.470 110.520 ; + RECT 86.570 110.120 88.230 110.520 ; + RECT 89.330 110.120 90.990 110.520 ; + RECT 92.090 110.120 93.750 110.520 ; + RECT 94.850 110.120 96.510 110.520 ; + RECT 97.610 110.120 99.270 110.520 ; + RECT 100.370 110.120 102.030 110.520 ; + RECT 103.130 110.120 104.790 110.520 ; + RECT 105.890 110.120 107.550 110.520 ; + RECT 108.650 110.120 110.310 110.520 ; + RECT 111.410 110.120 113.070 110.520 ; + RECT 114.170 110.120 115.830 110.520 ; + RECT 116.930 110.120 118.590 110.520 ; + RECT 119.690 110.120 121.350 110.520 ; + RECT 122.450 110.120 124.110 110.520 ; + RECT 125.210 110.120 126.870 110.520 ; + RECT 127.970 110.120 129.630 110.520 ; + RECT 130.730 110.120 132.390 110.520 ; + RECT 133.490 110.120 135.150 110.520 ; + RECT 136.250 110.120 137.910 110.520 ; + RECT 139.010 110.120 140.670 110.520 ; + RECT 141.770 110.120 143.430 110.520 ; + RECT 30.655 109.440 144.145 110.120 ; + RECT 30.655 107.615 56.750 109.440 ; + RECT 59.150 107.615 60.050 109.440 ; + RECT 62.450 107.615 95.620 109.440 ; + RECT 98.020 107.615 98.920 109.440 ; + RECT 101.320 107.615 134.490 109.440 ; + RECT 136.890 107.615 137.790 109.440 ; + RECT 140.190 107.615 144.145 109.440 ; END END tt_um_wokwi_413923150973445121 END LIBRARY diff --git a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v index 3661ff64..fde5d5c3 100644 --- a/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v +++ b/projects/tt_um_wokwi_413923150973445121/tt_um_wokwi_413923150973445121.v @@ -19,170 +19,442 @@ module tt_um_wokwi_413923150973445121 (clk, output [7:0] uio_out; output [7:0] uo_out; - wire net8; - wire net9; - wire net6; - wire net7; - wire net10; - wire net11; - wire net12; - wire net13; wire net14; wire net15; wire net16; wire net17; wire net18; wire net19; + wire net2; wire net20; wire net21; wire net22; wire net23; wire net24; wire net25; - wire net1; - wire net2; + wire net26; + wire net27; + wire net28; + wire net29; wire net3; + wire net30; + wire net31; + wire net32; + wire net33; + wire net34; + wire net35; + wire net36; + wire net37; + wire net38; + wire net39; wire net4; + wire net40; + wire net41; + wire net42; wire net5; + wire net6; + wire net7; + wire net8; + wire net9; + wire net10; + wire net11; + wire net12; + wire net13; + wire net43; + wire net44; + wire net45; + wire net46; + wire net47; + wire net48; + wire net49; + wire net50; + wire net51; + wire net52; + wire net53; + wire net54; + wire \flop4/q ; + wire net1; + sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_2 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net9)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_3 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net10)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_4 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net11)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_5 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net12)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_6 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net6)); + .LO(net13)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_7 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net7)); + .LO(net43)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_8 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net10)); + .LO(net44)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_9 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net11)); + .LO(net45)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_10 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net12)); + .LO(net46)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_11 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net13)); + .LO(net47)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_12 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net14)); + .LO(net48)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_13 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net15)); + .LO(net49)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_14 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net16)); + .LO(net50)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_15 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net17)); + .LO(net51)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_16 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net18)); + .LO(net52)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_17 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net19)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_18 (.VGND(VGND), + .LO(net53)); + sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(net18), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net20)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_19 (.VGND(VGND), + .X(net54)); + sky130_fd_sc_hd__buf_2 _17_ (.A(net2), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net21)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_20 (.VGND(VGND), + .X(uo_out[0])); + sky130_fd_sc_hd__buf_2 _18_ (.A(net3), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net22)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_21 (.VGND(VGND), + .X(uo_out[1])); + sky130_fd_sc_hd__buf_2 _19_ (.A(net4), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net23)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_22 (.VGND(VGND), + .X(uo_out[2])); + sky130_fd_sc_hd__buf_2 _20_ (.A(net5), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net24)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_23 (.VGND(VGND), + .X(uo_out[3])); + sky130_fd_sc_hd__buf_2 _21_ (.A(net6), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net25)); - sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), + .X(uo_out[4])); + sky130_fd_sc_hd__buf_2 _22_ (.A(net7), .VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__clkbuf_4 _19_ (.A(net8), + .VPWR(VPWR), + .X(uo_out[5])); + sky130_fd_sc_hd__buf_2 _23_ (.A(net8), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[0])); - sky130_fd_sc_hd__clkbuf_4 _20_ (.A(net9), + .X(uo_out[6])); + sky130_fd_sc_hd__and2_1 \and1/_0_ (.A(net20), + .B(net17), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[1])); - sky130_fd_sc_hd__buf_2 _21_ (.A(ui_in[5]), + .X(net21)); + sky130_fd_sc_hd__and2_1 \and2/_0_ (.A(net24), + .B(net22), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[5])); - sky130_fd_sc_hd__buf_2 _22_ (.A(ui_in[6]), + .X(net25)); + sky130_fd_sc_hd__and2_1 \and3/_0_ (.A(net23), + .B(net24), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[6])); - sky130_fd_sc_hd__buf_2 _23_ (.A(ui_in[7]), + .X(net26)); + sky130_fd_sc_hd__and2_1 \and4/_0_ (.A(net20), + .B(net14), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net27)); + sky130_fd_sc_hd__and2_1 \and5/_0_ (.A(net24), + .B(net14), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net28)); + sky130_fd_sc_hd__and2_1 \and6/_0_ (.A(net14), + .B(net22), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net29)); + sky130_fd_sc_hd__and2_1 \and7/_0_ (.A(net17), + .B(net23), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net30)); + sky130_fd_sc_hd__and2_1 \and8/_0_ (.A(net17), + .B(net24), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net31)); + sky130_fd_sc_hd__and2_1 \and9/_0_ (.A(net30), + .B(net24), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(uo_out[7])); - sky130_fd_sc_hd__and2_1 \and1/_0_ (.A(net2), - .B(net1), + .X(net32)); + sky130_fd_sc_hd__inv_2 \flop1/_0_ (.A(net16), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net14)); + sky130_fd_sc_hd__dfxtp_1 \flop1/_1_ (.CLK(net15), + .D(net14), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(net16)); + sky130_fd_sc_hd__inv_2 \flop2/_0_ (.A(net15), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net17)); + sky130_fd_sc_hd__dfxtp_1 \flop2/_1_ (.CLK(net18), + .D(net17), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(net15)); + sky130_fd_sc_hd__inv_2 \flop3/_0_ (.A(net54), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net19)); + sky130_fd_sc_hd__dfxtp_1 \flop3/_1_ (.CLK(clk), + .D(net19), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(net18)); + sky130_fd_sc_hd__inv_2 \flop4/_0_ (.A(\flop4/q ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net20)); + sky130_fd_sc_hd__dfxtp_1 \flop4/_1_ (.CLK(net16), + .D(net20), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(\flop4/q )); + sky130_fd_sc_hd__inv_2 \not1/_0_ (.A(net17), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net22)); + sky130_fd_sc_hd__inv_2 \not2/_0_ (.A(net14), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net23)); + sky130_fd_sc_hd__inv_2 \not3/_0_ (.A(net20), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net24)); + sky130_fd_sc_hd__or2_1 \or1/_0_ (.A(net34), + .B(net33), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net2)); + sky130_fd_sc_hd__or2_1 \or10/_0_ (.A(net27), + .B(net26), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net35)); + sky130_fd_sc_hd__or2_1 \or11/_0_ (.A(net23), + .B(net17), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net36)); + sky130_fd_sc_hd__or2_1 \or12/_0_ (.A(net29), + .B(net19), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net42)); + sky130_fd_sc_hd__or2_1 \or13/_0_ (.A(net31), + .B(net30), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net39)); + sky130_fd_sc_hd__or2_1 \or14/_0_ (.A(net30), + .B(net19), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net40)); + sky130_fd_sc_hd__or2_1 \or15/_0_ (.A(net28), + .B(net29), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net41)); + sky130_fd_sc_hd__or2_1 \or16/_0_ (.A(net42), + .B(net6), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net37)); + sky130_fd_sc_hd__or2_1 \or17/_0_ (.A(net26), + .B(net19), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net38)); + sky130_fd_sc_hd__or2_1 \or2/_0_ (.A(net22), + .B(net35), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net3)); + sky130_fd_sc_hd__or2_1 \or3/_0_ (.A(net20), + .B(net36), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net4)); + sky130_fd_sc_hd__or2_1 \or4/_0_ (.A(net32), + .B(net37), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net5)); + sky130_fd_sc_hd__or2_1 \or5/_0_ (.A(net39), + .B(net38), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net7)); + sky130_fd_sc_hd__or2_1 \or6/_0_ (.A(net41), + .B(net40), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(net8)); - sky130_fd_sc_hd__and2_1 \and2/_0_ (.A(net4), - .B(net3), + sky130_fd_sc_hd__or2_1 \or7/_0_ (.A(net14), + .B(net19), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net33)); + sky130_fd_sc_hd__or2_1 \or8/_0_ (.A(net25), + .B(net21), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(net9)); + .X(net34)); + sky130_fd_sc_hd__or2_1 \or9/_0_ (.A(net28), + .B(net25), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net6)); sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_0_Right_0 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -945,35 +1217,15 @@ module tt_um_wokwi_413923150973445121 (clk, .VPWR(VPWR)); sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_302 (.VGND(VGND), .VPWR(VPWR)); - sky130_fd_sc_hd__clkbuf_1 input1 (.A(ui_in[0]), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .X(net1)); - sky130_fd_sc_hd__clkbuf_1 input2 (.A(ui_in[1]), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .X(net2)); - sky130_fd_sc_hd__clkbuf_1 input3 (.A(ui_in[2]), - .VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_1 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(net3)); - sky130_fd_sc_hd__clkbuf_1 input4 (.A(ui_in[3]), + .LO(net1)); + sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .X(net4)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_413923150973445121_5 (.VGND(VGND), - .VNB(VGND), .VPB(VPWR), - .VPWR(VPWR), - .LO(net5)); + .VNB(VGND)); sky130_ef_sc_hd__decap_12 FILLER_0_0_15 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -5742,10 +5994,14 @@ module tt_um_wokwi_413923150973445121 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_33_205 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_33_205 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_33_213 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); sky130_fd_sc_hd__decap_6 FILLER_0_33_217 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -5862,47 +6118,39 @@ module tt_um_wokwi_413923150973445121 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_153 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_165 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_34_153 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_177 (.VPWR(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_34_159 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_34_189 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_34_171 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_34_195 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_34_181 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_197 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_209 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_34_192 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_221 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_34_197 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_233 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_34_205 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_34_245 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_34_242 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_34_251 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_34_250 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6002,34 +6250,34 @@ module tt_um_wokwi_413923150973445121 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_149 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_35_149 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_35_161 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_35_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_35_167 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_35_177 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_169 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_35_191 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_181 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_35_196 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_193 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_35_207 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_205 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_35_213 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); + .VPWR(VPWR)); sky130_fd_sc_hd__decap_6 FILLER_0_35_217 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -6146,47 +6394,35 @@ module tt_um_wokwi_413923150973445121 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_153 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_165 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_177 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_36_153 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_36_189 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_36_167 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_36_195 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_36_180 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_197 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_36_202 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_209 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_36_208 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_221 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_36_214 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_233 (.VPWR(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_36_234 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_36_245 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_36_251 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_36_246 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6286,35 +6522,23 @@ module tt_um_wokwi_413923150973445121 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_149 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_161 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_37_149 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_167 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_155 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_169 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_181 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_193 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_37_166 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_205 (.VPWR(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_37_184 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_217 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_37_196 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6446,75 +6670,67 @@ module tt_um_wokwi_413923150973445121 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_144 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_166 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_148 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_8 FILLER_0_38_154 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_181 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_38_162 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_38_191 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_180 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_195 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_184 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_201 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_6 FILLER_0_38_190 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_209 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_197 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_225 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_209 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_237 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_221 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_249 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_225 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_253 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_237 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_265 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_249 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_277 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_8 FILLER_0_38_253 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_267 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_38_275 (.VGND(VGND), - .VNB(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_38_281 (.VPWR(VPWR), + .VGND(VGND), .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_6 FILLER_0_38_301 (.VGND(VGND), - .VNB(VGND), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_38_293 (.VPWR(VPWR), + .VGND(VGND), .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_307 (.VGND(VGND), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_38_305 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6530,23 +6746,21 @@ module tt_um_wokwi_413923150973445121 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - assign uio_oe[0] = net25; - assign uio_oe[1] = net5; - assign uio_oe[2] = net6; - assign uio_oe[3] = net7; - assign uio_oe[4] = net10; - assign uio_oe[5] = net11; - assign uio_oe[6] = net12; - assign uio_oe[7] = net13; - assign uio_out[0] = net14; - assign uio_out[1] = net15; - assign uio_out[2] = net16; - assign uio_out[3] = net17; - assign uio_out[4] = net18; - assign uio_out[5] = net19; - assign uio_out[6] = net20; - assign uio_out[7] = net21; - assign uo_out[2] = net22; - assign uo_out[3] = net23; - assign uo_out[4] = net24; + assign uio_oe[0] = net1; + assign uio_oe[1] = net9; + assign uio_oe[2] = net10; + assign uio_oe[3] = net11; + assign uio_oe[4] = net12; + assign uio_oe[5] = net13; + assign uio_oe[6] = net43; + assign uio_oe[7] = net44; + assign uio_out[0] = net45; + assign uio_out[1] = net46; + assign uio_out[2] = net47; + assign uio_out[3] = net48; + assign uio_out[4] = net49; + assign uio_out[5] = net50; + assign uio_out[6] = net51; + assign uio_out[7] = net52; + assign uo_out[7] = net53; endmodule diff --git a/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json b/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json index 6d4c7c20..77ce5a1d 100644 --- a/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json +++ b/projects/tt_um_wokwi_413923150973445121/wokwi-diagram.json @@ -18,13 +18,13 @@ "left": -115.2, "attrs": { "frequency": "10000" } }, - { "type": "wokwi-gnd", "id": "pwr2", "top": -76.8, "left": 565.8, "attrs": {} }, + { "type": "wokwi-gnd", "id": "pwr2", "top": 19.2, "left": 1151.4, "attrs": {} }, { "type": "wokwi-vcc", "id": "pwr1", "top": -229.64, "left": -115.2, "attrs": {} }, { "type": "wokwi-7segment", "id": "sevseg1", - "top": -183.24, - "left": 552.28, + "top": -235.02, + "left": 1406.68, "attrs": { "common": "cathode" } }, { @@ -60,64 +60,64 @@ { "type": "board-tt-block-output", "id": "ttout", - "top": -208.93, - "left": 360, + "top": -247.33, + "left": 1147.2, "attrs": { "verilogRole": "output" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio0", - "top": 20.22, - "left": 148.8, + "top": 68.22, + "left": -139.2, "attrs": { "verilogRole": "bidirectional", "verilogBit": "0" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio1", - "top": 58.62, - "left": 148.8, + "top": 106.62, + "left": -139.2, "attrs": { "verilogRole": "bidirectional", "verilogBit": "1" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio2", - "top": 97.02, - "left": 148.8, + "top": 145.02, + "left": -139.2, "attrs": { "verilogRole": "bidirectional", "verilogBit": "2" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio3", - "top": 135.42, - "left": 148.8, + "top": 183.42, + "left": -139.2, "attrs": { "verilogRole": "bidirectional", "verilogBit": "3" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio4", - "top": 20.22, - "left": 273.6, + "top": 68.22, + "left": -14.4, "attrs": { "verilogRole": "bidirectional", "verilogBit": "4" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio5", - "top": 58.62, - "left": 273.6, + "top": 106.62, + "left": -14.4, "attrs": { "verilogRole": "bidirectional", "verilogBit": "5" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio6", - "top": 97.02, - "left": 273.6, + "top": 145.02, + "left": -14.4, "attrs": { "verilogRole": "bidirectional", "verilogBit": "6" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio7", - "top": 135.42, - "left": 273.6, + "top": 183.42, + "left": -14.4, "attrs": { "verilogRole": "bidirectional", "verilogBit": "7" } }, { @@ -131,12 +131,78 @@ { "type": "wokwi-text", "id": "text1", - "top": -18.98, - "left": 184.55, + "top": 29.02, + "left": -103.45, "attrs": { "text": "Bidirectional I/O pins" } }, - { "type": "wokwi-gate-and-2", "id": "and1", "top": -278.4, "left": 172.8, "attrs": {} }, - { "type": "wokwi-gate-and-2", "id": "and2", "top": -230.4, "left": 182.4, "attrs": {} } + { "type": "wokwi-junction", "id": "j1", "top": -254.4, "left": 388.8, "attrs": {} }, + { "type": "wokwi-junction", "id": "j2", "top": -187.2, "left": 388.8, "attrs": {} }, + { "type": "wokwi-junction", "id": "j3", "top": -129.6, "left": 388.8, "attrs": {} }, + { "type": "wokwi-junction", "id": "j4", "top": -72, "left": 388.8, "attrs": {} }, + { + "type": "wokwi-flip-flop-d", + "id": "flop1", + "top": -134.2, + "left": 268.6, + "rotate": 270, + "attrs": {} + }, + { + "type": "wokwi-flip-flop-d", + "id": "flop2", + "top": 9.8, + "left": 268.6, + "rotate": 270, + "attrs": {} + }, + { + "type": "wokwi-flip-flop-d", + "id": "flop3", + "top": 163.4, + "left": 259, + "rotate": 270, + "attrs": { "color": "white", "label": "Flop3" } + }, + { + "type": "wokwi-flip-flop-d", + "id": "flop4", + "top": -297.4, + "left": 268.6, + "rotate": 270, + "attrs": {} + }, + { "type": "wokwi-gate-and-2", "id": "and1", "top": -307.2, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-not", "id": "not1", "top": -201.6, "left": 432, "attrs": {} }, + { "type": "wokwi-gate-not", "id": "not2", "top": -144, "left": 432, "attrs": {} }, + { "type": "wokwi-gate-not", "id": "not3", "top": -86.4, "left": 432, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and2", "top": -230.4, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and3", "top": -163.2, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and4", "top": -96, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and5", "top": -28.8, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and6", "top": 38.4, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and7", "top": 105.6, "left": 566.4, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and8", "top": 172.8, "left": 556.8, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and9", "top": 76.8, "left": 681.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or1", "top": -316.8, "left": 1008, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or2", "top": -240, "left": 883.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or3", "top": -163.2, "left": 892.8, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or4", "top": -76.8, "left": 969.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or5", "top": -19.2, "left": 969.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or6", "top": 182.4, "left": 979.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or7", "top": -355.2, "left": 883.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or8", "top": -297.6, "left": 883.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or9", "top": -105.6, "left": 710.4, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or10", "top": -249.6, "left": 691.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or11", "top": -192, "left": 691.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or12", "top": -19.2, "left": 720, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or13", "top": 124.8, "left": 729.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or14", "top": 144, "left": 854.4, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or15", "top": 220.8, "left": 844.8, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or16", "top": -86.4, "left": 854.4, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or17", "top": -28.8, "left": 864, "attrs": {} }, + { "type": "wokwi-junction", "id": "j5", "top": -350.4, "left": 840, "attrs": {} }, + { "type": "wokwi-junction", "id": "j6", "top": 72, "left": 936, "attrs": {} }, + { "type": "wokwi-junction", "id": "j7", "top": 100.8, "left": 974.4, "attrs": {} } ], "connections": [ [ "pwr1:VCC", "sw1:8a", "red", [ "v0" ] ], @@ -160,7 +226,7 @@ [ "ttout:EXTOUT5", "sevseg1:F", "green", [ "h69.01", "v-57.6", "h28.8" ] ], [ "ttout:EXTOUT6", "sevseg1:G", "green", [ "h78.61", "v-57.6" ] ], [ "ttout:EXTOUT7", "sevseg1:DP", "green", [ "v28.8", "h136.21" ] ], - [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v0" ] ], + [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v-76.8", "h268.8" ] ], [ "sw2:1", "clock1:CLK", "blue", [ "h-19.2", "v-57.6" ] ], [ "sw1:1b", "ttin:EXTIN0", "green", [ "h0" ] ], [ "sw1:2b", "ttin:EXTIN1", "green", [ "h0" ] ], @@ -171,21 +237,87 @@ [ "sw1:7b", "ttin:EXTIN6", "green", [ "h0" ] ], [ "sw1:8b", "ttin:EXTIN7", "green", [ "v0" ] ], [ "sw2:2", "ttin:EXTCLK", "blue", [ "v0" ] ], - [ "ttout:OUT5", "ttin:IN5", "green", [ "h0" ] ], - [ "ttin:IN6", "ttout:OUT6", "green", [ "h0" ] ], - [ "ttout:OUT7", "ttin:IN7", "green", [ "h0" ] ], [ "btn1:1.l", "sw2:3", "blue", [ "h0" ] ], [ "pwr3:VCC", "btn1:2.r", "red", [ "v0" ] ], [ "btn2:2.l", "gnd1:GND", "black", [ "h0" ] ], [ "ttin:EXTRST_N", "btn2:1.r", "orange", [ "h-38.4", "v-96" ] ], [ "btn2:1.l", "r2:2", "green", [ "h0" ] ], [ "pwr5:VCC", "r2:1", "red", [ "v0" ] ], - [ "ttin:IN0", "and1:A", "green", [ "h28.8", "v-86.4" ] ], - [ "ttin:IN1", "and1:B", "green", [ "h38.4", "v-76.8" ] ], - [ "ttin:IN2", "and2:A", "green", [ "h48", "v-48" ] ], - [ "ttin:IN3", "and2:B", "green", [ "h57.6", "v-38.4" ] ], - [ "and2:OUT", "ttout:OUT1", "green", [ "v48", "h76.8" ] ], - [ "and1:OUT", "ttout:OUT0", "green", [ "v0" ] ] + [ "flop3:Q", "flop2:CLK", "green", [ "v-38.4", "h28.8" ] ], + [ "flop3:NOTQ", "flop3:D", "green", [ "v-19.2", "h-48", "v115.2" ] ], + [ "flop2:NOTQ", "flop2:D", "green", [ "v-9.6", "h-48", "v105.6" ] ], + [ "flop2:Q", "flop1:CLK", "green", [ "v-28.8", "h19.2" ] ], + [ "flop1:Q", "flop4:CLK", "green", [ "v-28.8", "h19.2" ] ], + [ "flop1:NOTQ", "flop1:D", "green", [ "h-48", "v96" ] ], + [ "flop4:NOTQ", "flop4:D", "green", [ "v-28.8", "h-48", "v124.8" ] ], + [ "flop3:CLK", "ttin:CLK", "green", [ "v28.8", "h-86.4", "v-220.8", "h-38.4", "v-240" ] ], + [ "ttout:OUT0", "or1:OUT", "green", [ "h-38.4", "v-67.2" ] ], + [ "ttout:OUT1", "or2:OUT", "green", [ "h-76.8", "v-9.6" ] ], + [ "ttout:OUT2", "or3:OUT", "green", [ "h-76.8", "v28.8" ] ], + [ "ttout:OUT3", "or4:OUT", "green", [ "h-67.2", "v76.8" ] ], + [ "ttout:OUT5", "or5:OUT", "green", [ "h-48", "v172.8" ] ], + [ "ttout:OUT6", "or6:OUT", "green", [ "h-38.4", "v220.8" ] ], + [ "flop3:NOTQ", "j1:J", "magenta", [ "h48", "v-384" ] ], + [ "flop2:NOTQ", "j2:J", "cyan", [ "h28.8", "v-163.2" ] ], + [ "flop1:NOTQ", "j3:J", "gold", [ "h48", "v38.4" ] ], + [ "flop4:NOTQ", "j4:J", "green", [ "h19.2", "v259.2" ] ], + [ "j2:J", "not1:IN", "cyan", [ "v0" ] ], + [ "j3:J", "not2:IN", "gold", [ "v0" ] ], + [ "j4:J", "not3:IN", "green", [ "v0" ] ], + [ "or1:A", "or7:OUT", "green", [ "h-9.6", "v-38.4" ] ], + [ "or1:B", "or8:OUT", "green", [ "h0" ] ], + [ "ttout:OUT4", "or9:OUT", "green", [ "h-57.6", "v124.8" ] ], + [ "and1:OUT", "or8:A", "green", [ "v0" ] ], + [ "j3:J", "or7:B", "gold", [ "h9.6", "v-201.6" ] ], + [ "or10:OUT", "or2:A", "green", [ "v0" ] ], + [ "or3:A", "or11:OUT", "green", [ "h-28.8", "v-19.2" ] ], + [ "or6:A", "or14:OUT", "green", [ "h0" ] ], + [ "or6:B", "or15:OUT", "green", [ "h0" ] ], + [ "or13:OUT", "or5:B", "green", [ "v-134.4", "h76.8" ] ], + [ "and9:OUT", "or4:B", "green", [ "h57.6", "v-144" ] ], + [ "or4:A", "or16:OUT", "green", [ "h0" ] ], + [ "or16:A", "or9:OUT", "green", [ "h0" ] ], + [ "or16:B", "or12:OUT", "green", [ "h0" ] ], + [ "or5:A", "or17:OUT", "green", [ "h0" ] ], + [ "or17:B", "and3:OUT", "green", [ "h-28.8", "v-144" ] ], + [ "or8:B", "and2:OUT", "green", [ "h0" ] ], + [ "j1:J", "j5:J", "magenta", [ "v0" ] ], + [ "j5:J", "or7:A", "magenta", [ "v0" ] ], + [ "or17:A", "j5:J", "magenta", [ "h0" ] ], + [ "or14:A", "j5:J", "magenta", [ "h0" ] ], + [ "and7:OUT", "and9:B", "green", [ "v0" ] ], + [ "and8:OUT", "or13:B", "green", [ "v0" ] ], + [ "or13:A", "and7:OUT", "green", [ "h0" ] ], + [ "or14:B", "and7:OUT", "green", [ "h0" ] ], + [ "and6:OUT", "or12:B", "green", [ "v0" ] ], + [ "and6:OUT", "or15:A", "green", [ "v0", "h153.6", "v172.8" ] ], + [ "and5:OUT", "or15:B", "green", [ "v0", "h38.4", "v259.2" ] ], + [ "and9:A", "not3:OUT", "green", [ "h-153.6" ] ], + [ "or2:B", "not1:OUT", "green", [ "h-48", "v9.6", "h-153.6", "v19.2", "h-9.6" ] ], + [ "or3:B", "j4:J", "green", [ "h-211.2", "v19.2", "h-163.2", "v19.2", "h-124.8" ] ], + [ "or12:A", "j5:J", "magenta", [ "h0", "v-28.8", "h76.8", "v-307.2" ] ], + [ "and5:OUT", "or9:B", "green", [ "v-28.8", "h28.8" ] ], + [ "or9:A", "and2:OUT", "green", [ "h0" ] ], + [ "or11:B", "not2:OUT", "green", [ "h0", "v38.4" ] ], + [ "or11:A", "j2:J", "cyan", [ "h-19.2", "v9.6", "h-278.4" ] ], + [ "or10:B", "and4:OUT", "green", [ "h0" ] ], + [ "or10:A", "and3:OUT", "green", [ "h0" ] ], + [ "j2:J", "and1:A", "cyan", [ "v0" ] ], + [ "j4:J", "and1:B", "green", [ "v0" ] ], + [ "and2:A", "not1:OUT", "green", [ "h0" ] ], + [ "and2:B", "not3:OUT", "green", [ "h0" ] ], + [ "and3:A", "not3:OUT", "green", [ "h0" ] ], + [ "and3:B", "not2:OUT", "green", [ "h0" ] ], + [ "j3:J", "and4:A", "gold", [ "v0" ] ], + [ "j4:J", "and4:B", "green", [ "v0" ] ], + [ "j3:J", "and5:A", "gold", [ "v0" ] ], + [ "and5:B", "not3:OUT", "green", [ "h0" ] ], + [ "and6:A", "not1:OUT", "green", [ "h0" ] ], + [ "j3:J", "and6:B", "gold", [ "v0" ] ], + [ "and7:A", "not2:OUT", "green", [ "h0" ] ], + [ "j2:J", "and7:B", "cyan", [ "v0" ] ], + [ "and8:A", "not3:OUT", "green", [ "h0" ] ], + [ "j2:J", "and8:B", "cyan", [ "v0" ] ] ], "dependencies": {} } \ No newline at end of file