diff --git a/projects/tt_um_senolgulgonul/commit_id.json b/projects/tt_um_senolgulgonul/commit_id.json index 4d4eb41f..f8b578e2 100644 --- a/projects/tt_um_senolgulgonul/commit_id.json +++ b/projects/tt_um_senolgulgonul/commit_id.json @@ -1,8 +1,8 @@ { "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/senolgulgonul/tt09-senolgulgonul", - "commit": "2bafa19bd627f72071b189c1c3173297d98a2501", - "workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11710162896", + "commit": "d92f06d6ae123e8817d1124692f40e26944da9f1", + "workflow_url": "https://github.com/senolgulgonul/tt09-senolgulgonul/actions/runs/11723961689", "sort_id": 1730725111692, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_senolgulgonul/info.yaml b/projects/tt_um_senolgulgonul/info.yaml index 4f993d63..2d9abf84 100644 --- a/projects/tt_um_senolgulgonul/info.yaml +++ b/projects/tt_um_senolgulgonul/info.yaml @@ -3,7 +3,7 @@ project: title: "Senol Gulgonul tt09" # Project title author: "Senol Gulgonul" # Your name discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) - description: "Display my name letters on 7-Seg at each button click" # One line description of what your project does + description: "Display the letters of SEnOLGULGONUL on 7-Seg using internal oscillator" # One line description of what your project does language: "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc clock_hz: 0 # Clock frequency in Hz (or 0 if not applicable) @@ -22,8 +22,8 @@ project: # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. pinout: # Inputs - ui[0]: "" - ui[1]: "" + ui[0]: "inv3_in" + ui[1]: "inv1_in" ui[2]: "" ui[3]: "" ui[4]: "" @@ -42,8 +42,8 @@ pinout: uo[7]: "dp" # Bidirectional pins - uio[0]: "" - uio[1]: "" + uio[0]: "inv3_out" + uio[1]: "inv2_out" uio[2]: "" uio[3]: "" uio[4]: "" diff --git a/projects/tt_um_senolgulgonul/stats/metrics.csv b/projects/tt_um_senolgulgonul/stats/metrics.csv index ccf35563..f66e11a0 100644 --- a/projects/tt_um_senolgulgonul/stats/metrics.csv +++ b/projects/tt_um_senolgulgonul/stats/metrics.csv @@ -1,23 +1,23 @@ Metric,Value design__lint_error__count,0 design__lint_timing_construct__count,0 -design__lint_warning__count,0 +design__lint_warning__count,1 design__inferred_latch__count,0 -design__instance__count,289 -design__instance__area,942.154 +design__instance__count,291 +design__instance__area,965.926 design__instance_unmapped__count,0 synthesis__check_error__count,0 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 -power__internal__total,0.00005628330836771056 -power__switching__total,0.000011626812010945287 -power__leakage__total,1.9286874319845992E-9 -power__total,0.00006791204941691831 -clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0012925494374000175 -clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0012925494374000175 -timing__hold__ws__corner:nom_tt_025C_1v80,0.33075532138237423 -timing__setup__ws__corner:nom_tt_025C_1v80,14.704005540457139 +power__internal__total,0.00005841313031851314 +power__switching__total,0.000012353103556961287 +power__leakage__total,1.9285466557050768E-9 +power__total,0.00007076816109474748 +clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.00261807249956396 +clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.00261807249956396 +timing__hold__ws__corner:nom_tt_025C_1v80,0.3752770422858427 +timing__setup__ws__corner:nom_tt_025C_1v80,11.47826755021178 timing__hold__tns__corner:nom_tt_025C_1v80,0.0 timing__setup__tns__corner:nom_tt_025C_1v80,0.0 timing__hold__wns__corner:nom_tt_025C_1v80,0 @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0 design__max_slew_violation__count__corner:nom_ss_100C_1v60,0 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 -clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0014997448152305728 -clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0014997448152305728 -timing__hold__ws__corner:nom_ss_100C_1v60,0.9373745378557752 -timing__setup__ws__corner:nom_ss_100C_1v60,13.705788003573586 +clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.003981259878903531 +clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.003981259878903531 +timing__hold__ws__corner:nom_ss_100C_1v60,0.9998261390694265 +timing__setup__ws__corner:nom_ss_100C_1v60,11.280718900515021 timing__hold__tns__corner:nom_ss_100C_1v60,0.0 timing__setup__tns__corner:nom_ss_100C_1v60,0.0 timing__hold__wns__corner:nom_ss_100C_1v60,0 @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 -clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0012136403336930827 -clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0012136403336930827 -timing__hold__ws__corner:nom_ff_n40C_1v95,0.11182885489706622 -timing__setup__ws__corner:nom_ff_n40C_1v95,15.066204710254542 +clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.00186713150225725 +clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.00186713150225725 +timing__hold__ws__corner:nom_ff_n40C_1v95,0.14265178331243708 +timing__setup__ws__corner:nom_ff_n40C_1v95,11.558058837159033 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 timing__hold__wns__corner:nom_ff_n40C_1v95,0 @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count,0 design__max_fanout_violation__count,0 design__max_cap_violation__count,0 -clock__skew__worst_hold,0.002018052448935568 -clock__skew__worst_setup,0.0010730583392239918 -timing__hold__ws,0.10889101040179083 -timing__setup__ws,13.69707941392213 +clock__skew__worst_hold,0.004094724675229225 +clock__skew__worst_setup,0.0016133483894382704 +timing__hold__ws,0.13986789899945587 +timing__setup__ws,11.275407593415 timing__hold__tns,0.0 timing__setup__tns,0.0 timing__hold__wns,0 @@ -86,12 +86,12 @@ flow__errors__count,0 design__io,45 design__die__area,17954.7 design__core__area,16493.3 -design__instance__count__stdcell,289 -design__instance__area__stdcell,942.154 +design__instance__count__stdcell,291 +design__instance__area__stdcell,965.926 design__instance__count__macros,0 design__instance__area__macros,0 -design__instance__utilization,0.0571234 -design__instance__utilization__stdcell,0.0571234 +design__instance__utilization,0.0585647 +design__instance__utilization__stdcell,0.0585647 design__power_grid_violation__count__net:VPWR,0 design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count,0 @@ -100,44 +100,44 @@ timing__drv__floating__pins,0 design__instance__displacement__total,0 design__instance__displacement__mean,0 design__instance__displacement__max,0 -route__wirelength__estimated,973.064 +route__wirelength__estimated,1116.14 design__violations,0 design__instance__count__setup_buffer,0 design__instance__count__hold_buffer,1 antenna__violating__nets,0 antenna__violating__pins,0 route__antenna_violation__count,0 -route__net,82 +route__net,84 route__net__special,2 -route__drc_errors__iter:1,29 -route__wirelength__iter:1,1073 -route__drc_errors__iter:2,6 -route__wirelength__iter:2,1047 -route__drc_errors__iter:3,13 -route__wirelength__iter:3,1028 +route__drc_errors__iter:1,55 +route__wirelength__iter:1,1304 +route__drc_errors__iter:2,4 +route__wirelength__iter:2,1233 +route__drc_errors__iter:3,2 +route__wirelength__iter:3,1233 route__drc_errors__iter:4,0 -route__wirelength__iter:4,1030 +route__wirelength__iter:4,1229 route__drc_errors,0 -route__wirelength,1030 -route__vias,393 -route__vias__singlecut,393 +route__wirelength,1229 +route__vias,424 +route__vias__singlecut,424 route__vias__multicut,0 -design__disconnected_pin__count,17 +design__disconnected_pin__count,15 design__critical_disconnected_pin__count,0 -route__wirelength__max,83.27 -timing__unannotated_net__count__corner:nom_tt_025C_1v80,34 +route__wirelength__max,90.99 +timing__unannotated_net__count__corner:nom_tt_025C_1v80,30 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 -timing__unannotated_net__count__corner:nom_ss_100C_1v60,34 +timing__unannotated_net__count__corner:nom_ss_100C_1v60,30 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 -timing__unannotated_net__count__corner:nom_ff_n40C_1v95,34 +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,30 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count__corner:min_tt_025C_1v80,0 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0 design__max_cap_violation__count__corner:min_tt_025C_1v80,0 -clock__skew__worst_hold__corner:min_tt_025C_1v80,0.001138422721647429 -clock__skew__worst_setup__corner:min_tt_025C_1v80,0.001138422721647429 -timing__hold__ws__corner:min_tt_025C_1v80,0.32609837975157424 -timing__setup__ws__corner:min_tt_025C_1v80,14.70882657305562 +clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0022805924461089403 +clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0022805924461089403 +timing__hold__ws__corner:min_tt_025C_1v80,0.3682081965769825 +timing__setup__ws__corner:min_tt_025C_1v80,11.48447414118418 timing__hold__tns__corner:min_tt_025C_1v80,0.0 timing__setup__tns__corner:min_tt_025C_1v80,0.0 timing__hold__wns__corner:min_tt_025C_1v80,0 @@ -148,15 +148,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 timing__setup_vio__count__corner:min_tt_025C_1v80,0 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 -timing__unannotated_net__count__corner:min_tt_025C_1v80,34 +timing__unannotated_net__count__corner:min_tt_025C_1v80,30 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 design__max_slew_violation__count__corner:min_ss_100C_1v60,0 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0 design__max_cap_violation__count__corner:min_ss_100C_1v60,0 -clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0013118395629984417 -clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0013118395629984417 -timing__hold__ws__corner:min_ss_100C_1v60,0.9300691036136761 -timing__setup__ws__corner:min_ss_100C_1v60,13.713386370169017 +clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0034955372918928514 +clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0034955372918928514 +timing__hold__ws__corner:min_ss_100C_1v60,0.992381538367255 +timing__setup__ws__corner:min_ss_100C_1v60,11.290653176420328 timing__hold__tns__corner:min_ss_100C_1v60,0.0 timing__setup__tns__corner:min_ss_100C_1v60,0.0 timing__hold__wns__corner:min_ss_100C_1v60,0 @@ -167,15 +167,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 timing__setup_vio__count__corner:min_ss_100C_1v60,0 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 -timing__unannotated_net__count__corner:min_ss_100C_1v60,34 +timing__unannotated_net__count__corner:min_ss_100C_1v60,30 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 -clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0010730583392239918 -clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0010730583392239918 -timing__hold__ws__corner:min_ff_n40C_1v95,0.10889101040179083 -timing__setup__ws__corner:min_ff_n40C_1v95,15.069725449609807 +clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0016133483894382704 +clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0016133483894382704 +timing__hold__ws__corner:min_ff_n40C_1v95,0.13986789899945587 +timing__setup__ws__corner:min_ff_n40C_1v95,11.562719109459001 timing__hold__tns__corner:min_ff_n40C_1v95,0.0 timing__setup__tns__corner:min_ff_n40C_1v95,0.0 timing__hold__wns__corner:min_ff_n40C_1v95,0 @@ -186,15 +186,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:min_ff_n40C_1v95,34 +timing__unannotated_net__count__corner:min_ff_n40C_1v95,30 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 design__max_slew_violation__count__corner:max_tt_025C_1v80,0 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0 design__max_cap_violation__count__corner:max_tt_025C_1v80,0 -clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0017431057091111231 -clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0017431057091111231 -timing__hold__ws__corner:max_tt_025C_1v80,0.33556303130418236 -timing__setup__ws__corner:max_tt_025C_1v80,14.698308763912067 +clock__skew__worst_hold__corner:max_tt_025C_1v80,0.002701894340293803 +clock__skew__worst_setup__corner:max_tt_025C_1v80,0.002701894340293803 +timing__hold__ws__corner:max_tt_025C_1v80,0.38285281584208364 +timing__setup__ws__corner:max_tt_025C_1v80,11.474650887584476 timing__hold__tns__corner:max_tt_025C_1v80,0.0 timing__setup__tns__corner:max_tt_025C_1v80,0.0 timing__hold__wns__corner:max_tt_025C_1v80,0 @@ -205,15 +205,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 timing__setup_vio__count__corner:max_tt_025C_1v80,0 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 -timing__unannotated_net__count__corner:max_tt_025C_1v80,34 +timing__unannotated_net__count__corner:max_tt_025C_1v80,30 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 design__max_slew_violation__count__corner:max_ss_100C_1v60,0 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0 design__max_cap_violation__count__corner:max_ss_100C_1v60,0 -clock__skew__worst_hold__corner:max_ss_100C_1v60,0.002018052448935568 -clock__skew__worst_setup__corner:max_ss_100C_1v60,0.002018052448935568 -timing__hold__ws__corner:max_ss_100C_1v60,0.945075711106194 -timing__setup__ws__corner:max_ss_100C_1v60,13.69707941392213 +clock__skew__worst_hold__corner:max_ss_100C_1v60,0.004094724675229225 +clock__skew__worst_setup__corner:max_ss_100C_1v60,0.004094724675229225 +timing__hold__ws__corner:max_ss_100C_1v60,1.0115796264743346 +timing__setup__ws__corner:max_ss_100C_1v60,11.275407593415 timing__hold__tns__corner:max_ss_100C_1v60,0.0 timing__setup__tns__corner:max_ss_100C_1v60,0.0 timing__hold__wns__corner:max_ss_100C_1v60,0 @@ -224,15 +224,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 timing__setup_vio__count__corner:max_ss_100C_1v60,0 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 -timing__unannotated_net__count__corner:max_ss_100C_1v60,34 +timing__unannotated_net__count__corner:max_ss_100C_1v60,30 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 -clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0016473350927408176 -clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0016473350927408176 -timing__hold__ws__corner:max_ff_n40C_1v95,0.11517728763403584 -timing__setup__ws__corner:max_ff_n40C_1v95,15.061735396320211 +clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0019437507709111346 +clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0019437507709111346 +timing__hold__ws__corner:max_ff_n40C_1v95,0.1458264661411389 +timing__setup__ws__corner:max_ff_n40C_1v95,11.555295714017198 timing__hold__tns__corner:max_ff_n40C_1v95,0.0 timing__setup__tns__corner:max_ff_n40C_1v95,0.0 timing__hold__wns__corner:max_ff_n40C_1v95,0 @@ -243,19 +243,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:max_ff_n40C_1v95,34 +timing__unannotated_net__count__corner:max_ff_n40C_1v95,30 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count,34 +timing__unannotated_net__count,30 timing__unannotated_net_filtered__count,0 -design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79995 +design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8 -design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000467214 -design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000460914 -design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000119085 -design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000460914 +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000447712 +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000350783 +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.00000120046 +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000350783 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 -ir__drop__avg,0.00000119000000000000004144145963891343598106686840765178203582763671875 -ir__drop__worst,0.00004669999999999999672206651979422531439922749996185302734375 +ir__drop__avg,0.000001219999999999999965968520108938744073157067759893834590911865234375 +ir__drop__worst,0.0000447999999999999979727154097997043891155044548213481903076171875 magic__drc_error__count,0 magic__illegal_overlap__count,0 design__lvs_device_difference__count,0 diff --git a/projects/tt_um_senolgulgonul/stats/synthesis-stats.txt b/projects/tt_um_senolgulgonul/stats/synthesis-stats.txt index 99cbf93f..103cdd24 100644 --- a/projects/tt_um_senolgulgonul/stats/synthesis-stats.txt +++ b/projects/tt_um_senolgulgonul/stats/synthesis-stats.txt @@ -2,34 +2,35 @@ === tt_um_senolgulgonul === - Number of wires: 41 - Number of wire bits: 76 + Number of wires: 40 + Number of wire bits: 75 Number of public wires: 12 Number of public wire bits: 47 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 57 - sky130_fd_sc_hd__a21o_2 1 - sky130_fd_sc_hd__a21oi_2 2 - sky130_fd_sc_hd__a31o_2 1 - sky130_fd_sc_hd__and2_2 1 - sky130_fd_sc_hd__and2b_2 1 - sky130_fd_sc_hd__and3_2 2 - sky130_fd_sc_hd__and4b_2 1 - sky130_fd_sc_hd__buf_2 1 - sky130_fd_sc_hd__conb_1 16 + Number of cells: 56 + sky130_fd_sc_hd__a21oi_2 3 + sky130_fd_sc_hd__a22o_2 1 + sky130_fd_sc_hd__a31o_2 2 + sky130_fd_sc_hd__a32o_2 1 + sky130_fd_sc_hd__and3_2 1 + sky130_fd_sc_hd__and3b_2 1 + sky130_fd_sc_hd__buf_2 2 + sky130_fd_sc_hd__conb_1 14 sky130_fd_sc_hd__dfrtp_2 11 sky130_fd_sc_hd__inv_2 4 - sky130_fd_sc_hd__mux2_1 2 - sky130_fd_sc_hd__nor2_2 7 - sky130_fd_sc_hd__nor3_2 1 + sky130_fd_sc_hd__mux2_1 3 + sky130_fd_sc_hd__nand2_2 2 + sky130_fd_sc_hd__nand2b_2 2 + sky130_fd_sc_hd__nand4_2 1 + sky130_fd_sc_hd__nor2_2 1 + sky130_fd_sc_hd__nor3_2 2 sky130_fd_sc_hd__o21a_2 1 - sky130_fd_sc_hd__o21ba_2 1 - sky130_fd_sc_hd__o22a_2 1 - sky130_fd_sc_hd__o31ai_2 1 + sky130_fd_sc_hd__o21ai_2 1 + sky130_fd_sc_hd__o311a_2 1 + sky130_fd_sc_hd__o31a_2 1 sky130_fd_sc_hd__or2_2 1 - sky130_fd_sc_hd__xnor2_2 1 - Chip area for module '\tt_um_senolgulgonul': 586.812800 + Chip area for module '\tt_um_senolgulgonul': 596.822400 diff --git a/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds b/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds index 30e5aee8..f5746c03 100644 Binary files a/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds and b/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.gds differ diff --git a/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.lef b/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.lef index bd98247e..f82e085e 100644 --- a/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.lef +++ b/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.lef @@ -76,6 +76,7 @@ MACRO tt_um_senolgulgonul PIN ui_in[0] DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 138.310 110.520 138.610 111.520 ; @@ -84,6 +85,7 @@ MACRO tt_um_senolgulgonul PIN ui_in[1] DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.213000 ; PORT LAYER met4 ; RECT 135.550 110.520 135.850 111.520 ; @@ -268,6 +270,7 @@ MACRO tt_um_senolgulgonul PIN uio_out[0] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 72.070 110.520 72.370 111.520 ; @@ -276,6 +279,7 @@ MACRO tt_um_senolgulgonul PIN uio_out[1] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.795200 ; PORT LAYER met4 ; RECT 69.310 110.520 69.610 111.520 ; @@ -456,13 +460,13 @@ MACRO tt_um_senolgulgonul RECT 139.010 110.120 140.670 110.520 ; RECT 141.770 110.120 143.430 110.520 ; RECT 30.655 109.440 144.145 110.120 ; - RECT 30.655 96.055 56.750 109.440 ; - RECT 59.150 96.055 60.050 109.440 ; - RECT 62.450 96.055 95.620 109.440 ; - RECT 98.020 96.055 98.920 109.440 ; - RECT 101.320 96.055 134.490 109.440 ; - RECT 136.890 96.055 137.790 109.440 ; - RECT 140.190 96.055 144.145 109.440 ; + RECT 30.655 93.335 56.750 109.440 ; + RECT 59.150 93.335 60.050 109.440 ; + RECT 62.450 93.335 95.620 109.440 ; + RECT 98.020 93.335 98.920 109.440 ; + RECT 101.320 93.335 134.490 109.440 ; + RECT 136.890 93.335 137.790 109.440 ; + RECT 140.190 93.335 144.145 109.440 ; END END tt_um_senolgulgonul END LIBRARY diff --git a/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.v b/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.v index d23e79f1..1d9f45ca 100644 --- a/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.v +++ b/projects/tt_um_senolgulgonul/tt_um_senolgulgonul.v @@ -47,344 +47,349 @@ module tt_um_senolgulgonul (clk, wire _25_; wire _26_; wire _27_; - wire _28_; wire \index[0] ; wire \index[1] ; wire \index[2] ; wire \index[3] ; - wire net12; wire net13; wire net14; wire net15; wire net16; wire net17; wire net18; + wire net19; wire clknet_0_clk; - wire net4; - wire net5; - wire net6; wire net7; wire net8; wire net9; wire net10; wire net11; + wire net12; wire net1; wire net2; wire net3; + wire net4; + wire net5; + wire net6; wire clknet_1_0__leaf_clk; wire clknet_1_1__leaf_clk; - wire net19; + wire net20; - sky130_fd_sc_hd__inv_2 _29_ (.A(\index[2] ), + sky130_fd_sc_hd__inv_2 _28_ (.A(\index[2] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(_11_)); - sky130_fd_sc_hd__inv_2 _30_ (.A(\index[3] ), + sky130_fd_sc_hd__inv_2 _29_ (.A(net3), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(_12_)); - sky130_fd_sc_hd__inv_2 _31_ (.A(\index[1] ), + sky130_fd_sc_hd__inv_2 _30_ (.A(net4), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(_13_)); - sky130_fd_sc_hd__and4b_1 _32_ (.A_N(\index[0] ), - .B(\index[1] ), - .C(\index[2] ), - .D(\index[3] ), + sky130_fd_sc_hd__inv_2 _31_ (.A(net2), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_14_)); - sky130_fd_sc_hd__nor2_1 _33_ (.A(net19), - .B(_14_), + .Y(uio_out[0])); + sky130_fd_sc_hd__nor2_1 _32_ (.A(net4), + .B(\index[3] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_07_)); - sky130_fd_sc_hd__nor2_1 _34_ (.A(\index[0] ), - .B(\index[1] ), + .Y(_14_)); + sky130_fd_sc_hd__a22o_1 _33_ (.A1(_11_), + .A2(net4), + .B1(_14_), + .B2(net3), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_15_)); - sky130_fd_sc_hd__and2_1 _35_ (.A(\index[0] ), + .X(_00_)); + sky130_fd_sc_hd__nand2b_1 _34_ (.A_N(net4), .B(\index[1] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_16_)); - sky130_fd_sc_hd__nor2_1 _36_ (.A(_15_), - .B(_16_), + .Y(_15_)); + sky130_fd_sc_hd__mux2_1 _35_ (.A0(\index[3] ), + .A1(_15_), + .S(_11_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_17_)); - sky130_fd_sc_hd__and2b_1 _37_ (.A_N(_14_), - .B(_17_), + .X(_16_)); + sky130_fd_sc_hd__and3_1 _36_ (.A(\index[2] ), + .B(net3), + .C(net4), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_08_)); - sky130_fd_sc_hd__and3_1 _38_ (.A(\index[2] ), - .B(\index[0] ), - .C(\index[1] ), + .X(_17_)); + sky130_fd_sc_hd__a21oi_1 _37_ (.A1(net3), + .A2(net4), + .B1(\index[2] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_18_)); - sky130_fd_sc_hd__inv_2 _39_ (.A(_18_), + .Y(_18_)); + sky130_fd_sc_hd__a31o_1 _38_ (.A1(\index[2] ), + .A2(net3), + .A3(net4), + .B1(\index[3] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_19_)); - sky130_fd_sc_hd__nor2_1 _40_ (.A(\index[2] ), - .B(_16_), + .X(_19_)); + sky130_fd_sc_hd__nand4_1 _39_ (.A(\index[2] ), + .B(net3), + .C(net4), + .D(\index[3] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(_20_)); - sky130_fd_sc_hd__nor3_1 _41_ (.A(_14_), - .B(_18_), - .C(_20_), + sky130_fd_sc_hd__o21ai_1 _40_ (.A1(net3), + .A2(_14_), + .B1(_16_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_09_)); - sky130_fd_sc_hd__xnor2_1 _42_ (.A(\index[3] ), - .B(_18_), + .Y(_01_)); + sky130_fd_sc_hd__nand2_2 _41_ (.A(net3), + .B(\index[3] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(_21_)); - sky130_fd_sc_hd__nor2_1 _43_ (.A(_14_), - .B(_21_), + sky130_fd_sc_hd__or2_1 _42_ (.A(net3), + .B(\index[3] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_10_)); - sky130_fd_sc_hd__a21oi_1 _44_ (.A1(_12_), - .A2(\index[1] ), - .B1(\index[0] ), + .X(_22_)); + sky130_fd_sc_hd__mux2_1 _43_ (.A0(_21_), + .A1(_22_), + .S(_11_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_22_)); - sky130_fd_sc_hd__a21oi_1 _45_ (.A1(\index[2] ), - .A2(net19), - .B1(_22_), + .X(_02_)); + sky130_fd_sc_hd__a21oi_1 _44_ (.A1(_13_), + .A2(_21_), + .B1(\index[2] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_00_)); - sky130_fd_sc_hd__nor2_1 _46_ (.A(\index[3] ), - .B(\index[0] ), + .Y(_23_)); + sky130_fd_sc_hd__nand2b_1 _45_ (.A_N(\index[1] ), + .B(net4), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_23_)); - sky130_fd_sc_hd__o22a_1 _47_ (.A1(_11_), - .A2(\index[3] ), - .B1(\index[1] ), - .B2(_23_), + .Y(_24_)); + sky130_fd_sc_hd__a31o_1 _46_ (.A1(\index[2] ), + .A2(_21_), + .A3(_24_), + .B1(_23_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_24_)); - sky130_fd_sc_hd__o31ai_1 _48_ (.A1(\index[2] ), - .A2(net19), - .A3(_13_), - .B1(_24_), + .X(_03_)); + sky130_fd_sc_hd__a32o_1 _47_ (.A1(net3), + .A2(_19_), + .A3(_20_), + .B1(_13_), + .B2(\index[2] ), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_01_)); - sky130_fd_sc_hd__or2_1 _49_ (.A(\index[2] ), - .B(\index[1] ), + .X(_25_)); + sky130_fd_sc_hd__o31a_1 _48_ (.A1(_12_), + .A2(_17_), + .A3(_18_), + .B1(_25_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_25_)); - sky130_fd_sc_hd__a31o_1 _50_ (.A1(_12_), - .A2(_19_), - .A3(_25_), - .B1(_10_), + .X(_04_)); + sky130_fd_sc_hd__nand2_1 _49_ (.A(_15_), + .B(_24_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_02_)); - sky130_fd_sc_hd__nor2_1 _51_ (.A(_15_), - .B(_23_), + .Y(_26_)); + sky130_fd_sc_hd__mux2_1 _50_ (.A0(_14_), + .A1(_26_), + .S(_11_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(_26_)); - sky130_fd_sc_hd__a21o_1 _52_ (.A1(_12_), - .A2(\index[1] ), - .B1(_11_), + .X(_05_)); + sky130_fd_sc_hd__and3b_1 _51_ (.A_N(_22_), + .B(_13_), + .C(_11_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_27_)); - sky130_fd_sc_hd__mux2_1 _53_ (.A0(\index[2] ), - .A1(_27_), - .S(_26_), + .X(_06_)); + sky130_fd_sc_hd__o21a_1 _52_ (.A1(_11_), + .A2(_21_), + .B1(_13_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_03_)); - sky130_fd_sc_hd__o21ba_1 _54_ (.A1(_18_), - .A2(_20_), - .B1_N(_21_), + .X(_07_)); + sky130_fd_sc_hd__nor3_1 _53_ (.A(_11_), + .B(net20), + .C(_21_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_28_)); - sky130_fd_sc_hd__o21a_1 _55_ (.A1(_15_), - .A2(_28_), - .B1(_25_), + .Y(_27_)); + sky130_fd_sc_hd__a21oi_1 _54_ (.A1(_15_), + .A2(_24_), + .B1(_27_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_04_)); - sky130_fd_sc_hd__mux2_1 _56_ (.A0(_17_), - .A1(_23_), - .S(\index[2] ), + .Y(_08_)); + sky130_fd_sc_hd__nor3_1 _55_ (.A(_17_), + .B(_18_), + .C(_27_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_05_)); - sky130_fd_sc_hd__and3_1 _57_ (.A(_11_), - .B(_13_), - .C(_23_), + .Y(_09_)); + sky130_fd_sc_hd__o311a_1 _56_ (.A1(_11_), + .A2(net4), + .A3(_21_), + .B1(_20_), + .C1(_19_), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(_06_)); - sky130_fd_sc_hd__dfrtp_4 _58_ (.CLK(clknet_1_1__leaf_clk), + .X(_10_)); + sky130_fd_sc_hd__dfrtp_4 _57_ (.CLK(clknet_1_1__leaf_clk), .D(_00_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[0])); - sky130_fd_sc_hd__dfrtp_4 _59_ (.CLK(clknet_1_1__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _58_ (.CLK(clknet_1_0__leaf_clk), .D(_02_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[2])); - sky130_fd_sc_hd__dfrtp_4 _60_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _59_ (.CLK(clknet_1_1__leaf_clk), .D(_01_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[3])); - sky130_fd_sc_hd__dfrtp_4 _61_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _60_ (.CLK(clknet_1_1__leaf_clk), .D(_03_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[4])); - sky130_fd_sc_hd__dfrtp_4 _62_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _61_ (.CLK(clknet_1_0__leaf_clk), .D(_04_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[5])); - sky130_fd_sc_hd__dfrtp_4 _63_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _62_ (.CLK(clknet_1_0__leaf_clk), .D(_05_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[6])); - sky130_fd_sc_hd__dfrtp_4 _64_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _63_ (.CLK(clknet_1_0__leaf_clk), .D(_06_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(uo_out[7])); - sky130_fd_sc_hd__dfrtp_4 _65_ (.CLK(clknet_1_1__leaf_clk), + sky130_fd_sc_hd__dfrtp_1 _64_ (.CLK(clknet_1_0__leaf_clk), .D(_07_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(\index[0] )); - sky130_fd_sc_hd__dfrtp_4 _66_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_1 _65_ (.CLK(clknet_1_1__leaf_clk), .D(_08_), - .RESET_B(net2), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(\index[1] )); - sky130_fd_sc_hd__dfrtp_4 _67_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfrtp_4 _66_ (.CLK(clknet_1_1__leaf_clk), .D(_09_), - .RESET_B(net2), + .RESET_B(net1), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(\index[2] )); - sky130_fd_sc_hd__dfrtp_2 _68_ (.CLK(clknet_1_1__leaf_clk), + sky130_fd_sc_hd__dfrtp_2 _67_ (.CLK(clknet_1_0__leaf_clk), .D(_10_), - .RESET_B(net1), + .RESET_B(net5), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Q(\index[3] )); - sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_12 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .HI(net12)); sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_13 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -415,27 +420,17 @@ module tt_um_senolgulgonul (clk, .VPB(VPWR), .VPWR(VPWR), .HI(net18)); - sky130_fd_sc_hd__clkbuf_16 clkbuf_0_clk (.A(clk), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .X(clknet_0_clk)); - sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_4 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .LO(net4)); - sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_5 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_19 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net5)); - sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_6 (.VGND(VGND), + .HI(net19)); + sky130_fd_sc_hd__clkbuf_16 clkbuf_0_clk (.A(clk), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net6)); + .X(clknet_0_clk)); sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_7 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -460,8 +455,19 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .HI(net11)); - sky130_fd_sc_hd__buf_2 _85_ (.A(uo_out[3]), + .LO(net11)); + sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_12 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .HI(net12)); + sky130_fd_sc_hd__clkbuf_4 _82_ (.A(ui_in[1]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uio_out[1])); + sky130_fd_sc_hd__buf_2 _83_ (.A(uo_out[3]), .VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -1235,17 +1241,35 @@ module tt_um_senolgulgonul (clk, .VPB(VPWR), .VPWR(VPWR), .X(net1)); - sky130_fd_sc_hd__clkbuf_4 fanout2 (.A(net1), + sky130_fd_sc_hd__clkbuf_1 input2 (.A(ui_in[0]), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(net2)); - sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_3 (.VGND(VGND), + sky130_fd_sc_hd__buf_2 fanout3 (.A(\index[1] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net3)); + sky130_fd_sc_hd__buf_2 fanout4 (.A(\index[0] ), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net4)); + sky130_fd_sc_hd__clkbuf_4 fanout5 (.A(net1), + .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net3)); + .X(net5)); + sky130_fd_sc_hd__conb_1 tt_um_senolgulgonul_6 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .LO(net6)); sky130_fd_sc_hd__clkbuf_16 clkbuf_1_0__f_clk (.A(clknet_0_clk), .VGND(VGND), .VNB(VGND), @@ -1258,7 +1282,7 @@ module tt_um_senolgulgonul (clk, .VPB(VPWR), .VPWR(VPWR), .X(clknet_1_1__leaf_clk)); - sky130_fd_sc_hd__clkinv_2 clkload0 (.A(clknet_1_1__leaf_clk), + sky130_fd_sc_hd__clkbuf_4 clkload0 (.A(clknet_1_1__leaf_clk), .VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -1268,7 +1292,7 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .X(net19)); + .X(net20)); sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -5465,15 +5489,19 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__fill_1 FILLER_0_29_181 (.VGND(VGND), - .VNB(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_29_181 (.VPWR(VPWR), + .VGND(VGND), .VPB(VPWR), - .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_29_203 (.VPWR(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_29_193 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_29_205 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_29_215 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_29_217 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -5585,15 +5613,27 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_30_164 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_30_141 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_30_153 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_30_165 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_30_176 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_30_177 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_30_188 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_30_189 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_30_195 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -5709,30 +5749,38 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_31_125 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_31_125 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_31_137 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_31_133 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_31_169 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_31_155 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_31_173 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_31_164 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_8 FILLER_0_31_181 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_31_176 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_31_212 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_31_203 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); + sky130_fd_sc_hd__decap_8 FILLER_0_31_215 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_31_223 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); sky130_ef_sc_hd__decap_12 FILLER_0_31_225 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -5837,39 +5885,35 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_32_141 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_32_151 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_32_175 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_32_186 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_32_179 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_32_192 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_32_194 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_32_197 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_32_208 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_32_207 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_32_220 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_32_219 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_32_232 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_32_231 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_32_244 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_32_243 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_32_251 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -5969,31 +6013,23 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_33_145 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_33_145 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_33_157 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_33_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_33_179 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_33_183 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_33_188 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_33_189 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_33_192 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_33_204 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_33_216 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_33_222 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6093,39 +6129,47 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_34_133 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_34_133 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_34_141 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_34_139 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_34_171 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_34_141 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_34_176 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_34_145 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_34_180 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_34_175 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_34_188 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_34_201 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_34_206 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_226 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_34_217 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_34_238 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_34_229 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__fill_2 FILLER_0_34_250 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_34_241 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_34_249 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6217,23 +6261,23 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_35_125 (.VGND(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_35_125 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_3 FILLER_0_35_165 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_35_133 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_35_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_194 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_35_206 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_35_177 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_35_218 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_35_203 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6341,35 +6385,31 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_141 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__fill_2 FILLER_0_36_153 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_36_161 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_36_141 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_36_186 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_36_179 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_36_193 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_36_197 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_220 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_36_221 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_232 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_36_233 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_36_244 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_36_245 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_36_251 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6465,23 +6505,15 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_4 FILLER_0_37_137 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_37_137 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_37_164 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_37_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_37_169 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_37_219 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_223 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_177 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6509,23 +6541,23 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_281 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_37_290 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_293 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_37_302 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_305 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_37_314 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_317 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_37_326 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_329 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_37_334 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6601,11 +6633,15 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_130 (.VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_130 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_38_136 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_167 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_38_164 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6613,26 +6649,30 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_181 (.VPWR(VPWR), + sky130_fd_sc_hd__decap_8 FILLER_0_38_181 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_38_189 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_38_197 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_193 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_209 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_8 FILLER_0_38_197 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_38_217 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_205 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_223 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_212 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); sky130_ef_sc_hd__decap_12 FILLER_0_38_225 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -6661,7 +6701,11 @@ module tt_um_senolgulgonul (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_38_293 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_293 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_38_298 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6681,20 +6725,18 @@ module tt_um_senolgulgonul (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - assign uio_oe[0] = net11; - assign uio_oe[1] = net12; - assign uio_oe[2] = net13; - assign uio_oe[3] = net14; - assign uio_oe[4] = net15; - assign uio_oe[5] = net16; - assign uio_oe[6] = net17; - assign uio_oe[7] = net18; - assign uio_out[0] = net3; - assign uio_out[1] = net4; - assign uio_out[2] = net5; - assign uio_out[3] = net6; - assign uio_out[4] = net7; - assign uio_out[5] = net8; - assign uio_out[6] = net9; - assign uio_out[7] = net10; + assign uio_oe[0] = net12; + assign uio_oe[1] = net13; + assign uio_oe[2] = net14; + assign uio_oe[3] = net15; + assign uio_oe[4] = net16; + assign uio_oe[5] = net17; + assign uio_oe[6] = net18; + assign uio_oe[7] = net19; + assign uio_out[2] = net6; + assign uio_out[3] = net7; + assign uio_out[4] = net8; + assign uio_out[5] = net9; + assign uio_out[6] = net10; + assign uio_out[7] = net11; endmodule