From 90ef82c437e81b7b6e74aa4a41e3920e68389419 Mon Sep 17 00:00:00 2001 From: TinyTapeoutBot <139130078+TinyTapeoutBot@users.noreply.github.com> Date: Sun, 10 Nov 2024 13:50:50 +0200 Subject: [PATCH] feat: update project tt_um_wokwi_414120349028170753 from leahcorbett18/LeahsFirstDesign Commit: f3d251c8f093999aaf9303c36362f007ecc60c5d Workflow: https://github.com/leahcorbett18/LeahsFirstDesign/actions/runs/11764833643 --- .../commit_id.json | 2 +- .../stats/metrics.csv | 116 +++---- .../stats/synthesis-stats.txt | 62 ++-- .../tt_um_wokwi_414120349028170753.gds | Bin 374840 -> 400452 bytes .../tt_um_wokwi_414120349028170753.lef | 97 +++--- .../tt_um_wokwi_414120349028170753.v | 322 ++++++++++++------ .../wokwi-diagram.json | 99 ++++-- 7 files changed, 430 insertions(+), 268 deletions(-) diff --git a/projects/tt_um_wokwi_414120349028170753/commit_id.json b/projects/tt_um_wokwi_414120349028170753/commit_id.json index 744cf05b..ada1b8b0 100644 --- a/projects/tt_um_wokwi_414120349028170753/commit_id.json +++ b/projects/tt_um_wokwi_414120349028170753/commit_id.json @@ -2,7 +2,7 @@ "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/leahcorbett18/LeahsFirstDesign", "commit": "f3d251c8f093999aaf9303c36362f007ecc60c5d", - "workflow_url": "https://github.com/leahcorbett18/LeahsFirstDesign/actions/runs/11760805552", + "workflow_url": "https://github.com/leahcorbett18/LeahsFirstDesign/actions/runs/11764833643", "sort_id": 1731202318047, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv b/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv index 437d46e9..9782e26b 100644 --- a/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv +++ b/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv @@ -1,23 +1,23 @@ Metric,Value design__lint_error__count,0 design__lint_timing_construct__count,0 -design__lint_warning__count,3 +design__lint_warning__count,0 design__inferred_latch__count,0 -design__instance__count,251 -design__instance__area,389.123 +design__instance__count,264 +design__instance__area,454.186 design__instance_unmapped__count,0 synthesis__check_error__count,0 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 -power__internal__total,3.150396707951586E-7 -power__switching__total,0.0000013010220527576166 -power__leakage__total,1.333226862243464E-9 -power__total,0.0000016173949006770272 +power__internal__total,0.0000014038823792361654 +power__switching__total,0.0000031479503377340734 +power__leakage__total,1.359440671144796E-9 +power__total,0.0000045531919568020385 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0 -timing__hold__ws__corner:nom_tt_025C_1v80,7.930767378404763 -timing__setup__ws__corner:nom_tt_025C_1v80,11.519813873325104 +timing__hold__ws__corner:nom_tt_025C_1v80,8.094457777606557 +timing__setup__ws__corner:nom_tt_025C_1v80,10.730094450006046 timing__hold__tns__corner:nom_tt_025C_1v80,0.0 timing__setup__tns__corner:nom_tt_025C_1v80,0.0 timing__hold__wns__corner:nom_tt_025C_1v80,0 @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0 -timing__hold__ws__corner:nom_ss_100C_1v60,8.101794131560766 -timing__setup__ws__corner:nom_ss_100C_1v60,11.356924611080537 +timing__hold__ws__corner:nom_ss_100C_1v60,8.360269158036811 +timing__setup__ws__corner:nom_ss_100C_1v60,9.599639577187093 timing__hold__tns__corner:nom_ss_100C_1v60,0.0 timing__setup__tns__corner:nom_ss_100C_1v60,0.0 timing__hold__wns__corner:nom_ss_100C_1v60,0 @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0 -timing__hold__ws__corner:nom_ff_n40C_1v95,7.867758223172376 -timing__setup__ws__corner:nom_ff_n40C_1v95,11.5879220610092 +timing__hold__ws__corner:nom_ff_n40C_1v95,7.987118748014782 +timing__setup__ws__corner:nom_ff_n40C_1v95,11.113675627684033 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 timing__hold__wns__corner:nom_ff_n40C_1v95,0 @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0 design__max_cap_violation__count,0 clock__skew__worst_hold,0.0 clock__skew__worst_setup,0.0 -timing__hold__ws,7.866922447255801 -timing__setup__ws,11.354212114110059 +timing__hold__ws,7.9865805118772215 +timing__setup__ws,9.598248689742505 timing__hold__tns,0.0 timing__setup__tns,0.0 timing__hold__wns,0 @@ -86,54 +86,54 @@ flow__errors__count,0 design__io,45 design__die__area,17954.7 design__core__area,16493.3 -design__instance__count__stdcell,251 -design__instance__area__stdcell,389.123 +design__instance__count__stdcell,264 +design__instance__area__stdcell,454.186 design__instance__count__macros,0 design__instance__area__macros,0 -design__instance__utilization,0.0235928 -design__instance__utilization__stdcell,0.0235928 +design__instance__utilization,0.0275376 +design__instance__utilization__stdcell,0.0275376 design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count__net:VPWR,0 design__power_grid_violation__count,0 -timing__drv__floating__nets,2 +timing__drv__floating__nets,0 timing__drv__floating__pins,0 design__instance__displacement__total,0 design__instance__displacement__mean,0 design__instance__displacement__max,0 -route__wirelength__estimated,312.821 +route__wirelength__estimated,404.455 design__violations,0 design__instance__count__setup_buffer,0 design__instance__count__hold_buffer,0 antenna__violating__nets,0 antenna__violating__pins,0 route__antenna_violation__count,0 -route__net,47 +route__net,58 route__net__special,2 -route__drc_errors__iter:1,33 -route__wirelength__iter:1,314 +route__drc_errors__iter:1,25 +route__wirelength__iter:1,364 route__drc_errors__iter:2,0 -route__wirelength__iter:2,277 +route__wirelength__iter:2,364 route__drc_errors,0 -route__wirelength,277 -route__vias,119 -route__vias__singlecut,119 +route__wirelength,364 +route__vias,180 +route__vias__singlecut,180 route__vias__multicut,0 -design__disconnected_pin__count,15 +design__disconnected_pin__count,13 design__critical_disconnected_pin__count,0 -route__wirelength__max,46.22 -timing__unannotated_net__count__corner:nom_tt_025C_1v80,35 +route__wirelength__max,41.8 +timing__unannotated_net__count__corner:nom_tt_025C_1v80,45 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 -timing__unannotated_net__count__corner:nom_ss_100C_1v60,35 +timing__unannotated_net__count__corner:nom_ss_100C_1v60,45 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 -timing__unannotated_net__count__corner:nom_ff_n40C_1v95,35 +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,45 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count__corner:min_tt_025C_1v80,0 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0 design__max_cap_violation__count__corner:min_tt_025C_1v80,0 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0 -timing__hold__ws__corner:min_tt_025C_1v80,7.929630509995394 -timing__setup__ws__corner:min_tt_025C_1v80,11.523804459077677 +timing__hold__ws__corner:min_tt_025C_1v80,8.093794308308276 +timing__setup__ws__corner:min_tt_025C_1v80,10.730892034249493 timing__hold__tns__corner:min_tt_025C_1v80,0.0 timing__setup__tns__corner:min_tt_025C_1v80,0.0 timing__hold__wns__corner:min_tt_025C_1v80,0 @@ -144,15 +144,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 timing__setup_vio__count__corner:min_tt_025C_1v80,0 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 -timing__unannotated_net__count__corner:min_tt_025C_1v80,35 +timing__unannotated_net__count__corner:min_tt_025C_1v80,45 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 design__max_slew_violation__count__corner:min_ss_100C_1v60,0 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0 design__max_cap_violation__count__corner:min_ss_100C_1v60,0 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0 -timing__hold__ws__corner:min_ss_100C_1v60,8.09967937868365 -timing__setup__ws__corner:min_ss_100C_1v60,11.363291074173004 +timing__hold__ws__corner:min_ss_100C_1v60,8.35931258985174 +timing__setup__ws__corner:min_ss_100C_1v60,9.600949640393202 timing__hold__tns__corner:min_ss_100C_1v60,0.0 timing__setup__tns__corner:min_ss_100C_1v60,0.0 timing__hold__wns__corner:min_ss_100C_1v60,0 @@ -163,15 +163,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 timing__setup_vio__count__corner:min_ss_100C_1v60,0 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 -timing__unannotated_net__count__corner:min_ss_100C_1v60,35 +timing__unannotated_net__count__corner:min_ss_100C_1v60,45 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0 -timing__hold__ws__corner:min_ff_n40C_1v95,7.866922447255801 -timing__setup__ws__corner:min_ff_n40C_1v95,11.590797982813525 +timing__hold__ws__corner:min_ff_n40C_1v95,7.9865805118772215 +timing__setup__ws__corner:min_ff_n40C_1v95,11.114298240773852 timing__hold__tns__corner:min_ff_n40C_1v95,0.0 timing__setup__tns__corner:min_ff_n40C_1v95,0.0 timing__hold__wns__corner:min_ff_n40C_1v95,0 @@ -182,15 +182,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:min_ff_n40C_1v95,35 +timing__unannotated_net__count__corner:min_ff_n40C_1v95,45 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 design__max_slew_violation__count__corner:max_tt_025C_1v80,0 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0 design__max_cap_violation__count__corner:max_tt_025C_1v80,0 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0 -timing__hold__ws__corner:max_tt_025C_1v80,7.931997505550838 -timing__setup__ws__corner:max_tt_025C_1v80,11.51798689026411 +timing__hold__ws__corner:max_tt_025C_1v80,8.09554757255835 +timing__setup__ws__corner:max_tt_025C_1v80,10.729207159739671 timing__hold__tns__corner:max_tt_025C_1v80,0.0 timing__setup__tns__corner:max_tt_025C_1v80,0.0 timing__hold__wns__corner:max_tt_025C_1v80,0 @@ -201,15 +201,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 timing__setup_vio__count__corner:max_tt_025C_1v80,0 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 -timing__unannotated_net__count__corner:max_tt_025C_1v80,35 +timing__unannotated_net__count__corner:max_tt_025C_1v80,45 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 design__max_slew_violation__count__corner:max_ss_100C_1v60,0 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0 design__max_cap_violation__count__corner:max_ss_100C_1v60,0 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0 -timing__hold__ws__corner:max_ss_100C_1v60,8.10393641796967 -timing__setup__ws__corner:max_ss_100C_1v60,11.354212114110059 +timing__hold__ws__corner:max_ss_100C_1v60,8.36179504860501 +timing__setup__ws__corner:max_ss_100C_1v60,9.598248689742505 timing__hold__tns__corner:max_ss_100C_1v60,0.0 timing__setup__tns__corner:max_ss_100C_1v60,0.0 timing__hold__wns__corner:max_ss_100C_1v60,0 @@ -220,15 +220,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 timing__setup_vio__count__corner:max_ss_100C_1v60,0 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 -timing__unannotated_net__count__corner:max_ss_100C_1v60,35 +timing__unannotated_net__count__corner:max_ss_100C_1v60,45 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0 -timing__hold__ws__corner:max_ff_n40C_1v95,7.868741436710791 -timing__setup__ws__corner:max_ff_n40C_1v95,11.586510745460382 +timing__hold__ws__corner:max_ff_n40C_1v95,7.988088638876525 +timing__setup__ws__corner:max_ff_n40C_1v95,11.112944656823947 timing__hold__tns__corner:max_ff_n40C_1v95,0.0 timing__setup__tns__corner:max_ff_n40C_1v95,0.0 timing__hold__wns__corner:max_ff_n40C_1v95,0 @@ -239,19 +239,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:max_ff_n40C_1v95,35 +timing__unannotated_net__count__corner:max_ff_n40C_1v95,45 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count,35 +timing__unannotated_net__count,45 timing__unannotated_net_filtered__count,0 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8 -design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000189768 -design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000238946 -design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.30822E-8 -design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000238946 +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000291159 +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000053732 +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,9.58821E-8 +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000053732 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 -ir__drop__avg,3.069999999999999696964069774950123470347307375050149857997894287109375E-8 -ir__drop__worst,0.00000190000000000000001990053087597143388620679615996778011322021484375 +ir__drop__avg,8.0599999999999993811598971403531432855515959090553224086761474609375E-8 +ir__drop__worst,0.0000029100000000000000906631540675828517805712181143462657928466796875 magic__drc_error__count,0 magic__illegal_overlap__count,0 design__lvs_device_difference__count,0 diff --git a/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt b/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt index ca166310..ff1011be 100644 --- a/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt +++ b/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt @@ -28,44 +28,62 @@ Chip area for module '\not_cell': 3.753600 +=== or_cell === + + Number of wires: 3 + Number of wire bits: 3 + Number of public wires: 3 + Number of public wire bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + sky130_fd_sc_hd__or2_2 1 + + Chip area for module '\or_cell': 6.256000 + === tt_um_wokwi_414120349028170753 === - Number of wires: 10 - Number of wire bits: 45 - Number of public wires: 10 - Number of public wire bits: 45 + Number of wires: 17 + Number of wire bits: 52 + Number of public wires: 17 + Number of public wire bits: 52 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - and_cell 1 - not_cell 1 - sky130_fd_sc_hd__buf_2 6 - sky130_fd_sc_hd__conb_1 18 + Number of cells: 33 + and_cell 2 + not_cell 2 + or_cell 5 + sky130_fd_sc_hd__buf_2 7 + sky130_fd_sc_hd__conb_1 17 Area for cell type \and_cell is unknown! Area for cell type \not_cell is unknown! + Area for cell type \or_cell is unknown! - Chip area for module '\tt_um_wokwi_414120349028170753': 97.593600 + Chip area for module '\tt_um_wokwi_414120349028170753': 98.844800 === design hierarchy === tt_um_wokwi_414120349028170753 1 - and_cell 1 - not_cell 1 + and_cell 2 + not_cell 2 + or_cell 5 - Number of wires: 15 - Number of wire bits: 50 - Number of public wires: 15 - Number of public wire bits: 50 + Number of wires: 42 + Number of wire bits: 77 + Number of public wires: 42 + Number of public wire bits: 77 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - sky130_fd_sc_hd__and2_2 1 - sky130_fd_sc_hd__buf_2 6 - sky130_fd_sc_hd__conb_1 18 - sky130_fd_sc_hd__inv_2 1 + Number of cells: 33 + sky130_fd_sc_hd__and2_2 2 + sky130_fd_sc_hd__buf_2 7 + sky130_fd_sc_hd__conb_1 17 + sky130_fd_sc_hd__inv_2 2 + sky130_fd_sc_hd__or2_2 5 - Chip area for top module '\tt_um_wokwi_414120349028170753': 108.854400 + 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