diff --git a/projects/tt_um_wokwi_414120349028170753/commit_id.json b/projects/tt_um_wokwi_414120349028170753/commit_id.json index 744cf05b..ada1b8b0 100644 --- a/projects/tt_um_wokwi_414120349028170753/commit_id.json +++ b/projects/tt_um_wokwi_414120349028170753/commit_id.json @@ -2,7 +2,7 @@ "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/leahcorbett18/LeahsFirstDesign", "commit": "f3d251c8f093999aaf9303c36362f007ecc60c5d", - "workflow_url": "https://github.com/leahcorbett18/LeahsFirstDesign/actions/runs/11760805552", + "workflow_url": "https://github.com/leahcorbett18/LeahsFirstDesign/actions/runs/11764833643", "sort_id": 1731202318047, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv b/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv index 437d46e9..9782e26b 100644 --- a/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv +++ b/projects/tt_um_wokwi_414120349028170753/stats/metrics.csv @@ -1,23 +1,23 @@ Metric,Value design__lint_error__count,0 design__lint_timing_construct__count,0 -design__lint_warning__count,3 +design__lint_warning__count,0 design__inferred_latch__count,0 -design__instance__count,251 -design__instance__area,389.123 +design__instance__count,264 +design__instance__area,454.186 design__instance_unmapped__count,0 synthesis__check_error__count,0 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 -power__internal__total,3.150396707951586E-7 -power__switching__total,0.0000013010220527576166 -power__leakage__total,1.333226862243464E-9 -power__total,0.0000016173949006770272 +power__internal__total,0.0000014038823792361654 +power__switching__total,0.0000031479503377340734 +power__leakage__total,1.359440671144796E-9 +power__total,0.0000045531919568020385 clock__skew__worst_hold__corner:nom_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:nom_tt_025C_1v80,0.0 -timing__hold__ws__corner:nom_tt_025C_1v80,7.930767378404763 -timing__setup__ws__corner:nom_tt_025C_1v80,11.519813873325104 +timing__hold__ws__corner:nom_tt_025C_1v80,8.094457777606557 +timing__setup__ws__corner:nom_tt_025C_1v80,10.730094450006046 timing__hold__tns__corner:nom_tt_025C_1v80,0.0 timing__setup__tns__corner:nom_tt_025C_1v80,0.0 timing__hold__wns__corner:nom_tt_025C_1v80,0 @@ -33,8 +33,8 @@ design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 clock__skew__worst_hold__corner:nom_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:nom_ss_100C_1v60,0.0 -timing__hold__ws__corner:nom_ss_100C_1v60,8.101794131560766 -timing__setup__ws__corner:nom_ss_100C_1v60,11.356924611080537 +timing__hold__ws__corner:nom_ss_100C_1v60,8.360269158036811 +timing__setup__ws__corner:nom_ss_100C_1v60,9.599639577187093 timing__hold__tns__corner:nom_ss_100C_1v60,0.0 timing__setup__tns__corner:nom_ss_100C_1v60,0.0 timing__hold__wns__corner:nom_ss_100C_1v60,0 @@ -50,8 +50,8 @@ design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 clock__skew__worst_hold__corner:nom_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:nom_ff_n40C_1v95,0.0 -timing__hold__ws__corner:nom_ff_n40C_1v95,7.867758223172376 -timing__setup__ws__corner:nom_ff_n40C_1v95,11.5879220610092 +timing__hold__ws__corner:nom_ff_n40C_1v95,7.987118748014782 +timing__setup__ws__corner:nom_ff_n40C_1v95,11.113675627684033 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 timing__hold__wns__corner:nom_ff_n40C_1v95,0 @@ -67,8 +67,8 @@ design__max_fanout_violation__count,0 design__max_cap_violation__count,0 clock__skew__worst_hold,0.0 clock__skew__worst_setup,0.0 -timing__hold__ws,7.866922447255801 -timing__setup__ws,11.354212114110059 +timing__hold__ws,7.9865805118772215 +timing__setup__ws,9.598248689742505 timing__hold__tns,0.0 timing__setup__tns,0.0 timing__hold__wns,0 @@ -86,54 +86,54 @@ flow__errors__count,0 design__io,45 design__die__area,17954.7 design__core__area,16493.3 -design__instance__count__stdcell,251 -design__instance__area__stdcell,389.123 +design__instance__count__stdcell,264 +design__instance__area__stdcell,454.186 design__instance__count__macros,0 design__instance__area__macros,0 -design__instance__utilization,0.0235928 -design__instance__utilization__stdcell,0.0235928 +design__instance__utilization,0.0275376 +design__instance__utilization__stdcell,0.0275376 design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count__net:VPWR,0 design__power_grid_violation__count,0 -timing__drv__floating__nets,2 +timing__drv__floating__nets,0 timing__drv__floating__pins,0 design__instance__displacement__total,0 design__instance__displacement__mean,0 design__instance__displacement__max,0 -route__wirelength__estimated,312.821 +route__wirelength__estimated,404.455 design__violations,0 design__instance__count__setup_buffer,0 design__instance__count__hold_buffer,0 antenna__violating__nets,0 antenna__violating__pins,0 route__antenna_violation__count,0 -route__net,47 +route__net,58 route__net__special,2 -route__drc_errors__iter:1,33 -route__wirelength__iter:1,314 +route__drc_errors__iter:1,25 +route__wirelength__iter:1,364 route__drc_errors__iter:2,0 -route__wirelength__iter:2,277 +route__wirelength__iter:2,364 route__drc_errors,0 -route__wirelength,277 -route__vias,119 -route__vias__singlecut,119 +route__wirelength,364 +route__vias,180 +route__vias__singlecut,180 route__vias__multicut,0 -design__disconnected_pin__count,15 +design__disconnected_pin__count,13 design__critical_disconnected_pin__count,0 -route__wirelength__max,46.22 -timing__unannotated_net__count__corner:nom_tt_025C_1v80,35 +route__wirelength__max,41.8 +timing__unannotated_net__count__corner:nom_tt_025C_1v80,45 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 -timing__unannotated_net__count__corner:nom_ss_100C_1v60,35 +timing__unannotated_net__count__corner:nom_ss_100C_1v60,45 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 -timing__unannotated_net__count__corner:nom_ff_n40C_1v95,35 +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,45 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count__corner:min_tt_025C_1v80,0 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0 design__max_cap_violation__count__corner:min_tt_025C_1v80,0 clock__skew__worst_hold__corner:min_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:min_tt_025C_1v80,0.0 -timing__hold__ws__corner:min_tt_025C_1v80,7.929630509995394 -timing__setup__ws__corner:min_tt_025C_1v80,11.523804459077677 +timing__hold__ws__corner:min_tt_025C_1v80,8.093794308308276 +timing__setup__ws__corner:min_tt_025C_1v80,10.730892034249493 timing__hold__tns__corner:min_tt_025C_1v80,0.0 timing__setup__tns__corner:min_tt_025C_1v80,0.0 timing__hold__wns__corner:min_tt_025C_1v80,0 @@ -144,15 +144,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 timing__setup_vio__count__corner:min_tt_025C_1v80,0 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 -timing__unannotated_net__count__corner:min_tt_025C_1v80,35 +timing__unannotated_net__count__corner:min_tt_025C_1v80,45 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 design__max_slew_violation__count__corner:min_ss_100C_1v60,0 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0 design__max_cap_violation__count__corner:min_ss_100C_1v60,0 clock__skew__worst_hold__corner:min_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:min_ss_100C_1v60,0.0 -timing__hold__ws__corner:min_ss_100C_1v60,8.09967937868365 -timing__setup__ws__corner:min_ss_100C_1v60,11.363291074173004 +timing__hold__ws__corner:min_ss_100C_1v60,8.35931258985174 +timing__setup__ws__corner:min_ss_100C_1v60,9.600949640393202 timing__hold__tns__corner:min_ss_100C_1v60,0.0 timing__setup__tns__corner:min_ss_100C_1v60,0.0 timing__hold__wns__corner:min_ss_100C_1v60,0 @@ -163,15 +163,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 timing__setup_vio__count__corner:min_ss_100C_1v60,0 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 -timing__unannotated_net__count__corner:min_ss_100C_1v60,35 +timing__unannotated_net__count__corner:min_ss_100C_1v60,45 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 clock__skew__worst_hold__corner:min_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:min_ff_n40C_1v95,0.0 -timing__hold__ws__corner:min_ff_n40C_1v95,7.866922447255801 -timing__setup__ws__corner:min_ff_n40C_1v95,11.590797982813525 +timing__hold__ws__corner:min_ff_n40C_1v95,7.9865805118772215 +timing__setup__ws__corner:min_ff_n40C_1v95,11.114298240773852 timing__hold__tns__corner:min_ff_n40C_1v95,0.0 timing__setup__tns__corner:min_ff_n40C_1v95,0.0 timing__hold__wns__corner:min_ff_n40C_1v95,0 @@ -182,15 +182,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:min_ff_n40C_1v95,35 +timing__unannotated_net__count__corner:min_ff_n40C_1v95,45 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 design__max_slew_violation__count__corner:max_tt_025C_1v80,0 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0 design__max_cap_violation__count__corner:max_tt_025C_1v80,0 clock__skew__worst_hold__corner:max_tt_025C_1v80,0.0 clock__skew__worst_setup__corner:max_tt_025C_1v80,0.0 -timing__hold__ws__corner:max_tt_025C_1v80,7.931997505550838 -timing__setup__ws__corner:max_tt_025C_1v80,11.51798689026411 +timing__hold__ws__corner:max_tt_025C_1v80,8.09554757255835 +timing__setup__ws__corner:max_tt_025C_1v80,10.729207159739671 timing__hold__tns__corner:max_tt_025C_1v80,0.0 timing__setup__tns__corner:max_tt_025C_1v80,0.0 timing__hold__wns__corner:max_tt_025C_1v80,0 @@ -201,15 +201,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 timing__setup_vio__count__corner:max_tt_025C_1v80,0 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 -timing__unannotated_net__count__corner:max_tt_025C_1v80,35 +timing__unannotated_net__count__corner:max_tt_025C_1v80,45 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 design__max_slew_violation__count__corner:max_ss_100C_1v60,0 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0 design__max_cap_violation__count__corner:max_ss_100C_1v60,0 clock__skew__worst_hold__corner:max_ss_100C_1v60,0.0 clock__skew__worst_setup__corner:max_ss_100C_1v60,0.0 -timing__hold__ws__corner:max_ss_100C_1v60,8.10393641796967 -timing__setup__ws__corner:max_ss_100C_1v60,11.354212114110059 +timing__hold__ws__corner:max_ss_100C_1v60,8.36179504860501 +timing__setup__ws__corner:max_ss_100C_1v60,9.598248689742505 timing__hold__tns__corner:max_ss_100C_1v60,0.0 timing__setup__tns__corner:max_ss_100C_1v60,0.0 timing__hold__wns__corner:max_ss_100C_1v60,0 @@ -220,15 +220,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 timing__setup_vio__count__corner:max_ss_100C_1v60,0 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 -timing__unannotated_net__count__corner:max_ss_100C_1v60,35 +timing__unannotated_net__count__corner:max_ss_100C_1v60,45 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 clock__skew__worst_hold__corner:max_ff_n40C_1v95,0.0 clock__skew__worst_setup__corner:max_ff_n40C_1v95,0.0 -timing__hold__ws__corner:max_ff_n40C_1v95,7.868741436710791 -timing__setup__ws__corner:max_ff_n40C_1v95,11.586510745460382 +timing__hold__ws__corner:max_ff_n40C_1v95,7.988088638876525 +timing__setup__ws__corner:max_ff_n40C_1v95,11.112944656823947 timing__hold__tns__corner:max_ff_n40C_1v95,0.0 timing__setup__tns__corner:max_ff_n40C_1v95,0.0 timing__hold__wns__corner:max_ff_n40C_1v95,0 @@ -239,19 +239,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:max_ff_n40C_1v95,35 +timing__unannotated_net__count__corner:max_ff_n40C_1v95,45 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count,35 +timing__unannotated_net__count,45 timing__unannotated_net_filtered__count,0 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.8 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8 -design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000189768 -design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000238946 -design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,3.30822E-8 -design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.00000238946 +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.00000291159 +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000053732 +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,9.58821E-8 +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000053732 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 -ir__drop__avg,3.069999999999999696964069774950123470347307375050149857997894287109375E-8 -ir__drop__worst,0.00000190000000000000001990053087597143388620679615996778011322021484375 +ir__drop__avg,8.0599999999999993811598971403531432855515959090553224086761474609375E-8 +ir__drop__worst,0.0000029100000000000000906631540675828517805712181143462657928466796875 magic__drc_error__count,0 magic__illegal_overlap__count,0 design__lvs_device_difference__count,0 diff --git a/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt b/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt index ca166310..ff1011be 100644 --- a/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt +++ b/projects/tt_um_wokwi_414120349028170753/stats/synthesis-stats.txt @@ -28,44 +28,62 @@ Chip area for module '\not_cell': 3.753600 +=== or_cell === + + Number of wires: 3 + Number of wire bits: 3 + Number of public wires: 3 + Number of public wire bits: 3 + Number of memories: 0 + Number of memory bits: 0 + Number of processes: 0 + Number of cells: 1 + sky130_fd_sc_hd__or2_2 1 + + Chip area for module '\or_cell': 6.256000 + === tt_um_wokwi_414120349028170753 === - Number of wires: 10 - Number of wire bits: 45 - Number of public wires: 10 - Number of public wire bits: 45 + Number of wires: 17 + Number of wire bits: 52 + Number of public wires: 17 + Number of public wire bits: 52 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - and_cell 1 - not_cell 1 - sky130_fd_sc_hd__buf_2 6 - sky130_fd_sc_hd__conb_1 18 + Number of cells: 33 + and_cell 2 + not_cell 2 + or_cell 5 + sky130_fd_sc_hd__buf_2 7 + sky130_fd_sc_hd__conb_1 17 Area for cell type \and_cell is unknown! Area for cell type \not_cell is unknown! + Area for cell type \or_cell is unknown! - Chip area for module '\tt_um_wokwi_414120349028170753': 97.593600 + Chip area for module '\tt_um_wokwi_414120349028170753': 98.844800 === design hierarchy === tt_um_wokwi_414120349028170753 1 - and_cell 1 - not_cell 1 + and_cell 2 + not_cell 2 + or_cell 5 - Number of wires: 15 - Number of wire bits: 50 - Number of public wires: 15 - Number of public wire bits: 50 + Number of wires: 42 + Number of wire bits: 77 + Number of public wires: 42 + Number of public wire bits: 77 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 26 - sky130_fd_sc_hd__and2_2 1 - sky130_fd_sc_hd__buf_2 6 - sky130_fd_sc_hd__conb_1 18 - sky130_fd_sc_hd__inv_2 1 + Number of cells: 33 + sky130_fd_sc_hd__and2_2 2 + sky130_fd_sc_hd__buf_2 7 + sky130_fd_sc_hd__conb_1 17 + sky130_fd_sc_hd__inv_2 2 + sky130_fd_sc_hd__or2_2 5 - Chip area for top module '\tt_um_wokwi_414120349028170753': 108.854400 + Chip area for top module '\tt_um_wokwi_414120349028170753': 152.646400 diff --git a/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.gds b/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.gds index 0a04d61c..785af99d 100644 Binary files a/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.gds and b/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.gds differ diff --git a/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.lef b/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.lef index c359fe14..9c906da8 100644 --- a/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.lef +++ b/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.lef @@ -74,6 +74,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[0] DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 138.310 110.520 138.610 111.520 ; @@ -82,6 +83,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[1] DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 135.550 110.520 135.850 111.520 ; @@ -90,6 +92,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[2] DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 132.790 110.520 133.090 111.520 ; @@ -98,7 +101,6 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[3] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; PORT LAYER met4 ; RECT 130.030 110.520 130.330 111.520 ; @@ -107,7 +109,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[4] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 127.270 110.520 127.570 111.520 ; @@ -116,7 +118,6 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[5] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; PORT LAYER met4 ; RECT 124.510 110.520 124.810 111.520 ; @@ -125,7 +126,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[6] DIRECTION INPUT ; USE SIGNAL ; - ANTENNAGATEAREA 0.159000 ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 121.750 110.520 122.050 111.520 ; @@ -134,6 +135,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN ui_in[7] DIRECTION INPUT ; USE SIGNAL ; + ANTENNAGATEAREA 0.196500 ; PORT LAYER met4 ; RECT 118.990 110.520 119.290 111.520 ; @@ -334,6 +336,7 @@ MACRO tt_um_wokwi_414120349028170753 PIN uo_out[0] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 94.150 110.520 94.450 111.520 ; @@ -409,52 +412,56 @@ MACRO tt_um_wokwi_414120349028170753 LAYER met1 ; RECT 2.760 2.480 158.240 109.440 ; LAYER met2 ; - RECT 18.310 2.535 139.760 110.005 ; + RECT 18.310 2.535 139.760 110.685 ; LAYER met3 ; - RECT 18.290 2.555 139.780 109.985 ; - LAYER met4 ; - RECT 31.370 110.120 33.030 110.520 ; - RECT 34.130 110.120 35.790 110.520 ; - RECT 36.890 110.120 38.550 110.520 ; - RECT 39.650 110.120 41.310 110.520 ; - RECT 42.410 110.120 44.070 110.520 ; - RECT 45.170 110.120 46.830 110.520 ; - RECT 47.930 110.120 49.590 110.520 ; - RECT 50.690 110.120 52.350 110.520 ; - RECT 53.450 110.120 55.110 110.520 ; - RECT 56.210 110.120 57.870 110.520 ; - RECT 58.970 110.120 60.630 110.520 ; - RECT 61.730 110.120 63.390 110.520 ; - RECT 64.490 110.120 66.150 110.520 ; - RECT 67.250 110.120 68.910 110.520 ; - RECT 70.010 110.120 71.670 110.520 ; - RECT 72.770 110.120 74.430 110.520 ; - RECT 75.530 110.120 77.190 110.520 ; - RECT 78.290 110.120 79.950 110.520 ; - RECT 81.050 110.120 82.710 110.520 ; - RECT 83.810 110.120 85.470 110.520 ; - RECT 86.570 110.120 88.230 110.520 ; - RECT 89.330 110.120 90.990 110.520 ; - RECT 92.090 110.120 93.750 110.520 ; - RECT 94.850 110.120 96.510 110.520 ; - RECT 97.610 110.120 99.270 110.520 ; - RECT 100.370 110.120 102.030 110.520 ; - RECT 103.130 110.120 104.790 110.520 ; - RECT 105.890 110.120 107.550 110.520 ; - RECT 108.650 110.120 110.310 110.520 ; - RECT 111.410 110.120 113.070 110.520 ; - RECT 114.170 110.120 115.830 110.520 ; - RECT 116.930 110.120 118.590 110.520 ; - RECT 119.690 110.120 121.350 110.520 ; - RECT 122.450 110.120 124.110 110.520 ; - RECT 125.210 110.120 126.870 110.520 ; - RECT 127.970 110.120 129.630 110.520 ; - RECT 30.655 109.440 130.345 110.120 ; + RECT 18.290 2.555 139.780 110.665 ; + LAYER met4 ; + RECT 31.370 110.120 33.030 110.665 ; + RECT 34.130 110.120 35.790 110.665 ; + RECT 36.890 110.120 38.550 110.665 ; + RECT 39.650 110.120 41.310 110.665 ; + RECT 42.410 110.120 44.070 110.665 ; + RECT 45.170 110.120 46.830 110.665 ; + RECT 47.930 110.120 49.590 110.665 ; + RECT 50.690 110.120 52.350 110.665 ; + RECT 53.450 110.120 55.110 110.665 ; + RECT 56.210 110.120 57.870 110.665 ; + RECT 58.970 110.120 60.630 110.665 ; + RECT 61.730 110.120 63.390 110.665 ; + RECT 64.490 110.120 66.150 110.665 ; + RECT 67.250 110.120 68.910 110.665 ; + RECT 70.010 110.120 71.670 110.665 ; + RECT 72.770 110.120 74.430 110.665 ; + RECT 75.530 110.120 77.190 110.665 ; + RECT 78.290 110.120 79.950 110.665 ; + RECT 81.050 110.120 82.710 110.665 ; + RECT 83.810 110.120 85.470 110.665 ; + RECT 86.570 110.120 88.230 110.665 ; + RECT 89.330 110.120 90.990 110.665 ; + RECT 92.090 110.120 93.750 110.665 ; + RECT 94.850 110.120 96.510 110.665 ; + RECT 97.610 110.120 99.270 110.665 ; + RECT 100.370 110.120 102.030 110.665 ; + RECT 103.130 110.120 104.790 110.665 ; + RECT 105.890 110.120 107.550 110.665 ; + RECT 108.650 110.120 110.310 110.665 ; + RECT 111.410 110.120 113.070 110.665 ; + RECT 114.170 110.120 115.830 110.665 ; + RECT 116.930 110.120 118.590 110.665 ; + RECT 119.690 110.120 121.350 110.665 ; + RECT 122.450 110.120 124.110 110.665 ; + RECT 125.210 110.120 126.870 110.665 ; + RECT 127.970 110.120 129.630 110.665 ; + RECT 130.730 110.120 132.390 110.665 ; + RECT 133.490 110.120 135.150 110.665 ; + RECT 136.250 110.120 137.910 110.665 ; + RECT 30.655 109.440 138.625 110.120 ; RECT 30.655 105.575 56.750 109.440 ; RECT 59.150 105.575 60.050 109.440 ; RECT 62.450 105.575 95.620 109.440 ; RECT 98.020 105.575 98.920 109.440 ; - RECT 101.320 105.575 130.345 109.440 ; + RECT 101.320 105.575 134.490 109.440 ; + RECT 136.890 105.575 137.790 109.440 ; END END tt_um_wokwi_414120349028170753 END LIBRARY diff --git a/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.v b/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.v index 9a678c2e..93cb6d23 100644 --- a/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.v +++ b/projects/tt_um_wokwi_414120349028170753/tt_um_wokwi_414120349028170753.v @@ -19,167 +19,226 @@ module tt_um_wokwi_414120349028170753 (clk, output [7:0] uio_out; output [7:0] uo_out; + wire net10; + wire net11; wire net12; - wire net6; - wire net2; - wire net3; - wire net4; - wire net5; + wire net18; + wire net19; + wire net20; wire net7; wire net8; wire net9; - wire net10; - wire net11; - wire net13; wire net14; wire net15; wire net16; wire net17; - wire net18; - wire net19; - wire net20; - wire \and1/a ; - wire \and1/b ; + wire net21; + wire net22; + wire net23; + wire net24; + wire net25; + wire net26; + wire net27; + wire net28; + wire net29; + wire net30; + wire net31; + wire net32; wire net1; + wire net2; + wire net3; + wire net4; + wire net5; + wire net6; + wire net13; - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_2 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .LO(net2)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_3 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_8 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net3)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_4 (.VGND(VGND), + .LO(net14)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_9 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net4)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_5 (.VGND(VGND), + .LO(net15)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_10 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net5)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_6 (.VGND(VGND), + .LO(net16)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_11 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net7)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_7 (.VGND(VGND), + .LO(net17)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_12 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net8)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_8 (.VGND(VGND), + .LO(net21)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_13 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net9)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_9 (.VGND(VGND), + .LO(net22)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_14 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net10)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_10 (.VGND(VGND), + .LO(net23)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_15 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net11)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_11 (.VGND(VGND), + .LO(net24)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_16 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net13)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_12 (.VGND(VGND), + .LO(net25)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_17 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net14)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_13 (.VGND(VGND), + .LO(net26)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_18 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net15)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_14 (.VGND(VGND), + .LO(net27)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_19 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net16)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_15 (.VGND(VGND), + .LO(net28)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_20 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net17)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_16 (.VGND(VGND), + .LO(net29)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_21 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net18)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_17 (.VGND(VGND), + .LO(net30)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_22 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net19)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_18 (.VGND(VGND), + .LO(net31)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_23 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net20)); + .LO(net32)); sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__buf_2 _18_ (.A(net6), + sky130_fd_sc_hd__buf_2 _17_ (.A(net7), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[0])); + sky130_fd_sc_hd__buf_2 _18_ (.A(net8), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[1])); - sky130_fd_sc_hd__buf_2 _19_ (.A(net6), + sky130_fd_sc_hd__buf_2 _19_ (.A(net8), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[2])); - sky130_fd_sc_hd__buf_2 _20_ (.A(ui_in[3]), + sky130_fd_sc_hd__buf_2 _20_ (.A(net9), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[3])); - sky130_fd_sc_hd__buf_2 _21_ (.A(ui_in[4]), + sky130_fd_sc_hd__buf_2 _21_ (.A(net10), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[4])); - sky130_fd_sc_hd__buf_2 _22_ (.A(ui_in[5]), + sky130_fd_sc_hd__buf_2 _22_ (.A(net11), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[5])); - sky130_fd_sc_hd__buf_2 _23_ (.A(ui_in[6]), + sky130_fd_sc_hd__buf_2 _23_ (.A(net12), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[6])); - sky130_fd_sc_hd__and2_1 \and1/_0_ (.A(\and1/b ), - .B(\and1/a ), + sky130_fd_sc_hd__and2_1 \and1/_0_ (.A(net3), + .B(net2), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net18)); + sky130_fd_sc_hd__and2_1 \and2/_0_ (.A(net1), + .B(net19), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net20)); + sky130_fd_sc_hd__inv_2 \not1/_0_ (.A(net18), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net8)); + sky130_fd_sc_hd__inv_2 \not2/_0_ (.A(net18), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(net19)); + sky130_fd_sc_hd__or2_1 \or1/_0_ (.A(net4), + .B(net18), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(net12)); - sky130_fd_sc_hd__inv_2 \not1/_0_ (.A(net12), + sky130_fd_sc_hd__or2_1 \or2/_0_ (.A(net12), + .B(net20), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net11)); + sky130_fd_sc_hd__or2_1 \or3/_0_ (.A(net6), + .B(net20), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Y(net6)); + .X(net7)); + sky130_fd_sc_hd__or2_1 \or4/_0_ (.A(net20), + .B(net5), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net10)); + sky130_fd_sc_hd__or2_1 \or5/_0_ (.A(net20), + .B(net10), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net9)); sky130_fd_sc_hd__decap_3 PHY_EDGE_ROW_0_Right_0 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -942,11 +1001,47 @@ module tt_um_wokwi_414120349028170753 (clk, .VPWR(VPWR)); sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_TAPCELL_ROW_38_302 (.VGND(VGND), .VPWR(VPWR)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_1 (.VGND(VGND), + sky130_fd_sc_hd__clkbuf_1 input1 (.A(ui_in[0]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net1)); + sky130_fd_sc_hd__clkbuf_1 input2 (.A(ui_in[1]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net2)); + sky130_fd_sc_hd__clkbuf_1 input3 (.A(ui_in[2]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net3)); + sky130_fd_sc_hd__clkbuf_1 input4 (.A(ui_in[4]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net4)); + sky130_fd_sc_hd__clkbuf_1 input5 (.A(ui_in[6]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net5)); + sky130_fd_sc_hd__clkbuf_1 input6 (.A(ui_in[7]), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net6)); + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414120349028170753_7 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net1)); + .LO(net13)); sky130_ef_sc_hd__decap_12 FILLER_0_0_15 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -6271,27 +6366,31 @@ module tt_um_wokwi_414120349028170753 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_169 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_181 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_37_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_191 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_37_175 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_203 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_187 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_37_215 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_4 FILLER_0_37_196 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_223 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_200 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_37_208 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__decap_4 FILLER_0_37_220 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6439,15 +6538,15 @@ module tt_um_wokwi_414120349028170753 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_38_180 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_195 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_204 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_38_215 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_38_216 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_38_223 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6463,27 +6562,31 @@ module tt_um_wokwi_414120349028170753 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_253 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_256 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_265 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_38_262 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_277 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_38_270 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_281 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_38_274 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_293 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_38_292 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_305 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_38_298 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_38_306 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6499,22 +6602,21 @@ module tt_um_wokwi_414120349028170753 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - assign uio_oe[0] = net1; - assign uio_oe[1] = net2; - assign uio_oe[2] = net3; - assign uio_oe[3] = net4; - assign uio_oe[4] = net5; - assign uio_oe[5] = net7; - assign uio_oe[6] = net8; - assign uio_oe[7] = net9; - assign uio_out[0] = net10; - assign uio_out[1] = net11; - assign uio_out[2] = net13; - assign uio_out[3] = net14; - assign uio_out[4] = net15; - assign uio_out[5] = net16; - assign uio_out[6] = net17; - assign uio_out[7] = net18; - assign uo_out[0] = net19; - assign uo_out[7] = net20; + assign uio_oe[0] = net13; + assign uio_oe[1] = net14; + assign uio_oe[2] = net15; + assign uio_oe[3] = net16; + assign uio_oe[4] = net17; + assign uio_oe[5] = net21; + assign uio_oe[6] = net22; + assign uio_oe[7] = net23; + assign uio_out[0] = net24; + assign uio_out[1] = net25; + assign uio_out[2] = net26; + assign uio_out[3] = net27; + assign uio_out[4] = net28; + assign uio_out[5] = net29; + assign uio_out[6] = net30; + assign uio_out[7] = net31; + assign uo_out[7] = net32; endmodule diff --git a/projects/tt_um_wokwi_414120349028170753/wokwi-diagram.json b/projects/tt_um_wokwi_414120349028170753/wokwi-diagram.json index 6510dbc6..4562e912 100644 --- a/projects/tt_um_wokwi_414120349028170753/wokwi-diagram.json +++ b/projects/tt_um_wokwi_414120349028170753/wokwi-diagram.json @@ -18,13 +18,13 @@ "left": -115.2, "attrs": { "frequency": "10000" } }, - { "type": "wokwi-gnd", "id": "pwr2", "top": -57.6, "left": 642.6, "attrs": {} }, + { "type": "wokwi-gnd", "id": "pwr2", "top": -57.6, "left": 719.4, "attrs": {} }, { "type": "wokwi-vcc", "id": "pwr1", "top": -229.64, "left": -115.2, "attrs": {} }, { "type": "wokwi-7segment", "id": "sevseg1", "top": -187.02, - "left": 686.68, + "left": 849.88, "attrs": { "common": "cathode" } }, { @@ -60,64 +60,64 @@ { "type": "board-tt-block-output", "id": "ttout", - "top": -208.93, - "left": 523.2, + "top": -199.33, + "left": 667.2, "attrs": { "verilogRole": "output" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio0", - "top": 20.22, - "left": 148.8, + "top": 10.62, + "left": -216, "attrs": { "verilogRole": "bidirectional", "verilogBit": "0" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio1", "top": 58.62, - "left": 148.8, + "left": -216, "attrs": { "verilogRole": "bidirectional", "verilogBit": "1" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio2", - "top": 97.02, - "left": 148.8, + "top": 106.62, + "left": -216, "attrs": { "verilogRole": "bidirectional", "verilogBit": "2" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio3", - "top": 135.42, - "left": 148.8, + "top": 154.62, + "left": -216, "attrs": { "verilogRole": "bidirectional", "verilogBit": "3" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio4", - "top": 20.22, - "left": 273.6, + "top": 10.62, + "left": -72, "attrs": { "verilogRole": "bidirectional", "verilogBit": "4" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio5", "top": 58.62, - "left": 273.6, + "left": -72, "attrs": { "verilogRole": "bidirectional", "verilogBit": "5" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio6", - "top": 97.02, - "left": 273.6, + "top": 106.62, + "left": -72, "attrs": { "verilogRole": "bidirectional", "verilogBit": "6" } }, { "type": "board-tt-block-bidirectional-io", "id": "ttio7", - "top": 135.42, - "left": 273.6, + "top": 154.62, + "left": -72, "attrs": { "verilogRole": "bidirectional", "verilogBit": "7" } }, { @@ -131,13 +131,33 @@ { "type": "wokwi-text", "id": "text1", - "top": -18.98, - "left": 184.55, + "top": -28.8, + "left": -163.2, "attrs": { "text": "Bidirectional I/O pins" } }, - { "type": "wokwi-gate-and-2", "id": "and1", "top": -201.6, "left": 230.4, "attrs": {} }, - { "type": "wokwi-gate-or-2", "id": "or1", "top": -240, "left": 153.6, "attrs": {} }, - { "type": "wokwi-gate-not", "id": "not1", "top": -288, "left": 326.4, "attrs": {} } + { "type": "wokwi-gate-and-2", "id": "and1", "top": -336, "left": 201.6, "attrs": {} }, + { + "type": "wokwi-resistor", + "id": "r1", + "top": -399.25, + "left": 19.2, + "attrs": { "value": "1000" } + }, + { "type": "wokwi-gate-not", "id": "not1", "top": -326.4, "left": 336, "attrs": {} }, + { "type": "wokwi-gate-and-2", "id": "and2", "top": -240, "left": 489.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or1", "top": -134.4, "left": 278.4, "attrs": {} }, + { "type": "wokwi-gate-not", "id": "not2", "top": -268.8, "left": 307.2, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or2", "top": -172.8, "left": 345.6, "attrs": {} }, + { + "type": "wokwi-resistor", + "id": "r3", + "top": -360.85, + "left": 57.6, + "attrs": { "value": "1000" } + }, + { "type": "wokwi-gate-or-2", "id": "or3", "top": -38.4, "left": 345.6, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or4", "top": -105.6, "left": 384, "attrs": {} }, + { "type": "wokwi-gate-or-2", "id": "or5", "top": -19.2, "left": 528, "attrs": {} } ], "connections": [ [ "pwr1:VCC", "sw1:8a", "red", [ "v0" ] ], @@ -161,7 +181,7 @@ [ "ttout:EXTOUT5", "sevseg1:F", "green", [ "h69.01", "v-57.6", "h28.8" ] ], [ "ttout:EXTOUT6", "sevseg1:G", "green", [ "h78.61", "v-57.6" ] ], [ "ttout:EXTOUT7", "sevseg1:DP", "green", [ "v28.8", "h136.21" ] ], - [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v0" ] ], + [ "pwr2:GND", "sevseg1:COM.1", "black", [ "v-9.6", "h182.4" ] ], [ "sw2:1", "clock1:CLK", "blue", [ "h-19.2", "v-57.6" ] ], [ "sw1:1b", "ttin:EXTIN0", "green", [ "h0" ] ], [ "sw1:2b", "ttin:EXTIN1", "green", [ "h0" ] ], @@ -172,20 +192,35 @@ [ "sw1:7b", "ttin:EXTIN6", "green", [ "h0" ] ], [ "sw1:8b", "ttin:EXTIN7", "green", [ "v0" ] ], [ "sw2:2", "ttin:EXTCLK", "blue", [ "v0" ] ], - [ "ttin:IN4", "ttout:OUT4", "green", [ "h0" ] ], - [ "ttout:OUT5", "ttin:IN5", "green", [ "h0" ] ], - [ "ttin:IN6", "ttout:OUT6", "green", [ "h0" ] ], [ "btn1:1.l", "sw2:3", "blue", [ "h0" ] ], [ "pwr3:VCC", "btn1:2.r", "red", [ "v0" ] ], [ "btn2:2.l", "gnd1:GND", "black", [ "h0" ] ], [ "ttin:EXTRST_N", "btn2:1.r", "orange", [ "h-38.4", "v-96" ] ], [ "btn2:1.l", "r2:2", "green", [ "h0" ] ], [ "pwr5:VCC", "r2:1", "red", [ "v0" ] ], - [ "ttin:IN3", "ttout:OUT3", "green", [ "h0" ] ], - [ "and1:OUT", "not1:IN", "green", [ "v0" ] ], - [ "ttout:OUT1", "not1:OUT", "green", [ "h0" ] ], - [ "ttout:OUT2", "not1:OUT", "green", [ "h0" ] ], - [ "or1:A", "ttin:IN0", "green", [ "h-19.2", "v48" ] ] + [ "and1:B", "ttin:IN2", "green", [ "h-86.4", "v144" ] ], + [ "not1:IN", "and1:OUT", "green", [ "v-9.6", "h-57.6" ] ], + [ "not1:OUT", "ttout:OUT1", "green", [ "v0" ] ], + [ "not1:OUT", "ttout:OUT2", "green", [ "h76.8", "v48", "h134.4", "v105.6" ] ], + [ "or1:B", "ttin:IN4", "green", [ "h-76.8", "v-48" ] ], + [ "or1:A", "not1:IN", "green", [ "v-105.6", "h28.8", "v-86.4" ] ], + [ "and1:OUT", "not2:IN", "green", [ "v67.2", "h-57.6" ] ], + [ "not2:OUT", "and2:A", "green", [ "h28.8", "v19.2", "h19.2" ] ], + [ "ttin:IN1", "and1:A", "green", [ "h96", "v-153.6" ] ], + [ "and2:B", "ttin:IN0", "green", [ "h-364.8", "v28.8" ] ], + [ "and2:OUT", "or2:A", "green", [ "h-9.6", "v38.4", "h-220.8", "v0", "h-9.6" ] ], + [ "or2:B", "or1:OUT", "green", [ "h-86.4", "v96", "h134.4" ] ], + [ "ttout:OUT5", "or2:OUT", "green", [ "h-144", "v-28.8" ] ], + [ "and2:OUT", "or3:A", "green", [ "h9.6", "v163.2", "h-86.4" ] ], + [ "or3:OUT", "ttout:OUT0", "green", [ "h48", "v-115.2" ] ], + [ "ttin:IN7", "or3:B", "green", [ "v124.8", "h403.2" ] ], + [ "ttin:IN6", "or4:A", "green", [ "h144", "v38.4", "h134.4" ] ], + [ "or4:OUT", "ttout:OUT4", "green", [ "v0" ] ], + [ "or4:B", "and2:OUT", "green", [ "v28.8", "h201.6" ] ], + [ "or4:OUT", "or5:A", "green", [ "v0" ] ], + [ "or5:OUT", "ttout:OUT3", "green", [ "v-144", "h48" ] ], + [ "and2:OUT", "or5:B", "green", [ "v115.2", "h-57.6" ] ], + [ "ttout:OUT6", "or1:OUT", "green", [ "h0" ] ] ], "dependencies": {} } \ No newline at end of file