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feat: update project tt_um_snn_with_delays_paolaunisa from PaolaUniSa/tt09_chatGPT_SNN_LD
Commit: da31a93c483ec2a4e3d4100a2b7191a5074a3229 Workflow: https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11765791446
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projects/tt_um_snn_with_delays_paolaunisa/commit_id.json

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{
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"app": "Tiny Tapeout tt09 a48b1c74",
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"repo": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD",
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"commit": "f18a95b590b6f6dd246201eaacb62f60dd6b6902",
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"workflow_url": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11758555274",
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"commit": "da31a93c483ec2a4e3d4100a2b7191a5074a3229",
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"workflow_url": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11765791446",
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"sort_id": 1730988218526,
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"openlane_version": "OpenLane2 2.1.9",
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"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_snn_with_delays_paolaunisa/docs/info.md

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You can also include images in this folder and reference them in the markdown. Each image must be less than
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512 kb in size, and the combined size of all images must be less than 1 MB.
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-->
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## Overview
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<img src="https://github.com/user-attachments/assets/2a59dda5-e970-48e8-8068-39cb6dc95023" width="900" align="center">
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## How it works
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This project implements 16 programmable digital LIF neurons with programmable delays and a total of 128 synapsis. The neurons are arranged in 2 layers (8 inputs + FC (8 neurons) + FC (8 neurons) ). Spikes_in directly maps to the inputs of the first layer neurons. When an input spike is received, it is first multiplied by an 2 bit weight, programmable from an SPI interface, 1 per input neuron. This 8 bit value is then added to the membrane potential of the respective neuron. When the first layer neurons activate, its pulse is routed to each of the 8 neurons in the next layer. There are 128 (8x8+8x8) programmable weights describing the connectivity between the input spikes and the first layer (64 weights=8x8), the first and second layers (64 weights=8x8). Output spikes from the 2nd layer drive spikes_out.
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This project implements 18 programmable digital LIF neurons with programmable delays and a total of 144 synapsis.
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The neurons are arranged in 3 layers (8 inputs + FC (8 neurons) + FC (8 neurons) + FC (2 neurons) +2 outputs). Spikes_in directly maps to the inputs of the first layer neurons. When an input spike is received, it is first multiplied by an 2-bit weight, programmable from an SPI interface, 1 per input neuron. This value is then added to the membrane potential of the respective neuron. When the first layer neurons activate, its pulse is routed to each of the 8 neurons in the next layer. There are 144 (8x8+8x8+8x2) programmable weights describing the connectivity between the input spikes and the first layer (64 weights=8x8), the first and second layers (64 weights=8x8), and the second and third layers (16 weights=8x2).
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Through a configurable selection signal via SPI, it is possible to read any of the membrane potentials from any neuron in any layer, or the output spikes from any layer.
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## How to test
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After reset, program the neuron threshold, leak rate, and refractory period. Additionally program the first and second layer weights and delays. Once programmed activate spikes_in to represent input data, track spikes_out synchronously.
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After reset, program the neuron threshold, decay rate, and refractory period. Additionally program the first, second, and third layer weights and delays. Once programmed activate spikes_in to represent input data, track spikes_out synchronously.
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### Memory Map Overview
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Each parameter (decay, refractory period, membrane potential threshold, weights, and delays) and each configuration signal ( value for the configurable clock divider and output select signal) is accessible via SPI in specific byte addresses. The memory is organized as follows:
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| Parameter | Bit Range / Byte | Address (Hex) | Address (Decimal) | Description |
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|---------------------|--------------------------|---------------|-------------------|-----------------------------------------------------|
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| `decay` | 5:0 bits in 2nd byte | 0x00 | 0 | Decay configuration parameter |
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| `refractory_period` | 5:0 bits in 3rd byte | 0x01 | 1 | Refractory period parameter |
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| `threshold` | 5:0 bits in 4th byte | 0x02 | 2 | Membrane potential threshold |
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| `div_value` | 5th byte | 0x03 | 3 | Division value for clock divider |
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| `weights` | 36 bytes (5th to 40th) | 0x04 - 0x27 | 4 - 39 | Synaptic weights |
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| `delays` | 72 bytes (41st to 112th) | 0x28 - 0x6F | 40 - 111 | Synaptic delay |
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| `output_config` | 8 bits in 113th byte | 0x70 | 112 | Output select signal |
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### Simulations
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## External hardware
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projects/tt_um_snn_with_delays_paolaunisa/info.yaml

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- "spi_slave.v"
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- "spiking_network_top.v"
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- "synchronizer.v"
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- "TwoLayerNetwork_debug.v"
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- "ThreeLayerNetwork_debug.v"
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- "reset_manager.v"
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# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.

projects/tt_um_snn_with_delays_paolaunisa/stats/metrics.csv

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design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79989
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design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
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design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000109611
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design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000976546
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design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000110045
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design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000976546
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design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000953447
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design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000109158
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design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000953447
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ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
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ir__drop__avg,0.000010799999999999999934796081346721763338791788555681705474853515625
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ir__drop__worst,0.000110000000000000003916138247017642015634919516742229461669921875
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