feat: update project tt_um_snn_with_delays_paolaunisa from PaolaUniSa…

…/tt09_chatGPT_SNN_LD

Commit: da31a93c483ec2a4e3d4100a2b7191a5074a3229
Workflow: https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11765791446

projects/tt_um_snn_with_delays_paolaunisa/commit_id.json

@@ -1,8 +1,8 @@
 {
   "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD",
-  "commit": "f18a95b590b6f6dd246201eaacb62f60dd6b6902",
-  "workflow_url": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11758555274",
+  "commit": "da31a93c483ec2a4e3d4100a2b7191a5074a3229",
+  "workflow_url": "https://github.com/PaolaUniSa/tt09_chatGPT_SNN_LD/actions/runs/11765791446",
   "sort_id": 1730988218526,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_snn_with_delays_paolaunisa/docs/info.md

@@ -6,14 +6,41 @@ sections.
 You can also include images in this folder and reference them in the markdown. Each image must be less than
 512 kb in size, and the combined size of all images must be less than 1 MB.
 -->
+## Overview
+
+<img src="https://github.com/user-attachments/assets/2a59dda5-e970-48e8-8068-39cb6dc95023" width="900" align="center">
+
 
 ## How it works
 
-This project implements 16 programmable digital LIF neurons with programmable delays and a total of 128 synapsis. The neurons are arranged in 2 layers (8 inputs + FC (8 neurons) + FC (8 neurons) ). Spikes_in directly maps to the inputs of the first layer neurons. When an input spike is received, it is first multiplied by an 2 bit weight, programmable from an SPI interface, 1 per input neuron. This 8 bit value is then added to the membrane potential of the respective neuron. When the first layer neurons activate, its pulse is routed to each of the 8 neurons in the next layer. There are 128 (8x8+8x8) programmable weights describing the connectivity between the input spikes and the first layer (64 weights=8x8), the first and second layers (64 weights=8x8). Output spikes from the 2nd layer drive spikes_out.
+This project implements 18 programmable digital LIF neurons with programmable delays and a total of 144 synapsis.
+The neurons are arranged in 3 layers (8 inputs + FC (8 neurons) + FC (8 neurons) + FC (2 neurons) +2 outputs). Spikes_in directly maps to the inputs of the first layer neurons. When an input spike is received, it is first multiplied by an 2-bit weight, programmable from an SPI interface, 1 per input neuron. This value is then added to the membrane potential of the respective neuron. When the first layer neurons activate, its pulse is routed to each of the 8 neurons in the next layer. There are 144 (8x8+8x8+8x2) programmable weights describing the connectivity between the input spikes and the first layer (64 weights=8x8), the first and second layers (64 weights=8x8), and the second and third layers (16 weights=8x2). 
+
+Through a configurable selection signal via SPI, it is possible to read any of the membrane potentials from any neuron in any layer, or the output spikes from any layer.
+
+
 
 ## How to test
 
-After reset, program the neuron threshold, leak rate, and refractory period. Additionally program the first and second layer weights and delays. Once programmed activate spikes_in to represent input data, track spikes_out synchronously. 
+After reset, program the neuron threshold, decay rate, and refractory period. Additionally program the first, second, and third layer weights and delays. Once programmed activate spikes_in to represent input data, track spikes_out synchronously. 
+
+###  Memory Map Overview
+
+Each parameter (decay, refractory period, membrane potential threshold, weights, and delays) and each configuration signal ( value for the configurable clock divider and output select signal) is accessible via SPI in specific byte addresses. The memory is organized as follows:
+
+
+| Parameter           | Bit Range / Byte         | Address (Hex) | Address (Decimal) | Description                                         |
+|---------------------|--------------------------|---------------|-------------------|-----------------------------------------------------|
+| `decay`             | 5:0 bits in 2nd byte     | 0x00          | 0                 | Decay configuration parameter                       |
+| `refractory_period` | 5:0 bits in 3rd byte     | 0x01          | 1                 | Refractory period parameter                         |
+| `threshold`         | 5:0 bits in 4th byte     | 0x02          | 2                 | Membrane potential threshold                        |
+| `div_value`         | 5th byte                 | 0x03          | 3                 | Division value for clock divider                    |
+| `weights`           | 36 bytes (5th to 40th)   | 0x04 - 0x27   | 4 - 39            | Synaptic weights                                    |
+| `delays`            | 72 bytes (41st to 112th) | 0x28 - 0x6F   | 40 - 111          | Synaptic delay                                      |
+| `output_config`     | 8 bits in 113th byte     | 0x70          | 112               | Output select signal                                |
+
+###  Simulations
+
 
 ## External hardware
 

projects/tt_um_snn_with_delays_paolaunisa/info.yaml

@@ -34,7 +34,7 @@ project:
     - "spi_slave.v"
     - "spiking_network_top.v"
     - "synchronizer.v"
-    - "TwoLayerNetwork_debug.v"
+    - "ThreeLayerNetwork_debug.v"
     - "reset_manager.v"
 
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.

projects/tt_um_snn_with_delays_paolaunisa/stats/metrics.csv

@@ -274,9 +274,9 @@ timing__unannotated_net_filtered__count,0
 design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79989
 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.79999
 design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.000109611
-design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000976546
-design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000110045
-design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000976546
+design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000953447
+design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,0.0000109158
+design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000953447
 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
 ir__drop__avg,0.000010799999999999999934796081346721763338791788555681705474853515625
 ir__drop__worst,0.000110000000000000003916138247017642015634919516742229461669921875