feat: update project tt_um_alf19185_ALU from alf19185/TT09-ALU

Commit: abde9d435b8aeaeff40794bfd8309368b26d1dae
Workflow: https://github.com/alf19185/TT09-ALU/actions/runs/11767049416

projects/tt_um_alf19185_ALU/commit_id.json

@@ -1,8 +1,8 @@
 {
-  "app": "Tiny Tapeout tt09 b176ed7c",
+  "app": "Tiny Tapeout tt09 a48b1c74",
   "repo": "https://github.com/alf19185/TT09-ALU",
-  "commit": "d122a56b5bc7c024a8f6a8c9f5ae8025c10ec137",
-  "workflow_url": "https://github.com/alf19185/TT09-ALU/actions/runs/11648943287",
+  "commit": "abde9d435b8aeaeff40794bfd8309368b26d1dae",
+  "workflow_url": "https://github.com/alf19185/TT09-ALU/actions/runs/11767049416",
   "sort_id": 1730613446440,
   "openlane_version": "OpenLane2 2.1.9",
   "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"

projects/tt_um_alf19185_ALU/docs/info.md

@@ -1,18 +1,22 @@
-<!---
 
-This file is used to generate your project datasheet. Please fill in the information below and delete any unused
-sections.
+## How it works?
 
-You can also include images in this folder and reference them in the markdown. Each image must be less than
-512 kb in size, and the combined size of all images must be less than 1 MB.
--->
+The 4-bit ALU (Arithmetic Logic Unit) is designed to perform a range of arithmetic and logical operations on two 4-bit inputs, A and B. The operation is determined by a 3-bit control signal, Opcode, which specifies the function to execute, such as addition, subtraction, multiplication, division, and bitwise operations (AND, OR, NOT, XOR).
 
-## How it works
+When an arithmetic operation like addition is selected, the ALU outputs an 8-bit result, ALU_Result, to accommodate larger sums or products, and it sets a Carry flag if there’s an overflow. For logical operations like AND or OR, the ALU applies the operation bit-by-bit between A and B. The Zero flag is activated when the result is zero, providing a useful condition for further logic. This flexibility allows the ALU to handle various computational tasks, making it a crucial part of digital systems that require multi-functional data processing.
 
-The 4 bit ALU (Arithmetic Logic Unit) has 2 inputs of 4 bits for each operand, 1 input of 3 bits to select the operational mode, 1 output of 8 bits with the result of the selected operation and 2 outputs of 1 bit each to identify an overflow or zero.
+## How to test?
 
-To test the design, the opcode was configured for addition (000), substraction (001), multiplication (010), division (011) and for zero (100).
+To test the design, the operation codes are: 
 
+- Addition (000)
+- Substraction (001)
+- Multiplication (010) 
+- Division (011) 
+- Logic AND (100) 
+- Logic OR (101) 
+- Logic NOT (110) 
+- Logic XOR (111) 
 
 
 

projects/tt_um_alf19185_ALU/info.yaml

@@ -3,7 +3,7 @@ project:
   title:        "4 bit ALU "      # Project title
   author:       "Gabriela Alfaro"      # Your name
   discord:      "N/A"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
-  description:  "A simple design of an Arithmetic Logic Unit capable of basic operations: addition, substraction , multiplication and division."      # One line description of what your project does
+  description:  "A simple design of an Arithmetic Logic Unit capable of basic operations: addition, substraction , multiplication, division and some logic operations."      # One line description of what your project does
   language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
@@ -36,14 +36,14 @@ pinout:
   uo[1]: "ALU_Out[1]"
   uo[2]: "ALU_Out[2]"
   uo[3]: "ALU_Out[3]"
-  uo[4]: "ZeroFlag"
-  uo[5]: "CarryOut"
-  uo[6]: ""
-  uo[7]: ""
+  uo[4]: "ALU_Out[4]"
+  uo[5]: "ALU_Out[5]"
+  uo[6]: "ALU_Out[6]"
+  uo[7]: "ALU_Out[7]"
 
   # Bidirectional pins
-  uio[0]: ""
-  uio[1]: ""
+  uio[0]: "ZeroFlag"
+  uio[1]: "CarryOut"
   uio[2]: ""
   uio[3]: ""
   uio[4]: ""

projects/tt_um_alf19185_ALU/stats/metrics.csv

@@ -92,8 +92,8 @@ design__instance__count__macros,0
 design__instance__area__macros,0
 design__instance__utilization,0.10044
 design__instance__utilization__stdcell,0.10044
-design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count__net:VPWR,0
+design__power_grid_violation__count__net:VGND,0
 design__power_grid_violation__count,0
 timing__drv__floating__nets,0
 timing__drv__floating__pins,0