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feat: update project tt_um_wokwi_414122607025630209 from lsk567/tinyt…
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…apeout-uart-tx

Commit: 2a446e40667d69481ec355d8e339330fb1cbaa3f
Workflow: https://github.com/lsk567/tinytapeout-uart-tx/actions/runs/11766852236
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@TinyTapeoutBot @urish
TinyTapeoutBot authored and urish committed Nov 10, 2024
1 parent 189495b commit 2eef3f7
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Showing 9 changed files with 7,425 additions and 4,072 deletions.
4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_414122607025630209/commit_id.json
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{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/lsk567/tinytapeout-uart-tx",
"commit": "7558cd83a2c4dda34308b19e73e9e65be4bbbf0c",
"workflow_url": "https://github.com/lsk567/tinytapeout-uart-tx/actions/runs/11761074681",
"commit": "2a446e40667d69481ec355d8e339330fb1cbaa3f",
"workflow_url": "https://github.com/lsk567/tinytapeout-uart-tx/actions/runs/11766852236",
"sort_id": 1731202880374,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_414122607025630209/docs/info.md
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Expand Up @@ -9,11 +9,11 @@ You can also include images in this folder and reference them in the markdown. E

## How it works

This design is a UART TX that sends ``TINY''.
This design is a UART TX that sends ``SHAOKAI''.

## How to test

Connect it to your serial receiver and see if ``TINY'' gets printed.
Connect it to your serial receiver and see if ``SHAOKAI'' gets printed.

## External hardware

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14 changes: 7 additions & 7 deletions projects/tt_um_wokwi_414122607025630209/info.yaml
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# Tiny Tapeout project information (Wokwi project)
project:
wokwi_id: 414122607025630209 # Set this to the ID of your Wokwi project (the number from the project's URL)
title: "UART TX" # Project title
author: "Anonymous" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "A UART transmitter" # One line description of what your project does
language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)
wokwi_id: 414122607025630209 # Set this to the ID of your Wokwi project (the number from the project's URL)
title: "UART TX" # Project title
author: "Shaokai Lin" # Your name
discord: "Shaokai" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "A UART transmitter modified from the one from the TinyTapeout website" # One line description of what your project does
language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)

# How many tiles your design occupies? A single tile is about 167x108 uM.
tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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182 changes: 92 additions & 90 deletions projects/tt_um_wokwi_414122607025630209/stats/metrics.csv
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42 changes: 21 additions & 21 deletions projects/tt_um_wokwi_414122607025630209/stats/synthesis-stats.txt
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Expand Up @@ -31,43 +31,43 @@

=== tt_um_wokwi_414122607025630209 ===

Number of wires: 325
Number of wire bits: 360
Number of public wires: 219
Number of public wire bits: 254
Number of wires: 514
Number of wire bits: 549
Number of public wires: 345
Number of public wire bits: 380
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 341
dff_cell 105
mux_cell 106
Number of cells: 530
dff_cell 168
mux_cell 169
sky130_fd_sc_hd__buf_2 3
sky130_fd_sc_hd__conb_1 127
sky130_fd_sc_hd__conb_1 190

Area for cell type \dff_cell is unknown!
Area for cell type \mux_cell is unknown!

Chip area for module '\tt_um_wokwi_414122607025630209': 491.721600
Chip area for module '\tt_um_wokwi_414122607025630209': 728.198400

=== design hierarchy ===

tt_um_wokwi_414122607025630209 1
dff_cell 105
mux_cell 106
dff_cell 168
mux_cell 169

Number of wires: 1169
Number of wire bits: 1204
Number of public wires: 1063
Number of public wire bits: 1098
Number of wires: 1862
Number of wire bits: 1897
Number of public wires: 1693
Number of public wire bits: 1728
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 446
Number of cells: 698
sky130_fd_sc_hd__buf_2 3
sky130_fd_sc_hd__conb_1 127
sky130_fd_sc_hd__dfxtp_2 105
sky130_fd_sc_hd__inv_2 105
sky130_fd_sc_hd__mux2_1 106
sky130_fd_sc_hd__conb_1 190
sky130_fd_sc_hd__dfxtp_2 168
sky130_fd_sc_hd__inv_2 168
sky130_fd_sc_hd__mux2_1 169

Chip area for top module '\tt_um_wokwi_414122607025630209': 4312.886400
Chip area for top module '\tt_um_wokwi_414122607025630209': 6835.305600

Binary file modified projects/tt_um_wokwi_414122607025630209/tt_um_wokwi_414122607025630209.gds
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102 changes: 51 additions & 51 deletions projects/tt_um_wokwi_414122607025630209/tt_um_wokwi_414122607025630209.lef
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Expand Up @@ -405,59 +405,59 @@ MACRO tt_um_wokwi_414122607025630209
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END
END tt_um_wokwi_414122607025630209
END LIBRARY
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