diff --git a/projects/tt_um_wokwi_414121715329142785/commit_id.json b/projects/tt_um_wokwi_414121715329142785/commit_id.json index 94984cf3..fc966527 100644 --- a/projects/tt_um_wokwi_414121715329142785/commit_id.json +++ b/projects/tt_um_wokwi_414121715329142785/commit_id.json @@ -1,8 +1,8 @@ { "app": "Tiny Tapeout tt09 a48b1c74", "repo": "https://github.com/schoeberl/tt09-sigma-delta", - "commit": "c28765e4da9c2fb936e10d67680ac6fb2cc782b4", - "workflow_url": "https://github.com/schoeberl/tt09-sigma-delta/actions/runs/11760976941", + "commit": "8d45b556dddb8096c0340936e6a9faf639c04ead", + "workflow_url": "https://github.com/schoeberl/tt09-sigma-delta/actions/runs/11764051619", "sort_id": 1731201795801, "openlane_version": "OpenLane2 2.1.9", "pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a" diff --git a/projects/tt_um_wokwi_414121715329142785/docs/info.md b/projects/tt_um_wokwi_414121715329142785/docs/info.md index e4fe5eca..eba934c3 100644 --- a/projects/tt_um_wokwi_414121715329142785/docs/info.md +++ b/projects/tt_um_wokwi_414121715329142785/docs/info.md @@ -1,27 +1,25 @@ - +Provide an analog signal at Vin (e.g., some music) and listen to the output at Vout (using an amplifier). +The circuit will probably add some noise, as it is very crude. But it went from the analog domain to digital +and then back. -## How it works +Future work should be to use that sigma-delta coded signal to do some fun audio processing. -Converting an analog signal to a pulse duration modulated digital signal +Anyone knowing how to do DSP in the sigma-delta domain? ## How to test -Connect an analog source to your design. +Connect an analog source to your design and listen to the music (output). ## External hardware +This is a sigma-delta AD converter and a DA converter. + +The input is mixed with the feedback delay/inversion and uses the threshold of the DFF input as a comparator, serving as a single bit ADC. + +The R and C values depend on the input signal and can be discussed and should be explored. + ``` - sigma delta AD converter - - without external comparator: - input threshold of the DFF input is used as comparator - (not very exact but only 3 external components) 100k @@ -29,13 +27,13 @@ Connect an analog source to your design. OUT0 o--|___|--+ | 100k | - ___ | - Vin o--|___|--o----------o IN0 - | - --- - --- 100n - | - | - --- - - + ___ | ____ + Vin o--|___|--o----------o IN0 OUT1 o----|____|---o--------o Vout + | | + --- --- + --- 100n --- + | | + | | + --- --- + - - ``` diff --git a/projects/tt_um_wokwi_414121715329142785/info.yaml b/projects/tt_um_wokwi_414121715329142785/info.yaml index e0944e15..3815221d 100644 --- a/projects/tt_um_wokwi_414121715329142785/info.yaml +++ b/projects/tt_um_wokwi_414121715329142785/info.yaml @@ -1,10 +1,10 @@ # Tiny Tapeout project information (Wokwi project) project: wokwi_id: 414121715329142785 # Set this to the ID of your Wokwi project (the number from the project's URL) - title: "Sigma Delta ADC" # Project title + title: "Sigma-Delta ADC" # Project title author: "Martin Schoeberl" # Your name - discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) - description: "Analog to digital converter" # One line description of what your project does + discord: "maybe I do not want to make this public ;-)" # Your discord username, for communication and automatically assigning you a Tapeout role (optional) + description: "Analog to digital converter - and back" # One-line description of what your project does language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable) @@ -26,7 +26,7 @@ pinout: # Outputs uo[0]: "OUT0" - uo[1]: "" + uo[1]: "OUT1" uo[2]: "" uo[3]: "" uo[4]: "" diff --git a/projects/tt_um_wokwi_414121715329142785/stats/metrics.csv b/projects/tt_um_wokwi_414121715329142785/stats/metrics.csv index 6c30341e..cdedc87c 100644 --- a/projects/tt_um_wokwi_414121715329142785/stats/metrics.csv +++ b/projects/tt_um_wokwi_414121715329142785/stats/metrics.csv @@ -3,21 +3,21 @@ design__lint_error__count,0 design__lint_timing_construct__count,0 design__lint_warning__count,0 design__inferred_latch__count,0 -design__instance__count,259 -design__instance__area,520.499 +design__instance__count,263 +design__instance__area,560.538 design__instance_unmapped__count,0 synthesis__check_error__count,0 design__max_slew_violation__count__corner:nom_tt_025C_1v80,0 design__max_fanout_violation__count__corner:nom_tt_025C_1v80,0 design__max_cap_violation__count__corner:nom_tt_025C_1v80,0 -power__internal__total,0.000034739598049782217 -power__switching__total,0.000006022106845193775 -power__leakage__total,1.5976063805211993E-9 -power__total,0.000040763301512924954 -clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.00003569367125118475 -clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.00003569367125118475 -timing__hold__ws__corner:nom_tt_025C_1v80,0.6328084901865719 -timing__setup__ws__corner:nom_tt_025C_1v80,11.511618650814754 +power__internal__total,0.0000398870870412793 +power__switching__total,0.000007369175818894291 +power__leakage__total,1.6589433160518752E-9 +power__total,0.00004725792314275168 +clock__skew__worst_hold__corner:nom_tt_025C_1v80,-0.0005482003894884525 +clock__skew__worst_setup__corner:nom_tt_025C_1v80,-0.0005482003894884525 +timing__hold__ws__corner:nom_tt_025C_1v80,0.6326933600556621 +timing__setup__ws__corner:nom_tt_025C_1v80,11.515686508092028 timing__hold__tns__corner:nom_tt_025C_1v80,0.0 timing__setup__tns__corner:nom_tt_025C_1v80,0.0 timing__hold__wns__corner:nom_tt_025C_1v80,0 @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0 design__max_slew_violation__count__corner:nom_ss_100C_1v60,0 design__max_fanout_violation__count__corner:nom_ss_100C_1v60,0 design__max_cap_violation__count__corner:nom_ss_100C_1v60,0 -clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.00003569367125118475 -clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.00003569367125118475 -timing__hold__ws__corner:nom_ss_100C_1v60,1.518397672794839 -timing__setup__ws__corner:nom_ss_100C_1v60,11.343490023924197 +clock__skew__worst_hold__corner:nom_ss_100C_1v60,-0.001081801345790184 +clock__skew__worst_setup__corner:nom_ss_100C_1v60,-0.001081801345790184 +timing__hold__ws__corner:nom_ss_100C_1v60,1.518006985301424 +timing__setup__ws__corner:nom_ss_100C_1v60,11.350162020401681 timing__hold__tns__corner:nom_ss_100C_1v60,0.0 timing__setup__tns__corner:nom_ss_100C_1v60,0.0 timing__hold__wns__corner:nom_ss_100C_1v60,0 @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0 design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,0 design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0 -clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.00003599898259159146 -clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.00003599898259159146 -timing__hold__ws__corner:nom_ff_n40C_1v95,0.33533357595407853 -timing__setup__ws__corner:nom_ff_n40C_1v95,11.582127584835197 +clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-0.0004039824145108818 +clock__skew__worst_setup__corner:nom_ff_n40C_1v95,-0.0004039824145108818 +timing__hold__ws__corner:nom_ff_n40C_1v95,0.33521322777480544 +timing__setup__ws__corner:nom_ff_n40C_1v95,11.585031040171312 timing__hold__tns__corner:nom_ff_n40C_1v95,0.0 timing__setup__tns__corner:nom_ff_n40C_1v95,0.0 timing__hold__wns__corner:nom_ff_n40C_1v95,0 @@ -65,10 +65,10 @@ timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count,0 design__max_fanout_violation__count,0 design__max_cap_violation__count,0 -clock__skew__worst_hold,-0.000028255176775821208 -clock__skew__worst_setup,-0.00004715672430463677 -timing__hold__ws,0.33532244596794186 -timing__setup__ws,11.341274018704372 +clock__skew__worst_hold,-0.0003437528137215576 +clock__skew__worst_setup,-0.0012674306407574653 +timing__hold__ws,0.3350317340607219 +timing__setup__ws,11.346405025580093 timing__hold__tns,0.0 timing__setup__tns,0.0 timing__hold__wns,0 @@ -86,12 +86,12 @@ flow__errors__count,0 design__io,45 design__die__area,17954.7 design__core__area,16493.3 -design__instance__count__stdcell,259 -design__instance__area__stdcell,520.499 +design__instance__count__stdcell,263 +design__instance__area__stdcell,560.538 design__instance__count__macros,0 design__instance__area__macros,0 -design__instance__utilization,0.0315582 -design__instance__utilization__stdcell,0.0315582 +design__instance__utilization,0.0339857 +design__instance__utilization__stdcell,0.0339857 design__power_grid_violation__count__net:VGND,0 design__power_grid_violation__count__net:VPWR,0 design__power_grid_violation__count,0 @@ -100,40 +100,40 @@ timing__drv__floating__pins,0 design__instance__displacement__total,0 design__instance__displacement__mean,0 design__instance__displacement__max,0 -route__wirelength__estimated,466.651 +route__wirelength__estimated,518.594 design__violations,0 design__instance__count__setup_buffer,0 -design__instance__count__hold_buffer,1 +design__instance__count__hold_buffer,2 antenna__violating__nets,0 antenna__violating__pins,0 route__antenna_violation__count,0 -route__net,53 +route__net,56 route__net__special,2 -route__drc_errors__iter:1,54 -route__wirelength__iter:1,442 +route__drc_errors__iter:1,45 +route__wirelength__iter:1,461 route__drc_errors__iter:2,0 -route__wirelength__iter:2,415 +route__wirelength__iter:2,439 route__drc_errors,0 -route__wirelength,415 -route__vias,155 -route__vias__singlecut,155 +route__wirelength,439 +route__vias,172 +route__vias__singlecut,172 route__vias__multicut,0 design__disconnected_pin__count,13 design__critical_disconnected_pin__count,0 -route__wirelength__max,67.39 -timing__unannotated_net__count__corner:nom_tt_025C_1v80,41 +route__wirelength__max,52.12 +timing__unannotated_net__count__corner:nom_tt_025C_1v80,44 timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0 -timing__unannotated_net__count__corner:nom_ss_100C_1v60,41 +timing__unannotated_net__count__corner:nom_ss_100C_1v60,44 timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0 -timing__unannotated_net__count__corner:nom_ff_n40C_1v95,41 +timing__unannotated_net__count__corner:nom_ff_n40C_1v95,44 timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0 design__max_slew_violation__count__corner:min_tt_025C_1v80,0 design__max_fanout_violation__count__corner:min_tt_025C_1v80,0 design__max_cap_violation__count__corner:min_tt_025C_1v80,0 -clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.000028282932352221816 -clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.000028282932352221816 -timing__hold__ws__corner:min_tt_025C_1v80,0.6328160952145057 -timing__setup__ws__corner:min_tt_025C_1v80,11.517147561633756 +clock__skew__worst_hold__corner:min_tt_025C_1v80,-0.0004883316111923363 +clock__skew__worst_setup__corner:min_tt_025C_1v80,-0.0004883316111923363 +timing__hold__ws__corner:min_tt_025C_1v80,0.6327533121006874 +timing__setup__ws__corner:min_tt_025C_1v80,11.520379642994454 timing__hold__tns__corner:min_tt_025C_1v80,0.0 timing__setup__tns__corner:min_tt_025C_1v80,0.0 timing__hold__wns__corner:min_tt_025C_1v80,0 @@ -144,15 +144,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0 timing__setup_vio__count__corner:min_tt_025C_1v80,0 timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0 -timing__unannotated_net__count__corner:min_tt_025C_1v80,41 +timing__unannotated_net__count__corner:min_tt_025C_1v80,44 timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0 design__max_slew_violation__count__corner:min_ss_100C_1v60,0 design__max_fanout_violation__count__corner:min_ss_100C_1v60,0 design__max_cap_violation__count__corner:min_ss_100C_1v60,0 -clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.000028255176775821208 -clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.000028255176775821208 -timing__hold__ws__corner:min_ss_100C_1v60,1.5184052223116198 -timing__setup__ws__corner:min_ss_100C_1v60,11.352446415361756 +clock__skew__worst_hold__corner:min_ss_100C_1v60,-0.0010220158342232697 +clock__skew__worst_setup__corner:min_ss_100C_1v60,-0.0010220158342232697 +timing__hold__ws__corner:min_ss_100C_1v60,1.5180668263241437 +timing__setup__ws__corner:min_ss_100C_1v60,11.35769732632753 timing__hold__tns__corner:min_ss_100C_1v60,0.0 timing__setup__tns__corner:min_ss_100C_1v60,0.0 timing__hold__wns__corner:min_ss_100C_1v60,0 @@ -163,15 +163,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0 timing__setup_vio__count__corner:min_ss_100C_1v60,0 timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0 -timing__unannotated_net__count__corner:min_ss_100C_1v60,41 +timing__unannotated_net__count__corner:min_ss_100C_1v60,44 timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0 design__max_slew_violation__count__corner:min_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:min_ff_n40C_1v95,0 design__max_cap_violation__count__corner:min_ff_n40C_1v95,0 -clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.000028491099175226393 -clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.000028491099175226393 -timing__hold__ws__corner:min_ff_n40C_1v95,0.3353410699597067 -timing__setup__ws__corner:min_ff_n40C_1v95,11.586090637055982 +clock__skew__worst_hold__corner:min_ff_n40C_1v95,-0.0003437528137215576 +clock__skew__worst_setup__corner:min_ff_n40C_1v95,-0.0003437528137215576 +timing__hold__ws__corner:min_ff_n40C_1v95,0.33527348513117117 +timing__setup__ws__corner:min_ff_n40C_1v95,11.588402565547847 timing__hold__tns__corner:min_ff_n40C_1v95,0.0 timing__setup__tns__corner:min_ff_n40C_1v95,0.0 timing__hold__wns__corner:min_ff_n40C_1v95,0 @@ -182,15 +182,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_vio__count__corner:min_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:min_ff_n40C_1v95,41 +timing__unannotated_net__count__corner:min_ff_n40C_1v95,44 timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0 design__max_slew_violation__count__corner:max_tt_025C_1v80,0 design__max_fanout_violation__count__corner:max_tt_025C_1v80,0 design__max_cap_violation__count__corner:max_tt_025C_1v80,0 -clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.000046851412964230055 -clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.000046851412964230055 -timing__hold__ws__corner:max_tt_025C_1v80,0.6327972214225532 -timing__setup__ws__corner:max_tt_025C_1v80,11.510135392811906 +clock__skew__worst_hold__corner:max_tt_025C_1v80,-0.0007283340803284128 +clock__skew__worst_setup__corner:max_tt_025C_1v80,-0.0007283340803284128 +timing__hold__ws__corner:max_tt_025C_1v80,0.6325129488090582 +timing__setup__ws__corner:max_tt_025C_1v80,11.51321737201543 timing__hold__tns__corner:max_tt_025C_1v80,0.0 timing__setup__tns__corner:max_tt_025C_1v80,0.0 timing__hold__wns__corner:max_tt_025C_1v80,0 @@ -201,15 +201,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0 timing__setup_vio__count__corner:max_tt_025C_1v80,0 timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0 -timing__unannotated_net__count__corner:max_tt_025C_1v80,41 +timing__unannotated_net__count__corner:max_tt_025C_1v80,44 timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0 design__max_slew_violation__count__corner:max_ss_100C_1v60,0 design__max_fanout_violation__count__corner:max_ss_100C_1v60,0 design__max_cap_violation__count__corner:max_ss_100C_1v60,0 -clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.000046629368353025176 -clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.000046629368353025176 -timing__hold__ws__corner:max_ss_100C_1v60,1.518386459541973 -timing__setup__ws__corner:max_ss_100C_1v60,11.341274018704372 +clock__skew__worst_hold__corner:max_ss_100C_1v60,-0.0012674306407574653 +clock__skew__worst_setup__corner:max_ss_100C_1v60,-0.0012674306407574653 +timing__hold__ws__corner:max_ss_100C_1v60,1.517821244984151 +timing__setup__ws__corner:max_ss_100C_1v60,11.346405025580093 timing__hold__tns__corner:max_ss_100C_1v60,0.0 timing__setup__tns__corner:max_ss_100C_1v60,0.0 timing__hold__wns__corner:max_ss_100C_1v60,0 @@ -220,15 +220,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0 timing__setup_vio__count__corner:max_ss_100C_1v60,0 timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0 -timing__unannotated_net__count__corner:max_ss_100C_1v60,41 +timing__unannotated_net__count__corner:max_ss_100C_1v60,44 timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0 design__max_slew_violation__count__corner:max_ff_n40C_1v95,0 design__max_fanout_violation__count__corner:max_ff_n40C_1v95,0 design__max_cap_violation__count__corner:max_ff_n40C_1v95,0 -clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.00004715672430463677 -clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.00004715672430463677 -timing__hold__ws__corner:max_ff_n40C_1v95,0.33532244596794186 -timing__setup__ws__corner:max_ff_n40C_1v95,11.5809267675778 +clock__skew__worst_hold__corner:max_ff_n40C_1v95,-0.0005855038841708726 +clock__skew__worst_setup__corner:max_ff_n40C_1v95,-0.0005855038841708726 +timing__hold__ws__corner:max_ff_n40C_1v95,0.3350317340607219 +timing__setup__ws__corner:max_ff_n40C_1v95,11.583163200901856 timing__hold__tns__corner:max_ff_n40C_1v95,0.0 timing__setup__tns__corner:max_ff_n40C_1v95,0.0 timing__hold__wns__corner:max_ff_n40C_1v95,0 @@ -239,19 +239,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_vio__count__corner:max_ff_n40C_1v95,0 timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count__corner:max_ff_n40C_1v95,41 +timing__unannotated_net__count__corner:max_ff_n40C_1v95,44 timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0 -timing__unannotated_net__count,41 +timing__unannotated_net__count,44 timing__unannotated_net_filtered__count,0 -design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996 +design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79997 design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8 -design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000420736 -design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000542823 -design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,6.63304E-7 -design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000542823 +design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000337614 +design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000490428 +design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,7.8008E-7 +design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000490428 ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125 -ir__drop__avg,7.06999999999999964830541508697958619222845300100743770599365234375E-7 -ir__drop__worst,0.0000421000000000000001065987575987747959516127593815326690673828125 +ir__drop__avg,7.490000000000000497508392989509662385216870461590588092803955078125E-7 +ir__drop__worst,0.0000338000000000000016468597319185818150799605064094066619873046875 magic__drc_error__count,0 magic__illegal_overlap__count,0 design__lvs_device_difference__count,0 diff --git a/projects/tt_um_wokwi_414121715329142785/stats/synthesis-stats.txt b/projects/tt_um_wokwi_414121715329142785/stats/synthesis-stats.txt index 653c350a..5a6f8c4e 100644 --- a/projects/tt_um_wokwi_414121715329142785/stats/synthesis-stats.txt +++ b/projects/tt_um_wokwi_414121715329142785/stats/synthesis-stats.txt @@ -31,42 +31,42 @@ === tt_um_wokwi_414121715329142785 === - Number of wires: 11 - Number of wire bits: 46 - Number of public wires: 11 - Number of public wire bits: 46 + Number of wires: 12 + Number of wire bits: 47 + Number of public wires: 12 + Number of public wire bits: 47 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 27 - dff_cell 2 + Number of cells: 28 + dff_cell 3 not_cell 1 - sky130_fd_sc_hd__buf_2 5 - sky130_fd_sc_hd__conb_1 19 + sky130_fd_sc_hd__buf_2 6 + sky130_fd_sc_hd__conb_1 18 Area for cell type \dff_cell is unknown! Area for cell type \not_cell is unknown! - Chip area for module '\tt_um_wokwi_414121715329142785': 96.342400 + Chip area for module '\tt_um_wokwi_414121715329142785': 97.593600 === design hierarchy === tt_um_wokwi_414121715329142785 1 - dff_cell 2 + dff_cell 3 not_cell 1 - Number of wires: 21 - Number of wire bits: 56 - Number of public wires: 21 - Number of public wire bits: 56 + Number of wires: 26 + Number of wire bits: 61 + Number of public wires: 26 + Number of public wire bits: 61 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 - Number of cells: 29 - sky130_fd_sc_hd__buf_2 5 - sky130_fd_sc_hd__conb_1 19 - sky130_fd_sc_hd__dfxtp_2 2 - sky130_fd_sc_hd__inv_2 3 + Number of cells: 31 + sky130_fd_sc_hd__buf_2 6 + sky130_fd_sc_hd__conb_1 18 + sky130_fd_sc_hd__dfxtp_2 3 + sky130_fd_sc_hd__inv_2 4 - Chip area for top module '\tt_um_wokwi_414121715329142785': 150.144000 + Chip area for top module '\tt_um_wokwi_414121715329142785': 176.419200 diff --git a/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.gds b/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.gds index 30dd80e1..5a841caa 100644 Binary files a/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.gds and b/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.gds differ diff --git a/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.lef b/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.lef index 7f2749b2..86a58677 100644 --- a/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.lef +++ b/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.lef @@ -336,7 +336,7 @@ MACRO tt_um_wokwi_414121715329142785 PIN uo_out[0] DIRECTION OUTPUT ; USE SIGNAL ; - ANTENNADIFFAREA 0.795200 ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 94.150 110.520 94.450 111.520 ; @@ -345,6 +345,7 @@ MACRO tt_um_wokwi_414121715329142785 PIN uo_out[1] DIRECTION OUTPUT ; USE SIGNAL ; + ANTENNADIFFAREA 0.445500 ; PORT LAYER met4 ; RECT 91.390 110.520 91.690 111.520 ; @@ -408,11 +409,11 @@ MACRO tt_um_wokwi_414121715329142785 LAYER li1 ; RECT 2.760 2.635 158.240 108.885 ; LAYER met1 ; - RECT 2.760 2.480 158.240 109.040 ; + RECT 2.760 2.480 158.240 109.440 ; LAYER met2 ; - RECT 18.310 2.535 154.920 110.005 ; + RECT 18.310 2.535 143.890 110.005 ; LAYER met3 ; - RECT 18.290 2.555 145.295 109.985 ; + RECT 18.290 2.555 144.370 109.985 ; LAYER met4 ; RECT 31.370 110.120 33.030 110.520 ; RECT 34.130 110.120 35.790 110.520 ; @@ -456,13 +457,13 @@ MACRO tt_um_wokwi_414121715329142785 RECT 139.010 110.120 140.670 110.520 ; RECT 141.770 110.120 143.430 110.520 ; RECT 30.655 109.440 144.145 110.120 ; - RECT 30.655 94.015 56.750 109.440 ; - RECT 59.150 94.015 60.050 109.440 ; - RECT 62.450 94.015 95.620 109.440 ; - RECT 98.020 94.015 98.920 109.440 ; - RECT 101.320 94.015 134.490 109.440 ; - RECT 136.890 94.015 137.790 109.440 ; - RECT 140.190 94.015 144.145 109.440 ; + RECT 30.655 105.575 56.750 109.440 ; + RECT 59.150 105.575 60.050 109.440 ; + RECT 62.450 105.575 95.620 109.440 ; + RECT 98.020 105.575 98.920 109.440 ; + RECT 101.320 105.575 134.490 109.440 ; + RECT 136.890 105.575 137.790 109.440 ; + RECT 140.190 105.575 144.145 109.440 ; END END tt_um_wokwi_414121715329142785 END LIBRARY diff --git a/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.v b/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.v index 0ed004d6..3a0575b7 100644 --- a/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.v +++ b/projects/tt_um_wokwi_414121715329142785/tt_um_wokwi_414121715329142785.v @@ -19,17 +19,17 @@ module tt_um_wokwi_414121715329142785 (clk, output [7:0] uio_out; output [7:0] uo_out; - wire net11; wire net12; + wire net13; wire net7; + wire net8; wire net3; wire net4; wire net5; wire net6; - wire net8; wire net9; wire net10; - wire net13; + wire net11; wire net14; wire net15; wire net16; @@ -43,11 +43,13 @@ module tt_um_wokwi_414121715329142785 (clk, wire clknet_0_clk; wire \flop1/notq ; wire \flop2/notq ; + wire \flop3/notq ; wire net1; wire net2; wire clknet_1_0__leaf_clk; wire clknet_1_1__leaf_clk; wire net24; + wire net25; sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_3 (.VGND(VGND), .VNB(VGND), @@ -73,68 +75,63 @@ module tt_um_wokwi_414121715329142785 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net8)); + .LO(net9)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_8 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net9)); + .LO(net10)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_9 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .LO(net10)); + .LO(net11)); sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_10 (.VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - .VPWR(VPWR), - .LO(net13)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_11 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net14)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_12 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_11 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net15)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_13 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_12 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net16)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_14 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_13 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net17)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_15 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_14 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net18)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_16 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_15 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net19)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_17 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_16 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net20)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_18 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_17 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net21)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_19 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_18 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .LO(net22)); - sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_20 (.VGND(VGND), + sky130_fd_sc_hd__conb_1 tt_um_wokwi_414121715329142785_19 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), @@ -145,12 +142,18 @@ module tt_um_wokwi_414121715329142785 (clk, .VPB(VPWR), .VPWR(VPWR), .X(clknet_0_clk)); - sky130_fd_sc_hd__clkbuf_4 _19_ (.A(net7), + sky130_fd_sc_hd__buf_2 _18_ (.A(net7), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(uo_out[0])); + sky130_fd_sc_hd__buf_2 _19_ (.A(net8), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(uo_out[1])); sky130_fd_sc_hd__buf_2 _20_ (.A(ui_in[4]), .VGND(VGND), .VNB(VGND), @@ -175,33 +178,46 @@ module tt_um_wokwi_414121715329142785 (clk, .VPB(VPWR), .VPWR(VPWR), .X(uo_out[7])); - sky130_fd_sc_hd__inv_2 \flop1/_0_ (.A(net11), + sky130_fd_sc_hd__inv_2 \flop1/_0_ (.A(net12), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(\flop1/notq )); - sky130_fd_sc_hd__dfxtp_1 \flop1/_1_ (.CLK(clknet_1_1__leaf_clk), + sky130_fd_sc_hd__dfxtp_1 \flop1/_1_ (.CLK(clknet_1_0__leaf_clk), .D(net1), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Q(net11)); - sky130_fd_sc_hd__inv_2 \flop2/_0_ (.A(net12), + .Q(net12)); + sky130_fd_sc_hd__inv_2 \flop2/_0_ (.A(net13), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .Y(\flop2/notq )); - sky130_fd_sc_hd__dfxtp_1 \flop2/_1_ (.CLK(clknet_1_0__leaf_clk), + sky130_fd_sc_hd__dfxtp_1 \flop2/_1_ (.CLK(clknet_1_1__leaf_clk), .D(net24), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), - .Q(net12)); - sky130_fd_sc_hd__inv_2 \not5/_0_ (.A(net12), + .Q(net13)); + sky130_fd_sc_hd__inv_2 \flop3/_0_ (.A(net8), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Y(\flop3/notq )); + sky130_fd_sc_hd__dfxtp_1 \flop3/_1_ (.CLK(clknet_1_0__leaf_clk), + .D(net25), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .Q(net8)); + sky130_fd_sc_hd__inv_2 \not5/_0_ (.A(net13), .VGND(VGND), .VNB(VGND), .VPB(VPWR), @@ -992,12 +1008,23 @@ module tt_um_wokwi_414121715329142785 (clk, .VPB(VPWR), .VPWR(VPWR), .X(clknet_1_1__leaf_clk)); - sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(net11), + sky130_fd_sc_hd__clkbuf_4 clkload0 (.A(clknet_1_1__leaf_clk), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(net12), .VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR), .X(net24)); + sky130_fd_sc_hd__dlygate4sd3_1 hold2 (.A(net13), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR), + .X(net25)); sky130_ef_sc_hd__decap_12 FILLER_0_0_3 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), @@ -5958,11 +5985,15 @@ module tt_um_wokwi_414121715329142785 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_2 FILLER_0_34_309 (.VGND(VGND), - .VNB(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_34_309 (.VPWR(VPWR), + .VGND(VGND), .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_34_331 (.VGND(VGND), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_34_321 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_34_333 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6190,55 +6221,63 @@ module tt_um_wokwi_414121715329142785 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_197 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_36_197 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_209 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_36_203 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_221 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_36_207 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_233 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_36_215 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_36_245 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_8 FILLER_0_36_241 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_3 FILLER_0_36_249 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_36_251 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_36_253 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_253 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_36_261 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_265 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_36_273 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_277 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_36_285 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_36_289 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_36_297 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_36_312 (.VPWR(VPWR), + sky130_fd_sc_hd__decap_3 FILLER_0_36_305 (.VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); + sky130_ef_sc_hd__decap_12 FILLER_0_36_309 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_8 FILLER_0_36_324 (.VGND(VGND), - .VNB(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_36_321 (.VPWR(VPWR), + .VGND(VGND), .VPB(VPWR), - .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_36_332 (.VGND(VGND), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_36_333 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6322,59 +6361,51 @@ module tt_um_wokwi_414121715329142785 (clk, .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_193 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_205 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_217 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_37_193 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_223 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_197 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_225 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_237 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_249 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_261 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_37_221 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_273 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_2 FILLER_0_37_225 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_279 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_254 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_6 FILLER_0_37_281 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_37_275 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_4 FILLER_0_37_290 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_37_279 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_37_322 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_37_281 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_37_293 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_37_305 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_37_317 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__fill_1 FILLER_0_37_334 (.VGND(VGND), + sky130_fd_sc_hd__decap_6 FILLER_0_37_329 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6466,71 +6497,79 @@ module tt_um_wokwi_414121715329142785 (clk, .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_8 FILLER_0_38_154 (.VGND(VGND), + sky130_fd_sc_hd__decap_4 FILLER_0_38_154 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_162 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_158 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_167 (.VGND(VGND), + sky130_fd_sc_hd__fill_1 FILLER_0_38_163 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_173 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_169 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_190 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_175 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_197 (.VPWR(VPWR), - .VGND(VGND), - .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_209 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_184 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_221 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_38_190 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_225 (.VPWR(VPWR), - .VGND(VGND), + sky130_fd_sc_hd__decap_3 FILLER_0_38_201 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_237 (.VPWR(VPWR), - .VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__decap_6 FILLER_0_38_225 (.VGND(VGND), + .VNB(VGND), .VPB(VPWR), - .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_249 (.VGND(VGND), + .VPWR(VPWR)); + sky130_fd_sc_hd__fill_1 FILLER_0_38_251 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_253 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_256 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_ef_sc_hd__decap_12 FILLER_0_38_265 (.VPWR(VPWR), + sky130_ef_sc_hd__decap_12 FILLER_0_38_268 (.VPWR(VPWR), .VGND(VGND), .VPB(VPWR), .VNB(VGND)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_277 (.VGND(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_38_281 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_38_293 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_290 (.VGND(VGND), + sky130_fd_sc_hd__decap_8 FILLER_0_38_298 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__fill_1 FILLER_0_38_307 (.VGND(VGND), + sky130_fd_sc_hd__fill_2 FILLER_0_38_306 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); - sky130_fd_sc_hd__decap_3 FILLER_0_38_332 (.VGND(VGND), + sky130_ef_sc_hd__decap_12 FILLER_0_38_309 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_ef_sc_hd__decap_12 FILLER_0_38_321 (.VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND)); + sky130_fd_sc_hd__fill_2 FILLER_0_38_333 (.VGND(VGND), .VNB(VGND), .VPB(VPWR), .VPWR(VPWR)); @@ -6539,18 +6578,17 @@ module tt_um_wokwi_414121715329142785 (clk, assign uio_oe[2] = net4; assign uio_oe[3] = net5; assign uio_oe[4] = net6; - assign uio_oe[5] = net8; - assign uio_oe[6] = net9; - assign uio_oe[7] = net10; - assign uio_out[0] = net13; - assign uio_out[1] = net14; - assign uio_out[2] = net15; - assign uio_out[3] = net16; - assign uio_out[4] = net17; - assign uio_out[5] = net18; - assign uio_out[6] = net19; - assign uio_out[7] = net20; - assign uo_out[1] = net21; + assign uio_oe[5] = net9; + assign uio_oe[6] = net10; + assign uio_oe[7] = net11; + assign uio_out[0] = net14; + assign uio_out[1] = net15; + assign uio_out[2] = net16; + assign uio_out[3] = net17; + assign uio_out[4] = net18; + assign uio_out[5] = net19; + assign uio_out[6] = net20; + assign uio_out[7] = net21; assign uo_out[2] = net22; assign uo_out[3] = net23; endmodule diff --git a/projects/tt_um_wokwi_414121715329142785/wokwi-diagram.json b/projects/tt_um_wokwi_414121715329142785/wokwi-diagram.json index 746215f6..78749c51 100644 --- a/projects/tt_um_wokwi_414121715329142785/wokwi-diagram.json +++ b/projects/tt_um_wokwi_414121715329142785/wokwi-diagram.json @@ -10,8 +10,6 @@ "left": -115.2, "attrs": { "frequency": "10000" } }, - { "type": "wokwi-gnd", "id": "pwr2", "top": -76.8, "left": 565.8, "attrs": {} }, - { "type": "wokwi-vcc", "id": "pwr1", "top": -229.64, "left": -115.2, "attrs": {} }, { "type": "wokwi-slide-switch", "id": "sw2", @@ -122,7 +120,6 @@ }, { "type": "wokwi-flip-flop-d", "id": "flop1", "top": -268.8, "left": 153.6, "attrs": {} }, { "type": "wokwi-gate-not", "id": "not5", "top": -374.4, "left": 374.4, "attrs": {} }, - { "type": "wokwi-gnd", "id": "gnd2", "top": -19.2, "left": -77.4, "attrs": {} }, { "type": "wokwi-flip-flop-d", "id": "flop2", "top": -268.8, "left": 278.4, "attrs": {} }, { "type": "wokwi-resistor", @@ -137,7 +134,8 @@ "top": -120.85, "left": -124.8, "attrs": { "value": "1000" } - } + }, + { "type": "wokwi-flip-flop-d", "id": "flop3", "top": -268.8, "left": 412.8, "attrs": {} } ], "connections": [ [ "sw2:1", "clock1:CLK", "blue", [ "h-19.2", "v-57.6" ] ], @@ -160,7 +158,10 @@ [ "ttout:EXTOUT0", "r1:1", "green", [ "v0", "h86.4", "v-316.8", "h-844.8", "v336" ] ], [ "flop1:D", "ttin:IN0", "green", [ "h-28.8", "v76.8" ] ], [ "ttin:CLK", "flop1:CLK", "green", [ "v0", "h48" ] ], - [ "ttin:CLK", "flop2:CLK", "green", [ "v0", "h172.8" ] ] + [ "ttin:CLK", "flop2:CLK", "green", [ "v0", "h172.8" ] ], + [ "flop2:Q", "flop3:D", "green", [ "v0", "h38.4" ] ], + [ "flop3:Q", "ttout:OUT1", "green", [ "v0", "h134.4", "v192", "h-336", "v-105.6" ] ], + [ "ttin:CLK", "flop3:CLK", "green", [ "v0", "h182.4" ] ] ], "dependencies": {} } \ No newline at end of file