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feat: update project tt_um_wokwi_414121715329142785 from schoeberl/tt…
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…09-sigma-delta

Commit: 8d45b556dddb8096c0340936e6a9faf639c04ead
Workflow: https://github.com/schoeberl/tt09-sigma-delta/actions/runs/11764051619
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TinyTapeoutBot authored and urish committed Nov 10, 2024
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4 changes: 2 additions & 2 deletions projects/tt_um_wokwi_414121715329142785/commit_id.json
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@@ -1,8 +1,8 @@
{
"app": "Tiny Tapeout tt09 a48b1c74",
"repo": "https://github.com/schoeberl/tt09-sigma-delta",
"commit": "c28765e4da9c2fb936e10d67680ac6fb2cc782b4",
"workflow_url": "https://github.com/schoeberl/tt09-sigma-delta/actions/runs/11760976941",
"commit": "8d45b556dddb8096c0340936e6a9faf639c04ead",
"workflow_url": "https://github.com/schoeberl/tt09-sigma-delta/actions/runs/11764051619",
"sort_id": 1731201795801,
"openlane_version": "OpenLane2 2.1.9",
"pdk_version": "open_pdks bdc9412b3e468c102d01b7cf6337be06ec6e9c9a"
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46 changes: 22 additions & 24 deletions projects/tt_um_wokwi_414121715329142785/docs/info.md
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@@ -1,41 +1,39 @@
<!---
This file is used to generate your project datasheet. Please fill in the information below and delete any unused
sections.
## How it works

You can also include images in this folder and reference them in the markdown. Each image must be less than
512 kb in size, and the combined size of all images must be less than 1 MB.
-->
Provide an analog signal at Vin (e.g., some music) and listen to the output at Vout (using an amplifier).
The circuit will probably add some noise, as it is very crude. But it went from the analog domain to digital
and then back.

## How it works
Future work should be to use that sigma-delta coded signal to do some fun audio processing.

Converting an analog signal to a pulse duration modulated digital signal
Anyone knowing how to do DSP in the sigma-delta domain?

## How to test
Connect an analog source to your design.
Connect an analog source to your design and listen to the music (output).

## External hardware

This is a sigma-delta AD converter and a DA converter.

The input is mixed with the feedback delay/inversion and uses the threshold of the DFF input as a comparator, serving as a single bit ADC.

The R and C values depend on the input signal and can be discussed and should be explored.

```
sigma delta AD converter
without external comparator:
input threshold of the DFF input is used as comparator
(not very exact but only 3 external components)
100k
___
OUT0 o--|___|--+
|
100k |
___ |
Vin o--|___|--o----------o IN0
|
---
--- 100n
|
|
---
-
___ | ____
Vin o--|___|--o----------o IN0 OUT1 o----|____|---o--------o Vout
| |
--- ---
--- 100n ---
| |
| |
--- ---
- -
```
8 changes: 4 additions & 4 deletions projects/tt_um_wokwi_414121715329142785/info.yaml
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@@ -1,10 +1,10 @@
# Tiny Tapeout project information (Wokwi project)
project:
wokwi_id: 414121715329142785 # Set this to the ID of your Wokwi project (the number from the project's URL)
title: "Sigma Delta ADC" # Project title
title: "Sigma-Delta ADC" # Project title
author: "Martin Schoeberl" # Your name
discord: "" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Analog to digital converter" # One line description of what your project does
discord: "maybe I do not want to make this public ;-)" # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
description: "Analog to digital converter - and back" # One-line description of what your project does
language: "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
clock_hz: 50000000 # Clock frequency in Hz (or 0 if not applicable)

Expand All @@ -26,7 +26,7 @@ pinout:

# Outputs
uo[0]: "OUT0"
uo[1]: ""
uo[1]: "OUT1"
uo[2]: ""
uo[3]: ""
uo[4]: ""
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154 changes: 77 additions & 77 deletions projects/tt_um_wokwi_414121715329142785/stats/metrics.csv
Original file line number Diff line number Diff line change
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Expand All @@ -31,10 +31,10 @@ timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
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Expand All @@ -48,10 +48,10 @@ timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
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Expand All @@ -100,40 +100,40 @@ timing__drv__floating__pins,0
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Expand All @@ -144,15 +144,15 @@ timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
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Expand All @@ -163,15 +163,15 @@ timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
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Expand All @@ -182,15 +182,15 @@ timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
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Expand All @@ -201,15 +201,15 @@ timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
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Expand All @@ -220,15 +220,15 @@ timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
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Expand All @@ -239,19 +239,19 @@ timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
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timing__unannotated_net__count,44
timing__unannotated_net_filtered__count,0
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79996
design_powergrid__voltage__worst__net:VPWR__corner:nom_tt_025C_1v80,1.79997
design_powergrid__drop__average__net:VPWR__corner:nom_tt_025C_1v80,1.8
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000420736
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000542823
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,6.63304E-7
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000542823
design_powergrid__drop__worst__net:VPWR__corner:nom_tt_025C_1v80,0.0000337614
design_powergrid__voltage__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000490428
design_powergrid__drop__average__net:VGND__corner:nom_tt_025C_1v80,7.8008E-7
design_powergrid__drop__worst__net:VGND__corner:nom_tt_025C_1v80,0.0000490428
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
ir__drop__avg,7.06999999999999964830541508697958619222845300100743770599365234375E-7
ir__drop__worst,0.0000421000000000000001065987575987747959516127593815326690673828125
ir__drop__avg,7.490000000000000497508392989509662385216870461590588092803955078125E-7
ir__drop__worst,0.0000338000000000000016468597319185818150799605064094066619873046875
magic__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
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