From 180374a804ac2b053034f68a2b0fcb706894c745 Mon Sep 17 00:00:00 2001 From: htfab Date: Wed, 5 Jun 2024 00:25:33 +0200 Subject: [PATCH] docs(tt_um_htfab_fprn): add more details and a diagram --- projects/tt_um_htfab_fprn/docs/circuit.svg | 2306 ++++++++++++++++++++ projects/tt_um_htfab_fprn/docs/info.md | 48 +- projects/tt_um_htfab_fprn/info.yaml | 34 +- 3 files changed, 2361 insertions(+), 27 deletions(-) create mode 100644 projects/tt_um_htfab_fprn/docs/circuit.svg diff --git a/projects/tt_um_htfab_fprn/docs/circuit.svg b/projects/tt_um_htfab_fprn/docs/circuit.svg new file mode 100644 index 0000000..81dd386 --- /dev/null +++ b/projects/tt_um_htfab_fprn/docs/circuit.svg @@ -0,0 +1,2306 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AP + HI0 + HI1 + HI2 + VI0 + VI1 + VI2 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + HR02 + HS02 + HL02 + VR22 + VS22 + VL22 + + + diff --git a/projects/tt_um_htfab_fprn/docs/info.md b/projects/tt_um_htfab_fprn/docs/info.md index 1b7ff98..ad62ffd 100644 --- a/projects/tt_um_htfab_fprn/docs/info.md +++ b/projects/tt_um_htfab_fprn/docs/info.md @@ -2,20 +2,48 @@ A few resistors and switches are wired up in a matrix pattern. Switches are implemented as pass gates controlled by latches that keep the configuration. -Can be used as a makeshift DAC by controlling the "bitstream". +The network can be used as a makeshift DAC by controlling the "bitstream". +![Circuit diagram](circuit.svg) + +Matrix cells can be selected using the `H_GATE_i` and `V_GATE_j` inputs: + +* `H_GATE_0` = `uio_in[5]` +* `H_GATE_1` = `uio_in[2]` +* `H_GATE_2` = `ui_in[1]` +* `V_GATE_0` = `uio_in[6]` +* `V_GATE_1` = `uio_in[3]` +* `V_GATE_2` = `uio_in[0]` + +When the inputs `H_GATE_i` and `V_GATE_j` are on, the latches in the +cell _ij_ become transparent and configure the pass gates as follows: + +* `HR_ij` ← `HD_RES` = `ui_in[4]` +* `HS_ij` ← `HD_SHORT` = `ui_in[3]` +* `HL_ij` ← `HD_LINE` = `ui_in[2]` +* `VR_ij` ← `VD_RES` = `ui_in[7]` +* `VS_ij` ← `VD_SHORT` = `ui_in[6]` +* `VL_ij` ← `VD_LINE` = `ui_in[5]` + +Once `H_GATE_i` or `V_GATE_j` is off again, the latches close and the +pass gates keep their configuration. Thus a new cell with different +_i_ or _j_ can be configured using the same inputs. + ## How to test -First configure the network. -Each cell of the 3×3 matrix is controlled by 6 bits: -`VD_SHORT`, `VD_NEXT`, `VD_LINE`, `HD_SHORT`, `HD_NEXT` and `HD_LINE`. -Set these bits, then briefly turn on `H_GATE_i` and `V_GATE_j` to -save this configuration in the latches. -Continue for the other cells of the matrix. +After the network is configured as above, manipulate the digital inputs +`H_INPUT_i` and `V_INPUT_j` to apply 0 V or 1.8 V at the respective nodes +of the network: + +* `HI_0` ← `H_INPUT_0` = `ui_in[0]` +* `HI_1` ← `H_INPUT_1` = `rst_n` +* `HI_2` ← `H_INPUT_2` = `clk` +* `VI_0` ← `V_INPUT_0` = `uio_in[7]` +* `VI_1` ← `V_INPUT_1` = `uio_in[4]` +* `VI_2` ← `V_INPUT_2` = `uio_in[1]` -Once the network is configured, manipulate the digital inputs -`H_INPUT_i` and `V_INPUT_j` and read the voltage at the analog output. +The voltage can be measured externally at the analog pin `AP` = `ua[0]`. ## External hardware -Multimeter or microcontroller with ADC to measure voltages. +Multimeter (or microcontroller with ADC) to measure the output voltage. diff --git a/projects/tt_um_htfab_fprn/info.yaml b/projects/tt_um_htfab_fprn/info.yaml index f6f7687..84d47bc 100644 --- a/projects/tt_um_htfab_fprn/info.yaml +++ b/projects/tt_um_htfab_fprn/info.yaml @@ -23,14 +23,14 @@ project: # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins. pinout: # Inputs - ui[0]: "H_INPUT_0" - ui[1]: "H_GATE_2" - ui[2]: "HD_LINE" - ui[3]: "HD_SHORT" - ui[4]: "HD_RES" - ui[5]: "VD_LINE" - ui[6]: "VD_SHORT" - ui[7]: "VD_RES" + ui[0]: "`H_INPUT_0`" + ui[1]: "`H_GATE_2`" + ui[2]: "`HD_LINE`" + ui[3]: "`HD_SHORT`" + ui[4]: "`HD_RES`" + ui[5]: "`VD_LINE`" + ui[6]: "`VD_SHORT`" + ui[7]: "`VD_RES`" # Outputs uo[0]: "" @@ -43,17 +43,17 @@ pinout: uo[7]: "" # Bidirectional pins - uio[0]: "V_GATE_2" - uio[1]: "V_INPUT_2" - uio[2]: "H_GATE_1" - uio[3]: "V_GATE_1" - uio[4]: "V_INPUT_1" - uio[5]: "H_GATE_0" - uio[6]: "V_GATE_0" - uio[7]: "V_INPUT_0" + uio[0]: "`V_GATE_2`" + uio[1]: "`V_INPUT_2`" + uio[2]: "`H_GATE_1`" + uio[3]: "`V_GATE_1`" + uio[4]: "`V_INPUT_1`" + uio[5]: "`H_GATE_0`" + uio[6]: "`V_GATE_0`" + uio[7]: "`V_INPUT_0`" # Analog pins - make sure to also set "analog_pins" above, else the pins won't be connected - ua[0]: "ANALOG_PIN" + ua[0]: "`ANALOG_PIN`" ua[1]: "" ua[2]: "" ua[3]: ""