docs(tt_um_dvxf_dj8v_dac): Update info.md #246
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name: formal | |
on: | |
workflow_dispatch: | |
push: | |
# Don't run on project submissions: | |
branches-ignore: | |
- projects/tt_um_* | |
pull_request: | |
# Don't run on project submissions: | |
paths-ignore: | |
- projects/tt_um_*/** | |
jobs: | |
formal: | |
runs-on: ubuntu-latest | |
steps: | |
- name: checkout repo | |
uses: actions/checkout@v4 | |
with: | |
submodules: recursive | |
- name: install oss-cad-suite (cocotb / iverilog) | |
uses: YosysHQ/setup-oss-cad-suite@v3 | |
with: | |
github-token: ${{ secrets.GITHUB_TOKEN }} | |
- run: | | |
yosys --version | |
- name: Python requirements | |
run: pip3 install -r tt-multiplexer/py/requirements.txt | |
- name: formal tristate | |
working-directory: tt-multiplexer | |
run: make formal_tristate | |
- name: formal tristate | |
working-directory: tt-multiplexer | |
run: make formal_connectivity |