diff --git a/BUILD b/BUILD
index 3437e973..873e0f9c 100644
--- a/BUILD
+++ b/BUILD
@@ -93,7 +93,7 @@ build_openroad(
             "CORE_UTILIZATION=3",
             "RTLMP_FLOW=True",
             "CORE_MARGIN=2",
-            "MACRO_PLACE_HALO=10 10",
+            "MACRO_PLACE_HALO=30 30",
         ],
         "place": [
             "PLACE_DENSITY=0.20",
diff --git a/test/constraints-top.sdc b/test/constraints-top.sdc
index 86e7240a..71d10c0f 100644
--- a/test/constraints-top.sdc
+++ b/test/constraints-top.sdc
@@ -1,21 +1,5 @@
-set sdc_version 2.0
-
-set clk_period 8500
-
-set clk_name  clock
+set clk_name clock
 set clk_port_name clock
-set clk_in_pct 0.20
-set clk_out_pct 0.2
-
-create_clock -name $clk_name       -period $clk_period -waveform [list 0 [expr $clk_period/2]] [get_ports $clk_port_name]
-set_clock_uncertainty 10 [get_clocks $clk_name]
-
-create_clock -name ${clk_name}_vir -period $clk_period -waveform [list 0 [expr $clk_period/2]]
-set_clock_uncertainty  10 [get_clocks ${clk_name}_vir]
-set_clock_latency     3300 [get_clocks ${clk_name}_vir]       ;# Matching real clock latency
-
-set clk_port [get_ports $clk_port_name]
-set non_clock_inputs [lsearch -inline -all -not -exact [all_inputs] $clk_port]
+set clk_period 2000
 
-set_input_delay  [expr $clk_period * $clk_in_pct] -clock ${clk_name}_vir $non_clock_inputs 
-set_output_delay [expr $clk_period * $clk_out_pct] -clock ${clk_name}_vir [all_outputs]
+source $env(PLATFORM_DIR)/constraints.sdc