Silly question about detailed router DRC violations

[oharboe]

Are DRC violations like timing closure errors: the tools know what it takes to avoid them, but isn't always able to find a solution?

I.e. if I improve my Verilog, I expect timing violations to go away.

Are DRC errors the same in that regard?

[maliberty]

Yes the router tries to eliminate them but can't always. However fixing them generally isn't done at the Verilog level. Usually you need to tweak placement density, macro placement, pin placement, layer utilization, or some other physical parameters.