Long running timing driven synthesis and dependencies

[oharboe]

I have a synthesis operation that runs for ca. 2 hours.

If I change the .sdc file, then synthesis has to be re-run.

Can the dependency be narrowed more down?

Do all changes to the .sdc file requre re-synthesis?

Under what exact circumstances is it that synthesis has to be re-run?

[maliberty]

Probably most changes could affect the output - anything that changes timing or constants would qualify. Is there some particular change you have in mind?

[oharboe]

I was thinking if only e.g. the clock period in the .sdc file(extracted automatically w/grep) affects synthesis, then I could skip synthesis upon other .sdc changes.

[rovinski]

If you want to do that for your case, I see nothing wrong with it. I'm not sure how you could program that into the flow, though.

[oharboe]

I have a wafer thin Bazel flow on top of ORFS, so straightforward...

The main thing I need to know is exactly what the dependencies are, which variables...

[rovinski]

A "complete" solution would require a full SDC parser. A "good enough" solution indeed only needs to look at the clock period because that's the only design-dependent variable passed to Yosys/ABC.